blob: e885a85ce65c3f96bfab16646a855a5b1eb9bc65 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Wang Huan8ce6bec2014-09-05 13:52:34 +08002/*
3 * Copyright 2014 Freescale Semiconductor, Inc.
Wang Huan8ce6bec2014-09-05 13:52:34 +08004 */
5
Tom Rini414e4042024-04-30 07:35:58 -06006#include <config.h>
Simon Glass85d65312019-12-28 10:44:58 -07007#include <clock_legacy.h>
Simon Glass3ba929a2020-10-30 21:38:53 -06008#include <asm/global_data.h>
Wang Huan8ce6bec2014-09-05 13:52:34 +08009#include <asm/io.h>
10#include <asm/arch/immap_ls102xa.h>
11#include <asm/arch/clock.h>
12#include <fsl_ifc.h>
13
14DECLARE_GLOBAL_DATA_PTR;
15
Wang Huan8ce6bec2014-09-05 13:52:34 +080016void get_sys_info(struct sys_info *sys_info)
17{
Tom Rini376b88a2022-10-28 20:27:13 -040018 struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
19 struct ccsr_clk *clk = (void *)(CFG_SYS_FSL_LS1_CLK_ADDR);
Wang Huan8ce6bec2014-09-05 13:52:34 +080020 unsigned int cpu;
21 const u8 core_cplx_pll[6] = {
22 [0] = 0, /* CC1 PPL / 1 */
23 [1] = 0, /* CC1 PPL / 2 */
24 [4] = 1, /* CC2 PPL / 1 */
25 [5] = 1, /* CC2 PPL / 2 */
26 };
27
28 const u8 core_cplx_pll_div[6] = {
29 [0] = 1, /* CC1 PPL / 1 */
30 [1] = 2, /* CC1 PPL / 2 */
31 [4] = 1, /* CC2 PPL / 1 */
32 [5] = 2, /* CC2 PPL / 2 */
33 };
34
35 uint i;
36 uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
37 uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
Tom Rini8c70baa2021-12-14 13:36:40 -050038 unsigned long sysclk = get_board_sys_clk();
Wang Huan8ce6bec2014-09-05 13:52:34 +080039
40 sys_info->freq_systembus = sysclk;
Tom Rinif7246c22021-08-21 13:50:17 -040041#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
42 sys_info->freq_ddrbus = get_board_ddr_clk();
Wang Huan8ce6bec2014-09-05 13:52:34 +080043#else
44 sys_info->freq_ddrbus = sysclk;
45#endif
46
47 sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >>
48 RCWSR0_SYS_PLL_RAT_SHIFT) & RCWSR0_SYS_PLL_RAT_MASK;
49 sys_info->freq_ddrbus *= (in_be32(&gur->rcwsr[0]) >>
50 RCWSR0_MEM_PLL_RAT_SHIFT) & RCWSR0_MEM_PLL_RAT_MASK;
51
52 for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
53 ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f;
54 if (ratio[i] > 4)
55 freq_c_pll[i] = sysclk * ratio[i];
56 else
57 freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
58 }
59
60 for (cpu = 0; cpu < CONFIG_MAX_CPUS; cpu++) {
61 u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
62 & 0xf;
63 u32 cplx_pll = core_cplx_pll[c_pll_sel];
64
65 sys_info->freq_processor[cpu] =
66 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
67 }
68
69#if defined(CONFIG_FSL_IFC)
Prabhakar Kushwaha79198462017-02-02 15:01:37 +053070 sys_info->freq_localbus = sys_info->freq_systembus;
Wang Huan8ce6bec2014-09-05 13:52:34 +080071#endif
72}
73
74int get_clocks(void)
75{
76 struct sys_info sys_info;
77
78 get_sys_info(&sys_info);
79 gd->cpu_clk = sys_info.freq_processor[0];
80 gd->bus_clk = sys_info.freq_systembus;
81 gd->mem_clk = sys_info.freq_ddrbus * 2;
82
83#if defined(CONFIG_FSL_ESDHC)
84 gd->arch.sdhc_clk = gd->bus_clk;
85#endif
86
87 return 0;
88}
89
90ulong get_bus_freq(ulong dummy)
91{
92 return gd->bus_clk;
93}
94
95ulong get_ddr_freq(ulong dummy)
96{
97 return gd->mem_clk;
98}
99
100int get_serial_clock(void)
101{
102 return gd->bus_clk / 2;
103}
104
105unsigned int mxc_get_clock(enum mxc_clock clk)
106{
107 switch (clk) {
108 case MXC_I2C_CLK:
109 return get_bus_freq(0) / 2;
Wang Huan8ce6bec2014-09-05 13:52:34 +0800110 case MXC_DSPI_CLK:
111 return get_bus_freq(0) / 2;
112 case MXC_UART_CLK:
113 return get_bus_freq(0) / 2;
114 default:
115 printf("Unsupported clock\n");
116 }
117 return 0;
118}