blob: c9d5cb6d3e5a86937299205779fcba563ab7fc99 [file] [log] [blame]
Miquel Raynalf3b43502018-05-15 11:57:08 +02001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
Ilias Apalodimasf4e05902020-11-11 11:18:10 +02003 * Defines APIs and structures that allow software to interact with a
4 * TPM2 device
5 *
6 * Copyright (c) 2020 Linaro
Miquel Raynalf3b43502018-05-15 11:57:08 +02007 * Copyright (c) 2018 Bootlin
Ilias Apalodimasf4e05902020-11-11 11:18:10 +02008 *
9 * https://trustedcomputinggroup.org/resource/tss-overview-common-structures-specification/
10 *
Miquel Raynalf3b43502018-05-15 11:57:08 +020011 * Author: Miquel Raynal <miquel.raynal@bootlin.com>
12 */
13
14#ifndef __TPM_V2_H
15#define __TPM_V2_H
16
17#include <tpm-common.h>
18
Simon Glass3ba929a2020-10-30 21:38:53 -060019struct udevice;
20
Miquel Raynalf3b43502018-05-15 11:57:08 +020021#define TPM2_DIGEST_LEN 32
22
Ilias Apalodimascae28ef2020-11-30 11:47:39 +020023#define TPM2_SHA1_DIGEST_SIZE 20
24#define TPM2_SHA256_DIGEST_SIZE 32
25#define TPM2_SHA384_DIGEST_SIZE 48
26#define TPM2_SHA512_DIGEST_SIZE 64
27#define TPM2_SM3_256_DIGEST_SIZE 32
28
Ilias Apalodimasf4e05902020-11-11 11:18:10 +020029#define TPM2_MAX_PCRS 32
30#define TPM2_PCR_SELECT_MAX ((TPM2_MAX_PCRS + 7) / 8)
31#define TPM2_MAX_CAP_BUFFER 1024
32#define TPM2_MAX_TPM_PROPERTIES ((TPM2_MAX_CAP_BUFFER - sizeof(u32) /* TPM2_CAP */ - \
33 sizeof(u32)) / sizeof(struct tpms_tagged_property))
34
Simon Glassca31f072021-07-18 14:18:03 -060035#define TPM2_HDR_LEN 10
36
Ilias Apalodimasf4e05902020-11-11 11:18:10 +020037/*
38 * We deviate from this draft of the specification by increasing the value of
39 * TPM2_NUM_PCR_BANKS from 3 to 16 to ensure compatibility with TPM2
40 * implementations that have enabled a larger than typical number of PCR
41 * banks. This larger value for TPM2_NUM_PCR_BANKS is expected to be included
42 * in a future revision of the specification.
43 */
44#define TPM2_NUM_PCR_BANKS 16
45
46/* Definition of (UINT32) TPM2_CAP Constants */
47#define TPM2_CAP_PCRS 0x00000005U
48#define TPM2_CAP_TPM_PROPERTIES 0x00000006U
49
50/* Definition of (UINT32) TPM2_PT Constants */
51#define TPM2_PT_GROUP (u32)(0x00000100)
52#define TPM2_PT_FIXED (u32)(TPM2_PT_GROUP * 1)
53#define TPM2_PT_MANUFACTURER (u32)(TPM2_PT_FIXED + 5)
54#define TPM2_PT_PCR_COUNT (u32)(TPM2_PT_FIXED + 18)
55#define TPM2_PT_MAX_COMMAND_SIZE (u32)(TPM2_PT_FIXED + 30)
56#define TPM2_PT_MAX_RESPONSE_SIZE (u32)(TPM2_PT_FIXED + 31)
57
Heinrich Schuchardt92c540d2021-04-21 12:24:29 +020058/*
59 * event types, cf.
60 * "TCG Server Management Domain Firmware Profile Specification",
61 * rev 1.00, 2020-05-01
62 */
63#define EV_POST_CODE ((u32)0x00000001)
64#define EV_NO_ACTION ((u32)0x00000003)
65#define EV_SEPARATOR ((u32)0x00000004)
66#define EV_ACTION ((u32)0x00000005)
67#define EV_TAG ((u32)0x00000006)
68#define EV_S_CRTM_CONTENTS ((u32)0x00000007)
69#define EV_S_CRTM_VERSION ((u32)0x00000008)
70#define EV_CPU_MICROCODE ((u32)0x00000009)
71#define EV_PLATFORM_CONFIG_FLAGS ((u32)0x0000000A)
72#define EV_TABLE_OF_DEVICES ((u32)0x0000000B)
73#define EV_COMPACT_HASH ((u32)0x0000000C)
Ilias Apalodimascae28ef2020-11-30 11:47:39 +020074
Masahisa Kojima70be5a62021-05-26 12:09:58 +090075/*
76 * event types, cf.
77 * "TCG PC Client Platform Firmware Profile Specification", Family "2.0"
Masahisa Kojima8173cd42021-08-13 16:12:40 +090078 * Level 00 Version 1.05 Revision 23, May 7, 2021
Masahisa Kojima70be5a62021-05-26 12:09:58 +090079 */
80#define EV_EFI_EVENT_BASE ((u32)0x80000000)
81#define EV_EFI_VARIABLE_DRIVER_CONFIG ((u32)0x80000001)
82#define EV_EFI_VARIABLE_BOOT ((u32)0x80000002)
83#define EV_EFI_BOOT_SERVICES_APPLICATION ((u32)0x80000003)
84#define EV_EFI_BOOT_SERVICES_DRIVER ((u32)0x80000004)
85#define EV_EFI_RUNTIME_SERVICES_DRIVER ((u32)0x80000005)
86#define EV_EFI_GPT_EVENT ((u32)0x80000006)
87#define EV_EFI_ACTION ((u32)0x80000007)
88#define EV_EFI_PLATFORM_FIRMWARE_BLOB ((u32)0x80000008)
89#define EV_EFI_HANDOFF_TABLES ((u32)0x80000009)
Masahisa Kojima8173cd42021-08-13 16:12:40 +090090#define EV_EFI_PLATFORM_FIRMWARE_BLOB2 ((u32)0x8000000A)
91#define EV_EFI_HANDOFF_TABLES2 ((u32)0x8000000B)
92#define EV_EFI_VARIABLE_BOOT2 ((u32)0x8000000C)
Masahisa Kojima70be5a62021-05-26 12:09:58 +090093#define EV_EFI_HCRTM_EVENT ((u32)0x80000010)
94#define EV_EFI_VARIABLE_AUTHORITY ((u32)0x800000E0)
Masahisa Kojima8173cd42021-08-13 16:12:40 +090095#define EV_EFI_SPDM_FIRMWARE_BLOB ((u32)0x800000E1)
96#define EV_EFI_SPDM_FIRMWARE_CONFIG ((u32)0x800000E2)
97
98#define EFI_CALLING_EFI_APPLICATION \
99 "Calling EFI Application from Boot Option"
100#define EFI_RETURNING_FROM_EFI_APPLICATION \
101 "Returning from EFI Application from Boot Option"
102#define EFI_EXIT_BOOT_SERVICES_INVOCATION \
103 "Exit Boot Services Invocation"
104#define EFI_EXIT_BOOT_SERVICES_FAILED \
105 "Exit Boot Services Returned with Failure"
106#define EFI_EXIT_BOOT_SERVICES_SUCCEEDED \
107 "Exit Boot Services Returned with Success"
Etienne Carriereb9064352023-02-16 17:29:48 +0100108#define EFI_DTB_EVENT_STRING \
109 "DTB DATA"
Masahisa Kojima70be5a62021-05-26 12:09:58 +0900110
Ilias Apalodimasf4e05902020-11-11 11:18:10 +0200111/* TPMS_TAGGED_PROPERTY Structure */
112struct tpms_tagged_property {
113 u32 property;
114 u32 value;
115} __packed;
116
117/* TPMS_PCR_SELECTION Structure */
118struct tpms_pcr_selection {
119 u16 hash;
120 u8 size_of_select;
121 u8 pcr_select[TPM2_PCR_SELECT_MAX];
122} __packed;
123
124/* TPML_PCR_SELECTION Structure */
125struct tpml_pcr_selection {
126 u32 count;
127 struct tpms_pcr_selection selection[TPM2_NUM_PCR_BANKS];
128} __packed;
129
130/* TPML_TAGGED_TPM_PROPERTY Structure */
131struct tpml_tagged_tpm_property {
132 u32 count;
133 struct tpms_tagged_property tpm_property[TPM2_MAX_TPM_PROPERTIES];
134} __packed;
135
136/* TPMU_CAPABILITIES Union */
137union tpmu_capabilities {
138 /*
139 * Non exhaustive. Only added the structs needed for our
140 * current code
141 */
142 struct tpml_pcr_selection assigned_pcr;
143 struct tpml_tagged_tpm_property tpm_properties;
144} __packed;
145
146/* TPMS_CAPABILITY_DATA Structure */
147struct tpms_capability_data {
148 u32 capability;
149 union tpmu_capabilities data;
150} __packed;
151
Miquel Raynalf3b43502018-05-15 11:57:08 +0200152/**
Ilias Apalodimascae28ef2020-11-30 11:47:39 +0200153 * SHA1 Event Log Entry Format
154 *
155 * @pcr_index: PCRIndex event extended to
156 * @event_type: Type of event (see EFI specs)
157 * @digest: Value extended into PCR index
158 * @event_size: Size of event
159 * @event: Event data
160 */
161struct tcg_pcr_event {
162 u32 pcr_index;
163 u32 event_type;
164 u8 digest[TPM2_SHA1_DIGEST_SIZE];
165 u32 event_size;
166 u8 event[];
167} __packed;
168
169/**
170 * Definition of TPMU_HA Union
171 */
Eddie James90b6c862023-10-24 10:43:47 -0500172union tpmu_ha {
Ilias Apalodimascae28ef2020-11-30 11:47:39 +0200173 u8 sha1[TPM2_SHA1_DIGEST_SIZE];
174 u8 sha256[TPM2_SHA256_DIGEST_SIZE];
175 u8 sm3_256[TPM2_SM3_256_DIGEST_SIZE];
176 u8 sha384[TPM2_SHA384_DIGEST_SIZE];
177 u8 sha512[TPM2_SHA512_DIGEST_SIZE];
178} __packed;
179
180/**
181 * Definition of TPMT_HA Structure
182 *
183 * @hash_alg: Hash algorithm defined in enum tpm2_algorithms
184 * @digest: Digest value for a given algorithm
185 */
186struct tpmt_ha {
187 u16 hash_alg;
Eddie James90b6c862023-10-24 10:43:47 -0500188 union tpmu_ha digest;
Ilias Apalodimascae28ef2020-11-30 11:47:39 +0200189} __packed;
190
191/**
192 * Definition of TPML_DIGEST_VALUES Structure
193 *
194 * @count: Number of algorithms supported by hardware
195 * @digests: struct for algorithm id and hash value
196 */
197struct tpml_digest_values {
198 u32 count;
199 struct tpmt_ha digests[TPM2_NUM_PCR_BANKS];
200} __packed;
201
202/**
203 * Crypto Agile Log Entry Format
204 *
205 * @pcr_index: PCRIndex event extended to
206 * @event_type: Type of event
207 * @digests: List of digestsextended to PCR index
208 * @event_size: Size of the event data
209 * @event: Event data
210 */
211struct tcg_pcr_event2 {
212 u32 pcr_index;
213 u32 event_type;
214 struct tpml_digest_values digests;
215 u32 event_size;
216 u8 event[];
217} __packed;
218
219/**
Eddie James8ed7bb32023-10-24 10:43:49 -0500220 * struct TCG_EfiSpecIdEventAlgorithmSize - hashing algorithm information
221 *
222 * @algorithm_id: algorithm defined in enum tpm2_algorithms
223 * @digest_size: size of the algorithm
224 */
225struct tcg_efi_spec_id_event_algorithm_size {
226 u16 algorithm_id;
227 u16 digest_size;
228} __packed;
229
230#define TCG_EFI_SPEC_ID_EVENT_SIGNATURE_03 "Spec ID Event03"
231#define TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MAJOR_TPM2 2
232#define TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_MINOR_TPM2 0
233#define TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_ERRATA_TPM2 2
234
235/**
236 * struct TCG_EfiSpecIDEventStruct - content of the event log header
237 *
238 * @signature: signature, set to Spec ID Event03
239 * @platform_class: class defined in TCG ACPI Specification
240 * Client Common Header.
241 * @spec_version_minor: minor version
242 * @spec_version_major: major version
243 * @spec_version_errata: major version
244 * @uintn_size: size of the efi_uintn_t fields used in various
245 * data structures used in this specification.
246 * 0x01 indicates u32 and 0x02 indicates u64
247 * @number_of_algorithms: hashing algorithms used in this event log
248 * @digest_sizes: array of number_of_algorithms pairs
249 * 1st member defines the algorithm id
250 * 2nd member defines the algorithm size
251 */
252struct tcg_efi_spec_id_event {
253 u8 signature[16];
254 u32 platform_class;
255 u8 spec_version_minor;
256 u8 spec_version_major;
257 u8 spec_errata;
258 u8 uintn_size;
259 u32 number_of_algorithms;
260 struct tcg_efi_spec_id_event_algorithm_size digest_sizes[];
261} __packed;
262
263/**
Miquel Raynalf3b43502018-05-15 11:57:08 +0200264 * TPM2 Structure Tags for command/response buffers.
265 *
266 * @TPM2_ST_NO_SESSIONS: the command does not need an authentication.
267 * @TPM2_ST_SESSIONS: the command needs an authentication.
268 */
269enum tpm2_structures {
270 TPM2_ST_NO_SESSIONS = 0x8001,
271 TPM2_ST_SESSIONS = 0x8002,
272};
273
274/**
275 * TPM2 type of boolean.
276 */
277enum tpm2_yes_no {
278 TPMI_YES = 1,
279 TPMI_NO = 0,
280};
281
282/**
283 * TPM2 startup values.
284 *
285 * @TPM2_SU_CLEAR: reset the internal state.
286 * @TPM2_SU_STATE: restore saved state (if any).
287 */
288enum tpm2_startup_types {
289 TPM2_SU_CLEAR = 0x0000,
290 TPM2_SU_STATE = 0x0001,
291};
292
293/**
294 * TPM2 permanent handles.
295 *
296 * @TPM2_RH_OWNER: refers to the 'owner' hierarchy.
297 * @TPM2_RS_PW: indicates a password.
298 * @TPM2_RH_LOCKOUT: refers to the 'lockout' hierarchy.
299 * @TPM2_RH_ENDORSEMENT: refers to the 'endorsement' hierarchy.
300 * @TPM2_RH_PLATFORM: refers to the 'platform' hierarchy.
301 */
302enum tpm2_handles {
303 TPM2_RH_OWNER = 0x40000001,
304 TPM2_RS_PW = 0x40000009,
305 TPM2_RH_LOCKOUT = 0x4000000A,
306 TPM2_RH_ENDORSEMENT = 0x4000000B,
307 TPM2_RH_PLATFORM = 0x4000000C,
308};
309
310/**
311 * TPM2 command codes used at the beginning of a buffer, gives the command.
312 *
313 * @TPM2_CC_STARTUP: TPM2_Startup().
314 * @TPM2_CC_SELF_TEST: TPM2_SelfTest().
315 * @TPM2_CC_CLEAR: TPM2_Clear().
316 * @TPM2_CC_CLEARCONTROL: TPM2_ClearControl().
317 * @TPM2_CC_HIERCHANGEAUTH: TPM2_HierarchyChangeAuth().
318 * @TPM2_CC_PCR_SETAUTHPOL: TPM2_PCR_SetAuthPolicy().
319 * @TPM2_CC_DAM_RESET: TPM2_DictionaryAttackLockReset().
320 * @TPM2_CC_DAM_PARAMETERS: TPM2_DictionaryAttackParameters().
321 * @TPM2_CC_GET_CAPABILITY: TPM2_GetCapibility().
Dhananjay Phadke7a2cf2e2020-06-04 16:43:59 -0700322 * @TPM2_CC_GET_RANDOM: TPM2_GetRandom().
Miquel Raynalf3b43502018-05-15 11:57:08 +0200323 * @TPM2_CC_PCR_READ: TPM2_PCR_Read().
324 * @TPM2_CC_PCR_EXTEND: TPM2_PCR_Extend().
325 * @TPM2_CC_PCR_SETAUTHVAL: TPM2_PCR_SetAuthValue().
326 */
327enum tpm2_command_codes {
328 TPM2_CC_STARTUP = 0x0144,
329 TPM2_CC_SELF_TEST = 0x0143,
Simon Glass77759db2021-02-06 14:23:42 -0700330 TPM2_CC_HIER_CONTROL = 0x0121,
Miquel Raynalf3b43502018-05-15 11:57:08 +0200331 TPM2_CC_CLEAR = 0x0126,
332 TPM2_CC_CLEARCONTROL = 0x0127,
333 TPM2_CC_HIERCHANGEAUTH = 0x0129,
Simon Glass713c58a2021-02-06 14:23:39 -0700334 TPM2_CC_NV_DEFINE_SPACE = 0x012a,
Miquel Raynal0b864f62018-05-15 11:57:20 +0200335 TPM2_CC_PCR_SETAUTHPOL = 0x012C,
Simon Glass3d930ed2021-02-06 14:23:40 -0700336 TPM2_CC_NV_WRITE = 0x0137,
Simon Glasse9d3d592021-02-06 14:23:41 -0700337 TPM2_CC_NV_WRITELOCK = 0x0138,
Miquel Raynalf3b43502018-05-15 11:57:08 +0200338 TPM2_CC_DAM_RESET = 0x0139,
339 TPM2_CC_DAM_PARAMETERS = 0x013A,
Simon Glass5ff3f162018-10-01 11:55:17 -0600340 TPM2_CC_NV_READ = 0x014E,
Miquel Raynalf3b43502018-05-15 11:57:08 +0200341 TPM2_CC_GET_CAPABILITY = 0x017A,
Dhananjay Phadke7a2cf2e2020-06-04 16:43:59 -0700342 TPM2_CC_GET_RANDOM = 0x017B,
Miquel Raynalf3b43502018-05-15 11:57:08 +0200343 TPM2_CC_PCR_READ = 0x017E,
344 TPM2_CC_PCR_EXTEND = 0x0182,
Miquel Raynal0b864f62018-05-15 11:57:20 +0200345 TPM2_CC_PCR_SETAUTHVAL = 0x0183,
Miquel Raynalf3b43502018-05-15 11:57:08 +0200346};
347
348/**
349 * TPM2 return codes.
350 */
351enum tpm2_return_codes {
352 TPM2_RC_SUCCESS = 0x0000,
353 TPM2_RC_BAD_TAG = 0x001E,
354 TPM2_RC_FMT1 = 0x0080,
355 TPM2_RC_HASH = TPM2_RC_FMT1 + 0x0003,
356 TPM2_RC_VALUE = TPM2_RC_FMT1 + 0x0004,
357 TPM2_RC_SIZE = TPM2_RC_FMT1 + 0x0015,
358 TPM2_RC_BAD_AUTH = TPM2_RC_FMT1 + 0x0022,
359 TPM2_RC_HANDLE = TPM2_RC_FMT1 + 0x000B,
360 TPM2_RC_VER1 = 0x0100,
361 TPM2_RC_INITIALIZE = TPM2_RC_VER1 + 0x0000,
362 TPM2_RC_FAILURE = TPM2_RC_VER1 + 0x0001,
363 TPM2_RC_DISABLED = TPM2_RC_VER1 + 0x0020,
364 TPM2_RC_AUTH_MISSING = TPM2_RC_VER1 + 0x0025,
365 TPM2_RC_COMMAND_CODE = TPM2_RC_VER1 + 0x0043,
366 TPM2_RC_AUTHSIZE = TPM2_RC_VER1 + 0x0044,
367 TPM2_RC_AUTH_CONTEXT = TPM2_RC_VER1 + 0x0045,
Simon Glass77759db2021-02-06 14:23:42 -0700368 TPM2_RC_NV_DEFINED = TPM2_RC_VER1 + 0x004c,
Miquel Raynalf3b43502018-05-15 11:57:08 +0200369 TPM2_RC_NEEDS_TEST = TPM2_RC_VER1 + 0x0053,
370 TPM2_RC_WARN = 0x0900,
371 TPM2_RC_TESTING = TPM2_RC_WARN + 0x000A,
372 TPM2_RC_REFERENCE_H0 = TPM2_RC_WARN + 0x0010,
373 TPM2_RC_LOCKOUT = TPM2_RC_WARN + 0x0021,
374};
375
376/**
377 * TPM2 algorithms.
378 */
379enum tpm2_algorithms {
Ilias Apalodimasf4e05902020-11-11 11:18:10 +0200380 TPM2_ALG_SHA1 = 0x04,
Miquel Raynalf3b43502018-05-15 11:57:08 +0200381 TPM2_ALG_XOR = 0x0A,
382 TPM2_ALG_SHA256 = 0x0B,
383 TPM2_ALG_SHA384 = 0x0C,
384 TPM2_ALG_SHA512 = 0x0D,
385 TPM2_ALG_NULL = 0x10,
Ilias Apalodimasf4e05902020-11-11 11:18:10 +0200386 TPM2_ALG_SM3_256 = 0x12,
Miquel Raynalf3b43502018-05-15 11:57:08 +0200387};
388
Tim Harvey6ea1e052024-05-25 13:00:48 -0700389/**
390 * struct digest_info - details of supported digests
391 *
392 * @hash_name: hash name
393 * @hash_alg: hash algorithm id
394 * @hash_mask: hash registry mask
395 * @hash_len: hash digest length
396 */
397struct digest_info {
398 const char *hash_name;
399 u16 hash_alg;
400 u32 hash_mask;
401 u16 hash_len;
402};
403
404/* Algorithm Registry */
405#define TCG2_BOOT_HASH_ALG_SHA1 0x00000001
406#define TCG2_BOOT_HASH_ALG_SHA256 0x00000002
407#define TCG2_BOOT_HASH_ALG_SHA384 0x00000004
408#define TCG2_BOOT_HASH_ALG_SHA512 0x00000008
409#define TCG2_BOOT_HASH_ALG_SM3_256 0x00000010
410
411static const struct digest_info hash_algo_list[] = {
412 {
413 "sha1",
414 TPM2_ALG_SHA1,
415 TCG2_BOOT_HASH_ALG_SHA1,
416 TPM2_SHA1_DIGEST_SIZE,
417 },
418 {
419 "sha256",
420 TPM2_ALG_SHA256,
421 TCG2_BOOT_HASH_ALG_SHA256,
422 TPM2_SHA256_DIGEST_SIZE,
423 },
424 {
425 "sha384",
426 TPM2_ALG_SHA384,
427 TCG2_BOOT_HASH_ALG_SHA384,
428 TPM2_SHA384_DIGEST_SIZE,
429 },
430 {
431 "sha512",
432 TPM2_ALG_SHA512,
433 TCG2_BOOT_HASH_ALG_SHA512,
434 TPM2_SHA512_DIGEST_SIZE,
435 },
436};
Eddie James8ed7bb32023-10-24 10:43:49 -0500437
438static inline u16 tpm2_algorithm_to_len(enum tpm2_algorithms a)
439{
440 switch (a) {
441 case TPM2_ALG_SHA1:
442 return TPM2_SHA1_DIGEST_SIZE;
443 case TPM2_ALG_SHA256:
444 return TPM2_SHA256_DIGEST_SIZE;
445 case TPM2_ALG_SHA384:
446 return TPM2_SHA384_DIGEST_SIZE;
447 case TPM2_ALG_SHA512:
448 return TPM2_SHA512_DIGEST_SIZE;
449 default:
450 return 0;
451 }
452}
453
Simon Glassb4ebd1f2018-11-23 21:29:34 -0700454/* NV index attributes */
455enum tpm_index_attrs {
456 TPMA_NV_PPWRITE = 1UL << 0,
457 TPMA_NV_OWNERWRITE = 1UL << 1,
458 TPMA_NV_AUTHWRITE = 1UL << 2,
459 TPMA_NV_POLICYWRITE = 1UL << 3,
460 TPMA_NV_COUNTER = 1UL << 4,
461 TPMA_NV_BITS = 1UL << 5,
462 TPMA_NV_EXTEND = 1UL << 6,
463 TPMA_NV_POLICY_DELETE = 1UL << 10,
464 TPMA_NV_WRITELOCKED = 1UL << 11,
465 TPMA_NV_WRITEALL = 1UL << 12,
466 TPMA_NV_WRITEDEFINE = 1UL << 13,
467 TPMA_NV_WRITE_STCLEAR = 1UL << 14,
468 TPMA_NV_GLOBALLOCK = 1UL << 15,
469 TPMA_NV_PPREAD = 1UL << 16,
470 TPMA_NV_OWNERREAD = 1UL << 17,
471 TPMA_NV_AUTHREAD = 1UL << 18,
472 TPMA_NV_POLICYREAD = 1UL << 19,
473 TPMA_NV_NO_DA = 1UL << 25,
474 TPMA_NV_ORDERLY = 1UL << 26,
475 TPMA_NV_CLEAR_STCLEAR = 1UL << 27,
476 TPMA_NV_READLOCKED = 1UL << 28,
477 TPMA_NV_WRITTEN = 1UL << 29,
478 TPMA_NV_PLATFORMCREATE = 1UL << 30,
479 TPMA_NV_READ_STCLEAR = 1UL << 31,
480
481 TPMA_NV_MASK_READ = TPMA_NV_PPREAD | TPMA_NV_OWNERREAD |
482 TPMA_NV_AUTHREAD | TPMA_NV_POLICYREAD,
483 TPMA_NV_MASK_WRITE = TPMA_NV_PPWRITE | TPMA_NV_OWNERWRITE |
484 TPMA_NV_AUTHWRITE | TPMA_NV_POLICYWRITE,
485};
486
Simon Glasse1ed0ec2020-02-06 09:55:03 -0700487enum {
488 TPM_ACCESS_VALID = 1 << 7,
489 TPM_ACCESS_ACTIVE_LOCALITY = 1 << 5,
490 TPM_ACCESS_REQUEST_PENDING = 1 << 2,
491 TPM_ACCESS_REQUEST_USE = 1 << 1,
492 TPM_ACCESS_ESTABLISHMENT = 1 << 0,
493};
494
495enum {
496 TPM_STS_FAMILY_SHIFT = 26,
497 TPM_STS_FAMILY_MASK = 0x3 << TPM_STS_FAMILY_SHIFT,
498 TPM_STS_FAMILY_TPM2 = 1 << TPM_STS_FAMILY_SHIFT,
499 TPM_STS_RESE_TESTABLISMENT_BIT = 1 << 25,
500 TPM_STS_COMMAND_CANCEL = 1 << 24,
501 TPM_STS_BURST_COUNT_SHIFT = 8,
502 TPM_STS_BURST_COUNT_MASK = 0xffff << TPM_STS_BURST_COUNT_SHIFT,
503 TPM_STS_VALID = 1 << 7,
504 TPM_STS_COMMAND_READY = 1 << 6,
505 TPM_STS_GO = 1 << 5,
506 TPM_STS_DATA_AVAIL = 1 << 4,
507 TPM_STS_DATA_EXPECT = 1 << 3,
508 TPM_STS_SELF_TEST_DONE = 1 << 2,
509 TPM_STS_RESPONSE_RETRY = 1 << 1,
Ilias Apalodimas97f5e2d2021-11-09 09:02:17 +0200510 TPM_STS_READ_ZERO = 0x23
Simon Glasse1ed0ec2020-02-06 09:55:03 -0700511};
512
513enum {
514 TPM_CMD_COUNT_OFFSET = 2,
515 TPM_CMD_ORDINAL_OFFSET = 6,
516 TPM_MAX_BUF_SIZE = 1260,
517};
518
Simon Glass3d930ed2021-02-06 14:23:40 -0700519enum {
520 /* Secure storage for firmware settings */
521 TPM_HT_PCR = 0,
522 TPM_HT_NV_INDEX,
523 TPM_HT_HMAC_SESSION,
524 TPM_HT_POLICY_SESSION,
525
526 HR_SHIFT = 24,
527 HR_PCR = TPM_HT_PCR << HR_SHIFT,
528 HR_HMAC_SESSION = TPM_HT_HMAC_SESSION << HR_SHIFT,
529 HR_POLICY_SESSION = TPM_HT_POLICY_SESSION << HR_SHIFT,
530 HR_NV_INDEX = TPM_HT_NV_INDEX << HR_SHIFT,
531};
532
Miquel Raynal65a1a6c2018-05-15 11:57:12 +0200533/**
Eddie James8ed7bb32023-10-24 10:43:49 -0500534 * struct tcg2_event_log - Container for managing the platform event log
535 *
536 * @log: Address of the log
537 * @log_position: Current entry position
538 * @log_size: Log space available
539 * @found: Boolean indicating if an existing log was discovered
540 */
541struct tcg2_event_log {
542 u8 *log;
543 u32 log_position;
544 u32 log_size;
545 bool found;
546};
547
548/**
549 * Create a list of digests of the supported PCR banks for a given input data
550 *
551 * @dev TPM device
552 * @input Data
553 * @length Length of the data to calculate the digest
554 * @digest_list List of digests to fill in
555 *
556 * Return: zero on success, negative errno otherwise
557 */
558int tcg2_create_digest(struct udevice *dev, const u8 *input, u32 length,
559 struct tpml_digest_values *digest_list);
560
561/**
562 * Get the event size of the specified digests
563 *
564 * @digest_list List of digests for the event
565 *
566 * Return: Size in bytes of the event
567 */
568u32 tcg2_event_get_size(struct tpml_digest_values *digest_list);
569
570/**
571 * tcg2_get_active_pcr_banks
572 *
573 * @dev TPM device
574 * @active_pcr_banks Bitmask of PCR algorithms supported
575 *
576 * Return: zero on success, negative errno otherwise
577 */
578int tcg2_get_active_pcr_banks(struct udevice *dev, u32 *active_pcr_banks);
579
580/**
581 * tcg2_log_append - Append an event to an event log
582 *
583 * @pcr_index Index of the PCR
584 * @event_type Type of event
585 * @digest_list List of digests to add
586 * @size Size of event
587 * @event Event data
588 * @log Log buffer to append the event to
589 */
590void tcg2_log_append(u32 pcr_index, u32 event_type,
591 struct tpml_digest_values *digest_list, u32 size,
592 const u8 *event, u8 *log);
593
594/**
595 * Extend the PCR with specified digests
596 *
597 * @dev TPM device
598 * @pcr_index Index of the PCR
599 * @digest_list List of digests to extend
600 *
601 * Return: zero on success, negative errno otherwise
602 */
603int tcg2_pcr_extend(struct udevice *dev, u32 pcr_index,
604 struct tpml_digest_values *digest_list);
605
606/**
607 * Read the PCR into a list of digests
608 *
609 * @dev TPM device
610 * @pcr_index Index of the PCR
611 * @digest_list List of digests to extend
612 *
613 * Return: zero on success, negative errno otherwise
614 */
615int tcg2_pcr_read(struct udevice *dev, u32 pcr_index,
616 struct tpml_digest_values *digest_list);
617
618/**
619 * Measure data into the TPM PCRs and the platform event log.
620 *
621 * @dev TPM device
622 * @log Platform event log
623 * @pcr_index Index of the PCR
624 * @size Size of the data or 0 for event only
625 * @data Pointer to the data or NULL for event only
626 * @event_type Event log type
627 * @event_size Size of the event
628 * @event Pointer to the event
629 *
630 * Return: zero on success, negative errno otherwise
631 */
632int tcg2_measure_data(struct udevice *dev, struct tcg2_event_log *elog,
633 u32 pcr_index, u32 size, const u8 *data, u32 event_type,
634 u32 event_size, const u8 *event);
635
636#define tcg2_measure_event(dev, elog, pcr_index, event_type, size, event) \
637 tcg2_measure_data(dev, elog, pcr_index, 0, NULL, event_type, size, \
638 event)
639
640/**
641 * Prepare the event log buffer. This function tries to discover an existing
642 * event log in memory from a previous bootloader stage. If such a log exists
643 * and the PCRs are not extended, the log is "replayed" to extend the PCRs.
644 * If no log is discovered, create the log header.
645 *
646 * @dev TPM device
647 * @elog Platform event log. The log pointer and log_size
648 * members must be initialized to either 0 or to a valid
649 * memory region, in which case any existing log
650 * discovered will be copied to the specified memory
651 * region.
652 * @ignore_existing_log Boolean to indicate whether or not to ignore an
653 * existing platform log in memory
654 *
655 * Return: zero on success, negative errno otherwise
656 */
657int tcg2_log_prepare_buffer(struct udevice *dev, struct tcg2_event_log *elog,
658 bool ignore_existing_log);
659
660/**
661 * Begin measurements.
662 *
663 * @dev TPM device
664 * @elog Platform event log. The log pointer and log_size
665 * members must be initialized to either 0 or to a valid
666 * memory region, in which case any existing log
667 * discovered will be copied to the specified memory
668 * region.
669 * @ignore_existing_log Boolean to indicate whether or not to ignore an
670 * existing platform log in memory
671 *
672 * Return: zero on success, negative errno otherwise
673 */
674int tcg2_measurement_init(struct udevice **dev, struct tcg2_event_log *elog,
675 bool ignore_existing_log);
676
677/**
678 * Stop measurements and record separator events.
679 *
680 * @dev TPM device
681 * @elog Platform event log
682 * @error Boolean to indicate whether an error ocurred or not
683 */
684void tcg2_measurement_term(struct udevice *dev, struct tcg2_event_log *elog,
685 bool error);
686
687/**
688 * Get the platform event log address and size.
689 *
690 * @dev TPM device
691 * @addr Address of the log
692 * @size Size of the log
693 *
694 * Return: zero on success, negative errno otherwise
695 */
696int tcg2_platform_get_log(struct udevice *dev, void **addr, u32 *size);
697
698/**
699 * Get the first TPM2 device found.
700 *
701 * @dev TPM device
702 *
703 * Return: zero on success, negative errno otherwise
704 */
705int tcg2_platform_get_tpm2(struct udevice **dev);
706
707/**
708 * Platform-specific function for handling TPM startup errors
709 *
710 * @dev TPM device
711 * @rc The TPM response code
712 */
713void tcg2_platform_startup_error(struct udevice *dev, int rc);
714
715/**
Miquel Raynal65a1a6c2018-05-15 11:57:12 +0200716 * Issue a TPM2_Startup command.
717 *
Simon Glass8ceca1d2018-11-18 14:22:27 -0700718 * @dev TPM device
Miquel Raynal65a1a6c2018-05-15 11:57:12 +0200719 * @mode TPM startup mode
720 *
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100721 * Return: code of the operation
Miquel Raynal65a1a6c2018-05-15 11:57:12 +0200722 */
Simon Glass8ceca1d2018-11-18 14:22:27 -0700723u32 tpm2_startup(struct udevice *dev, enum tpm2_startup_types mode);
Miquel Raynal65a1a6c2018-05-15 11:57:12 +0200724
Miquel Raynal39c76082018-05-15 11:57:13 +0200725/**
726 * Issue a TPM2_SelfTest command.
727 *
Simon Glass8ceca1d2018-11-18 14:22:27 -0700728 * @dev TPM device
Miquel Raynal39c76082018-05-15 11:57:13 +0200729 * @full_test Asking to perform all tests or only the untested ones
730 *
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100731 * Return: code of the operation
Miquel Raynal39c76082018-05-15 11:57:13 +0200732 */
Simon Glass8ceca1d2018-11-18 14:22:27 -0700733u32 tpm2_self_test(struct udevice *dev, enum tpm2_yes_no full_test);
Miquel Raynal39c76082018-05-15 11:57:13 +0200734
Miquel Raynal8df6f8d2018-05-15 11:57:14 +0200735/**
736 * Issue a TPM2_Clear command.
737 *
Simon Glass8ceca1d2018-11-18 14:22:27 -0700738 * @dev TPM device
Miquel Raynal8df6f8d2018-05-15 11:57:14 +0200739 * @handle Handle
740 * @pw Password
741 * @pw_sz Length of the password
742 *
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100743 * Return: code of the operation
Miquel Raynal8df6f8d2018-05-15 11:57:14 +0200744 */
Simon Glass8ceca1d2018-11-18 14:22:27 -0700745u32 tpm2_clear(struct udevice *dev, u32 handle, const char *pw,
746 const ssize_t pw_sz);
Miquel Raynal8df6f8d2018-05-15 11:57:14 +0200747
Miquel Raynal14d72352018-05-15 11:57:15 +0200748/**
Simon Glass713c58a2021-02-06 14:23:39 -0700749 * Issue a TPM_NV_DefineSpace command
750 *
751 * This allows a space to be defined with given attributes and policy
752 *
753 * @dev TPM device
754 * @space_index index of the area
755 * @space_size size of area in bytes
756 * @nv_attributes TPM_NV_ATTRIBUTES of the area
757 * @nv_policy policy to use
758 * @nv_policy_size size of the policy
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100759 * Return: return code of the operation
Simon Glass713c58a2021-02-06 14:23:39 -0700760 */
761u32 tpm2_nv_define_space(struct udevice *dev, u32 space_index,
762 size_t space_size, u32 nv_attributes,
763 const u8 *nv_policy, size_t nv_policy_size);
764
765/**
Miquel Raynal14d72352018-05-15 11:57:15 +0200766 * Issue a TPM2_PCR_Extend command.
767 *
Simon Glass8ceca1d2018-11-18 14:22:27 -0700768 * @dev TPM device
Miquel Raynal14d72352018-05-15 11:57:15 +0200769 * @index Index of the PCR
Ilias Apalodimas7f59c712020-11-26 23:07:22 +0200770 * @algorithm Algorithm used, defined in 'enum tpm2_algorithms'
Miquel Raynal14d72352018-05-15 11:57:15 +0200771 * @digest Value representing the event to be recorded
Ilias Apalodimas7f59c712020-11-26 23:07:22 +0200772 * @digest_len len of the hash
Miquel Raynal14d72352018-05-15 11:57:15 +0200773 *
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100774 * Return: code of the operation
Miquel Raynal14d72352018-05-15 11:57:15 +0200775 */
Ilias Apalodimas7f59c712020-11-26 23:07:22 +0200776u32 tpm2_pcr_extend(struct udevice *dev, u32 index, u32 algorithm,
777 const u8 *digest, u32 digest_len);
Miquel Raynal14d72352018-05-15 11:57:15 +0200778
Miquel Raynal4c1a5852018-05-15 11:57:16 +0200779/**
Simon Glass3d930ed2021-02-06 14:23:40 -0700780 * Read data from the secure storage
781 *
782 * @dev TPM device
783 * @index Index of data to read
784 * @data Place to put data
785 * @count Number of bytes of data
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100786 * Return: code of the operation
Simon Glass3d930ed2021-02-06 14:23:40 -0700787 */
788u32 tpm2_nv_read_value(struct udevice *dev, u32 index, void *data, u32 count);
789
790/**
791 * Write data to the secure storage
792 *
793 * @dev TPM device
794 * @index Index of data to write
795 * @data Data to write
796 * @count Number of bytes of data
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100797 * Return: code of the operation
Simon Glass3d930ed2021-02-06 14:23:40 -0700798 */
799u32 tpm2_nv_write_value(struct udevice *dev, u32 index, const void *data,
800 u32 count);
801
802/**
Miquel Raynal4c1a5852018-05-15 11:57:16 +0200803 * Issue a TPM2_PCR_Read command.
804 *
Simon Glass8ceca1d2018-11-18 14:22:27 -0700805 * @dev TPM device
Miquel Raynal4c1a5852018-05-15 11:57:16 +0200806 * @idx Index of the PCR
807 * @idx_min_sz Minimum size in bytes of the pcrSelect array
Ruchika Gupta686bedb2021-11-29 13:09:45 +0530808 * @algorithm Algorithm used, defined in 'enum tpm2_algorithms'
Miquel Raynal4c1a5852018-05-15 11:57:16 +0200809 * @data Output buffer for contents of the named PCR
Ruchika Gupta686bedb2021-11-29 13:09:45 +0530810 * @digest_len len of the data
Miquel Raynal4c1a5852018-05-15 11:57:16 +0200811 * @updates Optional out parameter: number of updates for this PCR
812 *
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100813 * Return: code of the operation
Miquel Raynal4c1a5852018-05-15 11:57:16 +0200814 */
Simon Glass8ceca1d2018-11-18 14:22:27 -0700815u32 tpm2_pcr_read(struct udevice *dev, u32 idx, unsigned int idx_min_sz,
Ruchika Gupta686bedb2021-11-29 13:09:45 +0530816 u16 algorithm, void *data, u32 digest_len,
817 unsigned int *updates);
Miquel Raynal4c1a5852018-05-15 11:57:16 +0200818
Miquel Raynal2e52c062018-05-15 11:57:17 +0200819/**
820 * Issue a TPM2_GetCapability command. This implementation is limited
821 * to query property index that is 4-byte wide.
822 *
Simon Glass8ceca1d2018-11-18 14:22:27 -0700823 * @dev TPM device
Miquel Raynal2e52c062018-05-15 11:57:17 +0200824 * @capability Partition of capabilities
825 * @property Further definition of capability, limited to be 4 bytes wide
826 * @buf Output buffer for capability information
827 * @prop_count Size of output buffer
828 *
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100829 * Return: code of the operation
Miquel Raynal2e52c062018-05-15 11:57:17 +0200830 */
Simon Glass8ceca1d2018-11-18 14:22:27 -0700831u32 tpm2_get_capability(struct udevice *dev, u32 capability, u32 property,
832 void *buf, size_t prop_count);
Miquel Raynal2e52c062018-05-15 11:57:17 +0200833
Miquel Raynal228e9902018-05-15 11:57:18 +0200834/**
Eddie James8ed7bb32023-10-24 10:43:49 -0500835 * tpm2_get_pcr_info() - get the supported, active PCRs and number of banks
836 *
837 * @dev: TPM device
838 * @supported_pcr: bitmask with the algorithms supported
839 * @active_pcr: bitmask with the active algorithms
840 * @pcr_banks: number of PCR banks
841 *
842 * @return 0 on success, code of operation or negative errno on failure
843 */
844int tpm2_get_pcr_info(struct udevice *dev, u32 *supported_pcr, u32 *active_pcr,
845 u32 *pcr_banks);
846
847/**
Miquel Raynal228e9902018-05-15 11:57:18 +0200848 * Issue a TPM2_DictionaryAttackLockReset command.
849 *
Simon Glass8ceca1d2018-11-18 14:22:27 -0700850 * @dev TPM device
Miquel Raynal228e9902018-05-15 11:57:18 +0200851 * @pw Password
852 * @pw_sz Length of the password
853 *
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100854 * Return: code of the operation
Miquel Raynal228e9902018-05-15 11:57:18 +0200855 */
Simon Glass8ceca1d2018-11-18 14:22:27 -0700856u32 tpm2_dam_reset(struct udevice *dev, const char *pw, const ssize_t pw_sz);
Miquel Raynal228e9902018-05-15 11:57:18 +0200857
858/**
859 * Issue a TPM2_DictionaryAttackParameters command.
860 *
Simon Glass8ceca1d2018-11-18 14:22:27 -0700861 * @dev TPM device
Miquel Raynal228e9902018-05-15 11:57:18 +0200862 * @pw Password
863 * @pw_sz Length of the password
864 * @max_tries Count of authorizations before lockout
865 * @recovery_time Time before decrementation of the failure count
866 * @lockout_recovery Time to wait after a lockout
867 *
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100868 * Return: code of the operation
Miquel Raynal228e9902018-05-15 11:57:18 +0200869 */
Simon Glass8ceca1d2018-11-18 14:22:27 -0700870u32 tpm2_dam_parameters(struct udevice *dev, const char *pw,
871 const ssize_t pw_sz, unsigned int max_tries,
872 unsigned int recovery_time,
Miquel Raynal228e9902018-05-15 11:57:18 +0200873 unsigned int lockout_recovery);
874
Miquel Raynal05d7be32018-05-15 11:57:19 +0200875/**
876 * Issue a TPM2_HierarchyChangeAuth command.
877 *
Simon Glass8ceca1d2018-11-18 14:22:27 -0700878 * @dev TPM device
Miquel Raynal05d7be32018-05-15 11:57:19 +0200879 * @handle Handle
880 * @newpw New password
881 * @newpw_sz Length of the new password
882 * @oldpw Old password
883 * @oldpw_sz Length of the old password
884 *
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100885 * Return: code of the operation
Miquel Raynal05d7be32018-05-15 11:57:19 +0200886 */
Simon Glass8ceca1d2018-11-18 14:22:27 -0700887int tpm2_change_auth(struct udevice *dev, u32 handle, const char *newpw,
888 const ssize_t newpw_sz, const char *oldpw,
889 const ssize_t oldpw_sz);
Miquel Raynal05d7be32018-05-15 11:57:19 +0200890
Miquel Raynal0b864f62018-05-15 11:57:20 +0200891/**
892 * Issue a TPM_PCR_SetAuthPolicy command.
893 *
Simon Glass8ceca1d2018-11-18 14:22:27 -0700894 * @dev TPM device
Miquel Raynal0b864f62018-05-15 11:57:20 +0200895 * @pw Platform password
896 * @pw_sz Length of the password
897 * @index Index of the PCR
898 * @digest New key to access the PCR
899 *
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100900 * Return: code of the operation
Miquel Raynal0b864f62018-05-15 11:57:20 +0200901 */
Simon Glass8ceca1d2018-11-18 14:22:27 -0700902u32 tpm2_pcr_setauthpolicy(struct udevice *dev, const char *pw,
903 const ssize_t pw_sz, u32 index, const char *key);
Miquel Raynal0b864f62018-05-15 11:57:20 +0200904
905/**
906 * Issue a TPM_PCR_SetAuthValue command.
907 *
Simon Glass8ceca1d2018-11-18 14:22:27 -0700908 * @dev TPM device
Miquel Raynal0b864f62018-05-15 11:57:20 +0200909 * @pw Platform password
910 * @pw_sz Length of the password
911 * @index Index of the PCR
912 * @digest New key to access the PCR
913 * @key_sz Length of the new key
914 *
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100915 * Return: code of the operation
Miquel Raynal0b864f62018-05-15 11:57:20 +0200916 */
Simon Glass8ceca1d2018-11-18 14:22:27 -0700917u32 tpm2_pcr_setauthvalue(struct udevice *dev, const char *pw,
918 const ssize_t pw_sz, u32 index, const char *key,
919 const ssize_t key_sz);
Miquel Raynal0b864f62018-05-15 11:57:20 +0200920
Dhananjay Phadke7a2cf2e2020-06-04 16:43:59 -0700921/**
922 * Issue a TPM2_GetRandom command.
923 *
924 * @dev TPM device
925 * @param data output buffer for the random bytes
926 * @param count size of output buffer
927 *
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100928 * Return: return code of the operation
Dhananjay Phadke7a2cf2e2020-06-04 16:43:59 -0700929 */
930u32 tpm2_get_random(struct udevice *dev, void *data, u32 count);
931
Simon Glasse9d3d592021-02-06 14:23:41 -0700932/**
933 * Lock data in the TPM
934 *
935 * Once locked the data cannot be written until after a reboot
936 *
937 * @dev TPM device
938 * @index Index of data to lock
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100939 * Return: code of the operation
Simon Glasse9d3d592021-02-06 14:23:41 -0700940 */
941u32 tpm2_write_lock(struct udevice *dev, u32 index);
942
Simon Glass77759db2021-02-06 14:23:42 -0700943/**
944 * Disable access to any platform data
945 *
946 * This can be called to close off access to the firmware data in the data,
947 * before calling the kernel.
948 *
949 * @dev TPM device
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100950 * Return: code of the operation
Simon Glass77759db2021-02-06 14:23:42 -0700951 */
952u32 tpm2_disable_platform_hierarchy(struct udevice *dev);
953
Masahisa Kojima06ef6b62021-11-04 22:59:16 +0900954/**
955 * submit user specified data to the TPM and get response
956 *
957 * @dev TPM device
958 * @sendbuf: Buffer of the data to send
959 * @recvbuf: Buffer to save the response to
960 * @recv_size: Pointer to the size of the response buffer
961 *
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +0100962 * Return: code of the operation
Masahisa Kojima06ef6b62021-11-04 22:59:16 +0900963 */
964u32 tpm2_submit_command(struct udevice *dev, const u8 *sendbuf,
965 u8 *recvbuf, size_t *recv_size);
966
Simon Glass3f7a73a2022-08-30 21:05:37 -0600967/**
968 * tpm_cr50_report_state() - Report the Cr50 internal state
969 *
970 * @dev: TPM device
971 * @vendor_cmd: Vendor command number to send
972 * @vendor_subcmd: Vendor sub-command number to send
973 * @recvbuf: Buffer to save the response to
974 * @recv_size: Pointer to the size of the response buffer
975 * Return: result of the operation
976 */
977u32 tpm2_report_state(struct udevice *dev, uint vendor_cmd, uint vendor_subcmd,
978 u8 *recvbuf, size_t *recv_size);
979
Simon Glass3564b8e2022-08-30 21:05:38 -0600980/**
981 * tpm2_enable_nvcommits() - Tell TPM to commit NV data immediately
982 *
983 * For Chromium OS verified boot, we may reboot or reset at different times,
984 * possibly leaving non-volatile data unwritten by the TPM.
985 *
986 * This vendor command is used to indicate that non-volatile data should be
987 * written to its store immediately.
988 *
989 * @dev TPM device
990 * @vendor_cmd: Vendor command number to send
991 * @vendor_subcmd: Vendor sub-command number to send
992 * Return: result of the operation
993 */
994u32 tpm2_enable_nvcommits(struct udevice *dev, uint vendor_cmd,
995 uint vendor_subcmd);
996
Ilias Apalodimas42d7bdf2023-01-25 12:18:36 +0200997/**
998 * tpm2_auto_start() - start up the TPM and perform selftests.
999 * If a testable function has not been tested and is
1000 * requested the TPM2 will return TPM_RC_NEEDS_TEST.
1001 *
1002 * @param dev TPM device
1003 * Return: TPM2_RC_TESTING, if TPM2 self-test is in progress.
1004 * TPM2_RC_SUCCESS, if testing of all functions is complete without
1005 * functional failures.
1006 * TPM2_RC_FAILURE, if any test failed.
1007 * TPM2_RC_INITIALIZE, if the TPM has not gone through the Startup
1008 * sequence
1009
1010 */
1011u32 tpm2_auto_start(struct udevice *dev);
1012
Tim Harvey6ea1e052024-05-25 13:00:48 -07001013/**
1014 * tpm2_name_to_algorithm() - Return an algorithm id given a supported
1015 * algorithm name
1016 *
1017 * @name: algorithm name
1018 * Return: enum tpm2_algorithms or -EINVAL
1019 */
1020enum tpm2_algorithms tpm2_name_to_algorithm(const char *name);
1021
1022/**
1023 * tpm2_algorithm_name() - Return an algorithm name string for a
1024 * supported algorithm id
1025 *
1026 * @algorithm_id: algorithm defined in enum tpm2_algorithms
1027 * Return: algorithm name string or ""
1028 */
1029const char *tpm2_algorithm_name(enum tpm2_algorithms);
1030
1031/**
1032 * tpm2_algorithm_to_mask() - Get a TCG hash mask for algorithm
1033 *
1034 * @hash_alg: TCG defined algorithm
1035 * Return: TCG hashing algorithm bitmaps (or 0 if algo not supported)
1036 */
1037u32 tpm2_algorithm_to_mask(enum tpm2_algorithms);
1038
Miquel Raynalf3b43502018-05-15 11:57:08 +02001039#endif /* __TPM_V2_H */