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git01.mediatek.com / filogic / uboot / e51ca6a64f6495d1ba7acd86932cb8dd23fd7ba9 / . / drivers / pinctrl / renesas / pfc-r8a77951.c
blob: 81568ae4a5e1e34e6b3d9f16bf741c948ad0aee2 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]2/*
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3 * R8A77951 processor support - PFC hardware block.
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4 *
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5 * Copyright (C) 2015-2019 Renesas Electronics Corporation
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6 */
7
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]8#include <dm.h>
9#include <errno.h>
10#include <dm/pinctrl.h>
11#include <linux/kernel.h>
12
13#include "sh_pfc.h"
14
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]15#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]16
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]17#define CPU_ALL_GP(fn, sfx) \
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]18 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]19 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]20 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
Marek Vasut14dfdd62023-09-17 16:08:40 +0200[diff] [blame]21 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]22 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
23 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
Marek Vasut14dfdd62023-09-17 16:08:40 +0200[diff] [blame]26 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]27 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]30
31#define CPU_ALL_NOGP(fn) \
32 PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
33 PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
34 PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \
35 PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \
36 PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \
37 PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \
38 PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \
39 PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \
40 PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
41 PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
42 PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
43 PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
44 PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
45 PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \
46 PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
47 PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \
48 PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \
49 PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \
50 PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS), \
51 PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
52 PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, CFG_FLAGS), \
53 PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
54 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \
55 PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \
56 PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \
57 PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \
58 PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \
59 PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \
60 PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \
61 PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \
62 PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \
63 PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \
64 PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \
65 PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \
66 PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \
67 PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \
68 PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \
69 PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \
70 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
71 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
72 PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
73 PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
74 PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
75
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]76/*
77 * F_() : just information
78 * FM() : macro for FN_xxx / xxx_MARK
79 */
80
81/* GPSR0 */
82#define GPSR0_15 F_(D15, IP7_11_8)
83#define GPSR0_14 F_(D14, IP7_7_4)
84#define GPSR0_13 F_(D13, IP7_3_0)
85#define GPSR0_12 F_(D12, IP6_31_28)
86#define GPSR0_11 F_(D11, IP6_27_24)
87#define GPSR0_10 F_(D10, IP6_23_20)
88#define GPSR0_9 F_(D9, IP6_19_16)
89#define GPSR0_8 F_(D8, IP6_15_12)
90#define GPSR0_7 F_(D7, IP6_11_8)
91#define GPSR0_6 F_(D6, IP6_7_4)
92#define GPSR0_5 F_(D5, IP6_3_0)
93#define GPSR0_4 F_(D4, IP5_31_28)
94#define GPSR0_3 F_(D3, IP5_27_24)
95#define GPSR0_2 F_(D2, IP5_23_20)
96#define GPSR0_1 F_(D1, IP5_19_16)
97#define GPSR0_0 F_(D0, IP5_15_12)
98
99/* GPSR1 */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]100#define GPSR1_28 FM(CLKOUT)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]101#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
102#define GPSR1_26 F_(WE1_N, IP5_7_4)
103#define GPSR1_25 F_(WE0_N, IP5_3_0)
104#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
105#define GPSR1_23 F_(RD_N, IP4_27_24)
106#define GPSR1_22 F_(BS_N, IP4_23_20)
107#define GPSR1_21 F_(CS1_N, IP4_19_16)
108#define GPSR1_20 F_(CS0_N, IP4_15_12)
109#define GPSR1_19 F_(A19, IP4_11_8)
110#define GPSR1_18 F_(A18, IP4_7_4)
111#define GPSR1_17 F_(A17, IP4_3_0)
112#define GPSR1_16 F_(A16, IP3_31_28)
113#define GPSR1_15 F_(A15, IP3_27_24)
114#define GPSR1_14 F_(A14, IP3_23_20)
115#define GPSR1_13 F_(A13, IP3_19_16)
116#define GPSR1_12 F_(A12, IP3_15_12)
117#define GPSR1_11 F_(A11, IP3_11_8)
118#define GPSR1_10 F_(A10, IP3_7_4)
119#define GPSR1_9 F_(A9, IP3_3_0)
120#define GPSR1_8 F_(A8, IP2_31_28)
121#define GPSR1_7 F_(A7, IP2_27_24)
122#define GPSR1_6 F_(A6, IP2_23_20)
123#define GPSR1_5 F_(A5, IP2_19_16)
124#define GPSR1_4 F_(A4, IP2_15_12)
125#define GPSR1_3 F_(A3, IP2_11_8)
126#define GPSR1_2 F_(A2, IP2_7_4)
127#define GPSR1_1 F_(A1, IP2_3_0)
128#define GPSR1_0 F_(A0, IP1_31_28)
129
130/* GPSR2 */
131#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
132#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
133#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
134#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
135#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
136#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
137#define GPSR2_8 F_(PWM2_A, IP1_27_24)
138#define GPSR2_7 F_(PWM1_A, IP1_23_20)
139#define GPSR2_6 F_(PWM0, IP1_19_16)
140#define GPSR2_5 F_(IRQ5, IP1_15_12)
141#define GPSR2_4 F_(IRQ4, IP1_11_8)
142#define GPSR2_3 F_(IRQ3, IP1_7_4)
143#define GPSR2_2 F_(IRQ2, IP1_3_0)
144#define GPSR2_1 F_(IRQ1, IP0_31_28)
145#define GPSR2_0 F_(IRQ0, IP0_27_24)
146
147/* GPSR3 */
148#define GPSR3_15 F_(SD1_WP, IP11_23_20)
149#define GPSR3_14 F_(SD1_CD, IP11_19_16)
150#define GPSR3_13 F_(SD0_WP, IP11_15_12)
151#define GPSR3_12 F_(SD0_CD, IP11_11_8)
152#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
153#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
154#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
155#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
156#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
157#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
158#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
159#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
160#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
161#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
162#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
163#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
164
165/* GPSR4 */
166#define GPSR4_17 F_(SD3_DS, IP11_7_4)
167#define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
168#define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
169#define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
170#define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
171#define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
172#define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
173#define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
174#define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
175#define GPSR4_8 F_(SD3_CMD, IP10_3_0)
176#define GPSR4_7 F_(SD3_CLK, IP9_31_28)
177#define GPSR4_6 F_(SD2_DS, IP9_27_24)
178#define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
179#define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
180#define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
181#define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
182#define GPSR4_1 F_(SD2_CMD, IP9_7_4)
183#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
184
185/* GPSR5 */
186#define GPSR5_25 F_(MLB_DAT, IP14_19_16)
187#define GPSR5_24 F_(MLB_SIG, IP14_15_12)
188#define GPSR5_23 F_(MLB_CLK, IP14_11_8)
189#define GPSR5_22 FM(MSIOF0_RXD)
190#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
191#define GPSR5_20 FM(MSIOF0_TXD)
192#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
193#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
194#define GPSR5_17 FM(MSIOF0_SCK)
195#define GPSR5_16 F_(HRTS0_N, IP13_27_24)
196#define GPSR5_15 F_(HCTS0_N, IP13_23_20)
197#define GPSR5_14 F_(HTX0, IP13_19_16)
198#define GPSR5_13 F_(HRX0, IP13_15_12)
199#define GPSR5_12 F_(HSCK0, IP13_11_8)
200#define GPSR5_11 F_(RX2_A, IP13_7_4)
201#define GPSR5_10 F_(TX2_A, IP13_3_0)
202#define GPSR5_9 F_(SCK2, IP12_31_28)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]203#define GPSR5_8 F_(RTS1_N, IP12_27_24)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]204#define GPSR5_7 F_(CTS1_N, IP12_23_20)
205#define GPSR5_6 F_(TX1_A, IP12_19_16)
206#define GPSR5_5 F_(RX1_A, IP12_15_12)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]207#define GPSR5_4 F_(RTS0_N, IP12_11_8)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]208#define GPSR5_3 F_(CTS0_N, IP12_7_4)
209#define GPSR5_2 F_(TX0, IP12_3_0)
210#define GPSR5_1 F_(RX0, IP11_31_28)
211#define GPSR5_0 F_(SCK0, IP11_27_24)
212
213/* GPSR6 */
214#define GPSR6_31 F_(USB2_CH3_OVC, IP18_7_4)
215#define GPSR6_30 F_(USB2_CH3_PWEN, IP18_3_0)
216#define GPSR6_29 F_(USB30_OVC, IP17_31_28)
217#define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
218#define GPSR6_27 F_(USB1_OVC, IP17_23_20)
219#define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
220#define GPSR6_25 F_(USB0_OVC, IP17_15_12)
221#define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
222#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
223#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
224#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
225#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
226#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
227#define GPSR6_18 F_(SSI_WS78, IP16_19_16)
228#define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
229#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
230#define GPSR6_15 F_(SSI_WS6, IP16_7_4)
231#define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
232#define GPSR6_13 FM(SSI_SDATA5)
233#define GPSR6_12 FM(SSI_WS5)
234#define GPSR6_11 FM(SSI_SCK5)
235#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
236#define GPSR6_9 F_(SSI_WS4, IP15_27_24)
237#define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
238#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
239#define GPSR6_6 F_(SSI_WS349, IP15_15_12)
240#define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
241#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
242#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
243#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
244#define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]245#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]246
247/* GPSR7 */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]248#define GPSR7_3 FM(GP7_03)
249#define GPSR7_2 FM(GP7_02)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]250#define GPSR7_1 FM(AVS2)
251#define GPSR7_0 FM(AVS1)
252
253
254/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
255#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]260#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]261#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]264#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268#define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269#define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]270#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274
275/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
276#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]282#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]283#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]298#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]299#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]311#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]312#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317
318/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
319#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349
350/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
351#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]358#define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]359#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]362#define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]363#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
364#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
365#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
366#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
367#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
368#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
369#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
370#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
371#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
372#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
373#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
374#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
375#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
376#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
377#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
378#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
379
380/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
381#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
382#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
383#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
384#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
385#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
386#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
387#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
388#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
389#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
390#define IP16_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
391#define IP16_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
392#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
393#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
394#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
395#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
396#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
397#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]398#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]399#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
400#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
401#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
402#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
403#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
404#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
405#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
406#define IP18_3_0 FM(USB2_CH3_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
407#define IP18_7_4 FM(USB2_CH3_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
408
409#define PINMUX_GPSR \
410\
411 GPSR6_31 \
412 GPSR6_30 \
413 GPSR6_29 \
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]414 GPSR1_28 GPSR6_28 \
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]415 GPSR1_27 GPSR6_27 \
416 GPSR1_26 GPSR6_26 \
417 GPSR1_25 GPSR5_25 GPSR6_25 \
418 GPSR1_24 GPSR5_24 GPSR6_24 \
419 GPSR1_23 GPSR5_23 GPSR6_23 \
420 GPSR1_22 GPSR5_22 GPSR6_22 \
421 GPSR1_21 GPSR5_21 GPSR6_21 \
422 GPSR1_20 GPSR5_20 GPSR6_20 \
423 GPSR1_19 GPSR5_19 GPSR6_19 \
424 GPSR1_18 GPSR5_18 GPSR6_18 \
425 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
426 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
427GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
428GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
429GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
430GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
431GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
432GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
433GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
434GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
435GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
436GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
437GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
438GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
439GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
440GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
441GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
442GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
443
444#define PINMUX_IPSR \
445\
446FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
447FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
448FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
449FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
450FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
451FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
452FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
453FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
454\
455FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
456FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
457FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
458FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
459FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
460FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
461FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
462FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
463\
464FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
465FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
466FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
467FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
468FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
469FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
470FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
471FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
472\
473FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
474FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
475FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
476FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
477FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
478FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
479FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
480FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
481\
482FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
483FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
484FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
485FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
486FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
487FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
488FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
489FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
490
491/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
492#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
493#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
494#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
495#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
496#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
497#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
498#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
499#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
500#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
501#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
502#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
503#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
504#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
505#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
506#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
507#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
508#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]509#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]510
511/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
512#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
513#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
514#define MOD_SEL1_26 FM(SEL_TIMER_TMU1_0) FM(SEL_TIMER_TMU1_1)
515#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
516#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]517#define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]518#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
519#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
520#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
521#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
522#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
523#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
524#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
525#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
526#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
527#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
528#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
529#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
530#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
531#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
532#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
533#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
534
535/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
536#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
537#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
538#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
539#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
540#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
541#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
542#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
543#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
544#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]545#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1)
546#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]547#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
548
549#define PINMUX_MOD_SELS \
550\
551MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
552 MOD_SEL2_30 \
553 MOD_SEL1_29_28_27 MOD_SEL2_29 \
554MOD_SEL0_28_27 MOD_SEL2_28_27 \
555MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
556 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
557MOD_SEL0_23 MOD_SEL1_23_22_21 \
558MOD_SEL0_22 \
559MOD_SEL0_21 MOD_SEL2_21 \
560MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
561MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
562MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
563 MOD_SEL2_17 \
564MOD_SEL0_16 MOD_SEL1_16 \
565 MOD_SEL1_15_14 \
566MOD_SEL0_14_13 \
567 MOD_SEL1_13 \
568MOD_SEL0_12 MOD_SEL1_12 \
569MOD_SEL0_11 MOD_SEL1_11 \
570MOD_SEL0_10 MOD_SEL1_10 \
571MOD_SEL0_9_8 MOD_SEL1_9 \
572MOD_SEL0_7_6 \
573 MOD_SEL1_6 \
574MOD_SEL0_5 MOD_SEL1_5 \
575MOD_SEL0_4_3 MOD_SEL1_4 \
576 MOD_SEL1_3 \
577 MOD_SEL1_2 \
578 MOD_SEL1_1 \
579 MOD_SEL1_0 MOD_SEL2_0
580
581/*
582 * These pins are not able to be muxed but have other properties
583 * that can be set, such as drive-strength or pull-up/pull-down enable.
584 */
585#define PINMUX_STATIC \
586 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
587 FM(QSPI0_IO2) FM(QSPI0_IO3) \
588 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
589 FM(QSPI1_IO2) FM(QSPI1_IO3) \
590 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
591 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
592 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
593 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]594 FM(PRESETOUT) \
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]595 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
596 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
597
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]598#define PINMUX_PHYS \
599 FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
600
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]601enum {
602 PINMUX_RESERVED = 0,
603
604 PINMUX_DATA_BEGIN,
605 GP_ALL(DATA),
606 PINMUX_DATA_END,
607
608#define F_(x, y)
609#define FM(x) FN_##x,
610 PINMUX_FUNCTION_BEGIN,
611 GP_ALL(FN),
612 PINMUX_GPSR
613 PINMUX_IPSR
614 PINMUX_MOD_SELS
615 PINMUX_FUNCTION_END,
616#undef F_
617#undef FM
618
619#define F_(x, y)
620#define FM(x) x##_MARK,
621 PINMUX_MARK_BEGIN,
622 PINMUX_GPSR
623 PINMUX_IPSR
624 PINMUX_MOD_SELS
625 PINMUX_STATIC
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]626 PINMUX_PHYS
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]627 PINMUX_MARK_END,
628#undef F_
629#undef FM
630};
631
632static const u16 pinmux_data[] = {
633 PINMUX_DATA_GP_ALL(),
634
635 PINMUX_SINGLE(AVS1),
636 PINMUX_SINGLE(AVS2),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]637 PINMUX_SINGLE(CLKOUT),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]638 PINMUX_SINGLE(GP7_02),
639 PINMUX_SINGLE(GP7_03),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]640 PINMUX_SINGLE(MSIOF0_RXD),
641 PINMUX_SINGLE(MSIOF0_SCK),
642 PINMUX_SINGLE(MSIOF0_TXD),
643 PINMUX_SINGLE(SSI_SCK5),
644 PINMUX_SINGLE(SSI_SDATA5),
645 PINMUX_SINGLE(SSI_WS5),
646
647 /* IPSR0 */
648 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
649 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
650
651 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
652 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
653 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
654
655 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
656 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
657 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
658
659 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
660 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
661 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
662
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]663 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
664 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
665 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
666 PINMUX_IPSR_MSEL(IP0_19_16, FSCLKST2_N_A, I2C_SEL_5_0),
667 PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]668
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]669 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
670 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
671 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]672 PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]673
674 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
675 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
676 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
677 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
678 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
679 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
680 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
681
682 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
683 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
684 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
685 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
686 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
687 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
688 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
689
690 /* IPSR1 */
691 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
692 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
693 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
694 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
695 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
696 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
697
698 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
699 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]700 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
701 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
702 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
703 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
704
705 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
706 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]707 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
708 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
709 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
710 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
711
712 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
713 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]714 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
715 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
716 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
717 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B),
718 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
719
720 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
721 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]722 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
723 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
724
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]725 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
726 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
727 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
728 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]729 PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]730
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]731 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
732 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
733 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
734 PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]735
736 PINMUX_IPSR_GPSR(IP1_31_28, A0),
737 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
738 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
739 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
740 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
741 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
742
743 /* IPSR2 */
744 PINMUX_IPSR_GPSR(IP2_3_0, A1),
745 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
746 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
747 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
748 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
749 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
750
751 PINMUX_IPSR_GPSR(IP2_7_4, A2),
752 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
753 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
754 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
755 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
756 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
757
758 PINMUX_IPSR_GPSR(IP2_11_8, A3),
759 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
760 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
761 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
762 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
763 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
764
765 PINMUX_IPSR_GPSR(IP2_15_12, A4),
766 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
767 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
768 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
769 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
770 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
771
772 PINMUX_IPSR_GPSR(IP2_19_16, A5),
773 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
774 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
775 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
776 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
777 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
778 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
779
780 PINMUX_IPSR_GPSR(IP2_23_20, A6),
781 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
782 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
783 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
784 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
785 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
786 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
787
788 PINMUX_IPSR_GPSR(IP2_27_24, A7),
789 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
790 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
791 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
792 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
793 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
794 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
795
796 PINMUX_IPSR_GPSR(IP2_31_28, A8),
797 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
798 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
799 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
800 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
801 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
802 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
803
804 /* IPSR3 */
805 PINMUX_IPSR_GPSR(IP3_3_0, A9),
806 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
807 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
808 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
809
810 PINMUX_IPSR_GPSR(IP3_7_4, A10),
811 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]812 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]813 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
814
815 PINMUX_IPSR_GPSR(IP3_11_8, A11),
816 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
817 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
818 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
819 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
820 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
821 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
822 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
823 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
824
825 PINMUX_IPSR_GPSR(IP3_15_12, A12),
826 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
827 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
828 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
829 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
830 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
831
832 PINMUX_IPSR_GPSR(IP3_19_16, A13),
833 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
834 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
835 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
836 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
837 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
838
839 PINMUX_IPSR_GPSR(IP3_23_20, A14),
840 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
841 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
842 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
843 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
844 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
845
846 PINMUX_IPSR_GPSR(IP3_27_24, A15),
847 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
848 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
849 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
850 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
851 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
852
853 PINMUX_IPSR_GPSR(IP3_31_28, A16),
854 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
855 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
856 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
857
858 /* IPSR4 */
859 PINMUX_IPSR_GPSR(IP4_3_0, A17),
860 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
861 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
862 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
863
864 PINMUX_IPSR_GPSR(IP4_7_4, A18),
865 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
866 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
867 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
868
869 PINMUX_IPSR_GPSR(IP4_11_8, A19),
870 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
871 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
872 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
873
874 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
875 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
876
877 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
878 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
879 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
880
881 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
882 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
883 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
884 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
885 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
886 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
887 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
888 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
889
890 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
891 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
892 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
893 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
894 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
895 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
896
897 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
898 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
899 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
900 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
901 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
902 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
903
904 /* IPSR5 */
905 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
906 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
907 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
908 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
909 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
910 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
911 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
912
913 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
914 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]915 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]916 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
917 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
918 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
919 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
920 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
921
922 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
923 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
924 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
925 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
926
927 PINMUX_IPSR_GPSR(IP5_15_12, D0),
928 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
929 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
930 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
931 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
932
933 PINMUX_IPSR_GPSR(IP5_19_16, D1),
934 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
935 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
936 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
937 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
938
939 PINMUX_IPSR_GPSR(IP5_23_20, D2),
940 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
941 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
942 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
943
944 PINMUX_IPSR_GPSR(IP5_27_24, D3),
945 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
946 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
947 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
948
949 PINMUX_IPSR_GPSR(IP5_31_28, D4),
950 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
951 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
952 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
953
954 /* IPSR6 */
955 PINMUX_IPSR_GPSR(IP6_3_0, D5),
956 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
957 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
958 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
959
960 PINMUX_IPSR_GPSR(IP6_7_4, D6),
961 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
962 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
963 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
964
965 PINMUX_IPSR_GPSR(IP6_11_8, D7),
966 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
967 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
968 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
969
970 PINMUX_IPSR_GPSR(IP6_15_12, D8),
971 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
972 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
973 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
974 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
975 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
976
977 PINMUX_IPSR_GPSR(IP6_19_16, D9),
978 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
979 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
980 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
981 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
982
983 PINMUX_IPSR_GPSR(IP6_23_20, D10),
984 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
985 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
986 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
987 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
988 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
989 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
990
991 PINMUX_IPSR_GPSR(IP6_27_24, D11),
992 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
993 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
994 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
995 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]996 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]997 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
998
999 PINMUX_IPSR_GPSR(IP6_31_28, D12),
1000 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
1001 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
1002 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
1003 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
1004 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
1005
1006 /* IPSR7 */
1007 PINMUX_IPSR_GPSR(IP7_3_0, D13),
1008 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
1009 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
1010 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
1011 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
1012 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
1013
1014 PINMUX_IPSR_GPSR(IP7_7_4, D14),
1015 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
1016 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
1017 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
1018 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
1019 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
1020 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
1021
1022 PINMUX_IPSR_GPSR(IP7_11_8, D15),
1023 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
1024 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
1025 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
1026 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
1027 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
1028 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
1029
1030 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
1031 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
1032 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
1033
1034 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
1035 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
1036 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
1037
1038 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
1039 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
1040 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
1041 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
1042
1043 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
1044 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
1045 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1046 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
1047
1048 /* IPSR8 */
1049 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1050 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1051 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1052 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
1053
1054 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1055 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1056 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1057 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
1058
1059 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1060 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1061 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1062
1063 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1064 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
1065 PINMUX_IPSR_GPSR(IP8_15_12, NFCE_N_B),
1066 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1067 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1068
1069 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1070 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1071 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
1072 PINMUX_IPSR_GPSR(IP8_19_16, NFWP_N_B),
1073 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1074 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1075
1076 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1077 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1078 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
1079 PINMUX_IPSR_GPSR(IP8_23_20, NFDATA14_B),
1080 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1081 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1082
1083 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1084 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1085 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
1086 PINMUX_IPSR_GPSR(IP8_27_24, NFDATA15_B),
1087 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1088 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1089
1090 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1091 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1092 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
1093 PINMUX_IPSR_GPSR(IP8_31_28, NFRB_N_B),
1094 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1095 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1096
1097 /* IPSR9 */
1098 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1099 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
1100
1101 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1102 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
1103
1104 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1105 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
1106
1107 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1108 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
1109
1110 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1111 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
1112
1113 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1114 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
1115
1116 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1117 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1118 PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B),
1119
1120 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1121 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
1122
1123 /* IPSR10 */
1124 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1125 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
1126
1127 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1128 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
1129
1130 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1131 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
1132
1133 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1134 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
1135
1136 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1137 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
1138
1139 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1140 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1141 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
1142
1143 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1144 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1145 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
1146
1147 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1148 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1149 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
1150
1151 /* IPSR11 */
1152 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1153 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1154 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1155
1156 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1157 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1158
1159 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
1160 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1161 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1162
1163 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
1164 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1165
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1166 PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
1167 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1168 PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1169
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1170 PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
1171 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1172 PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1173
1174 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1175 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1176 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1177 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1178 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1179 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1180 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1181 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1182 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1183 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1184
1185 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1186 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1187 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1188 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1189 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
1190
1191 /* IPSR12 */
1192 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1193 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1194 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1195 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1196 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1197
1198 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1199 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1200 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1201 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1202 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1203 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1204 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1205 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1206
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1207 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1208 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1209 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1210 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1211 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1212 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1213 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1214 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1215
1216 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1217 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1218 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1219 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1220 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1221
1222 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1223 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1224 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1225 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1226 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1227
1228 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1229 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1230 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1231 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1232 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1233 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1234 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1235
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1236 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1237 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1238 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1239 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1240 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1241 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1242 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1243
1244 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
1245 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
1246 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1247 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1248 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1249 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1250 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
1251
1252 /* IPSR13 */
1253 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1254 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1255 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1256 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1257 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1258 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
1259
1260 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1261 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1262 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1263 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1264 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1265 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
1266
1267 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1268 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1269 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1270 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1271 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1272 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1273 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1274 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1275
1276 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1277 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1278 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1279 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1280 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1281 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1282
1283 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1284 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1285 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1286 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1287 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1288 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1289
1290 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1291 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1292 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1293 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1294 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1295 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1296 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1297 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1298
1299 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1300 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1301 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1302 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1303 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1304 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1305 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1306
1307 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1308 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1309 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1310 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
1311
1312 /* IPSR14 */
1313 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1314 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
1315 PINMUX_IPSR_GPSR(IP14_3_0, NFWP_N_A),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1316 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1317 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1318 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1319 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
1320 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU1_1),
1321
1322 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1323 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1324 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1325 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1326 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1327 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1328 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1329 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1330
1331 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1332 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1333 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1334
1335 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1336 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1337 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1338 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1339
1340 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1341 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1342 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1343
1344 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
1345 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1346
1347 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
1348 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1349
1350 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1351 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1352
1353 /* IPSR15 */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1354 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1355
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1356 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
1357 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1358
1359 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
1360 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1361 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1362
1363 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
1364 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1365 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1366 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1367
1368 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1369 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1370 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1371 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1372 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1373 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1374 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1375
1376 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1377 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1378 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1379 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1380 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1381 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1382 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1383
1384 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1385 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1386 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1387 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1388 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1389 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1390 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1391
1392 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1393 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1394 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1395 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1396 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1397 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1398 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
1399
1400 /* IPSR16 */
1401 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1402 PINMUX_IPSR_GPSR(IP16_3_0, USB2_PWEN),
1403 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1404
1405 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1406 PINMUX_IPSR_GPSR(IP16_7_4, USB2_OVC),
1407 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1408
1409 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1410 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1411 PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A),
1412
1413 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1414 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1415 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1416 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1417 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1418 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1419 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1420
1421 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1422 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1423 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1424 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1425 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1426 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1427 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1428
1429 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1430 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1431 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1432 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1433 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1434 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1435 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
1436 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
1437
1438 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1439 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1440 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1441 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1442 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1443 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1444 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1445
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1446 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1447 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1448 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1449 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1450 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1451 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1452 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1453 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
1454
1455 /* IPSR17 */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1456 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1457
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1458 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1459 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
1460 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1461 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
1462 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU1_0),
1463
1464 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1465 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1466 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1467 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1468 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1469 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1470 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1471
1472 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1473 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1474 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1475 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1476 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1477 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1478
1479 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1480 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1481 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1482 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1483 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1484 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1485 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1486 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1487 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1488
1489 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1490 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1491 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1492 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1493 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1494 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1495 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1496 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1497 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1498
1499 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1500 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1501 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1502 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1503 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
1504 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1505 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
1506 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
1507 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1508 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1509 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1510
1511 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1512 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1513 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1514 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1515 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1516 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1517 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1518 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1519 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1520
1521 /* IPSR18 */
1522 PINMUX_IPSR_GPSR(IP18_3_0, USB2_CH3_PWEN),
1523 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1524 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1525 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1526 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1527 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1528 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1529 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1530 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1531
1532 PINMUX_IPSR_GPSR(IP18_7_4, USB2_CH3_OVC),
1533 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1534 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1535 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1536 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1537 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1538 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1539 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1540 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
1541
1542/*
1543 * Static pins can not be muxed between different functions but
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1544 * still need mark entries in the pinmux list. Add each static
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1545 * pin to the list without an associated function. The sh-pfc
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1546 * core will do the right thing and skip trying to mux the pin
1547 * while still applying configuration to it.
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1548 */
1549#define FM(x) PINMUX_DATA(x##_MARK, 0),
1550 PINMUX_STATIC
1551#undef FM
1552};
1553
1554/*
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1555 * Pins not associated with a GPIO port.
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1556 */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1557enum {
1558 GP_ASSIGN_LAST(),
1559 NOGP_ALL(),
1560};
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1561
1562static const struct sh_pfc_pin pinmux_pins[] = {
1563 PINMUX_GPIO_GP_ALL(),
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1564 PINMUX_NOGP_ALL(),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1565};
1566
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1567/* - AUDIO CLOCK ------------------------------------------------------------ */
1568static const unsigned int audio_clk_a_a_pins[] = {
1569 /* CLK A */
1570 RCAR_GP_PIN(6, 22),
1571};
1572static const unsigned int audio_clk_a_a_mux[] = {
1573 AUDIO_CLKA_A_MARK,
1574};
1575static const unsigned int audio_clk_a_b_pins[] = {
1576 /* CLK A */
1577 RCAR_GP_PIN(5, 4),
1578};
1579static const unsigned int audio_clk_a_b_mux[] = {
1580 AUDIO_CLKA_B_MARK,
1581};
1582static const unsigned int audio_clk_a_c_pins[] = {
1583 /* CLK A */
1584 RCAR_GP_PIN(5, 19),
1585};
1586static const unsigned int audio_clk_a_c_mux[] = {
1587 AUDIO_CLKA_C_MARK,
1588};
1589static const unsigned int audio_clk_b_a_pins[] = {
1590 /* CLK B */
1591 RCAR_GP_PIN(5, 12),
1592};
1593static const unsigned int audio_clk_b_a_mux[] = {
1594 AUDIO_CLKB_A_MARK,
1595};
1596static const unsigned int audio_clk_b_b_pins[] = {
1597 /* CLK B */
1598 RCAR_GP_PIN(6, 23),
1599};
1600static const unsigned int audio_clk_b_b_mux[] = {
1601 AUDIO_CLKB_B_MARK,
1602};
1603static const unsigned int audio_clk_c_a_pins[] = {
1604 /* CLK C */
1605 RCAR_GP_PIN(5, 21),
1606};
1607static const unsigned int audio_clk_c_a_mux[] = {
1608 AUDIO_CLKC_A_MARK,
1609};
1610static const unsigned int audio_clk_c_b_pins[] = {
1611 /* CLK C */
1612 RCAR_GP_PIN(5, 0),
1613};
1614static const unsigned int audio_clk_c_b_mux[] = {
1615 AUDIO_CLKC_B_MARK,
1616};
1617static const unsigned int audio_clkout_a_pins[] = {
1618 /* CLKOUT */
1619 RCAR_GP_PIN(5, 18),
1620};
1621static const unsigned int audio_clkout_a_mux[] = {
1622 AUDIO_CLKOUT_A_MARK,
1623};
1624static const unsigned int audio_clkout_b_pins[] = {
1625 /* CLKOUT */
1626 RCAR_GP_PIN(6, 28),
1627};
1628static const unsigned int audio_clkout_b_mux[] = {
1629 AUDIO_CLKOUT_B_MARK,
1630};
1631static const unsigned int audio_clkout_c_pins[] = {
1632 /* CLKOUT */
1633 RCAR_GP_PIN(5, 3),
1634};
1635static const unsigned int audio_clkout_c_mux[] = {
1636 AUDIO_CLKOUT_C_MARK,
1637};
1638static const unsigned int audio_clkout_d_pins[] = {
1639 /* CLKOUT */
1640 RCAR_GP_PIN(5, 21),
1641};
1642static const unsigned int audio_clkout_d_mux[] = {
1643 AUDIO_CLKOUT_D_MARK,
1644};
1645static const unsigned int audio_clkout1_a_pins[] = {
1646 /* CLKOUT1 */
1647 RCAR_GP_PIN(5, 15),
1648};
1649static const unsigned int audio_clkout1_a_mux[] = {
1650 AUDIO_CLKOUT1_A_MARK,
1651};
1652static const unsigned int audio_clkout1_b_pins[] = {
1653 /* CLKOUT1 */
1654 RCAR_GP_PIN(6, 29),
1655};
1656static const unsigned int audio_clkout1_b_mux[] = {
1657 AUDIO_CLKOUT1_B_MARK,
1658};
1659static const unsigned int audio_clkout2_a_pins[] = {
1660 /* CLKOUT2 */
1661 RCAR_GP_PIN(5, 16),
1662};
1663static const unsigned int audio_clkout2_a_mux[] = {
1664 AUDIO_CLKOUT2_A_MARK,
1665};
1666static const unsigned int audio_clkout2_b_pins[] = {
1667 /* CLKOUT2 */
1668 RCAR_GP_PIN(6, 30),
1669};
1670static const unsigned int audio_clkout2_b_mux[] = {
1671 AUDIO_CLKOUT2_B_MARK,
1672};
1673static const unsigned int audio_clkout3_a_pins[] = {
1674 /* CLKOUT3 */
1675 RCAR_GP_PIN(5, 19),
1676};
1677static const unsigned int audio_clkout3_a_mux[] = {
1678 AUDIO_CLKOUT3_A_MARK,
1679};
1680static const unsigned int audio_clkout3_b_pins[] = {
1681 /* CLKOUT3 */
1682 RCAR_GP_PIN(6, 31),
1683};
1684static const unsigned int audio_clkout3_b_mux[] = {
1685 AUDIO_CLKOUT3_B_MARK,
1686};
1687
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1688/* - EtherAVB --------------------------------------------------------------- */
1689static const unsigned int avb_link_pins[] = {
1690 /* AVB_LINK */
1691 RCAR_GP_PIN(2, 12),
1692};
1693static const unsigned int avb_link_mux[] = {
1694 AVB_LINK_MARK,
1695};
1696static const unsigned int avb_magic_pins[] = {
1697 /* AVB_MAGIC_ */
1698 RCAR_GP_PIN(2, 10),
1699};
1700static const unsigned int avb_magic_mux[] = {
1701 AVB_MAGIC_MARK,
1702};
1703static const unsigned int avb_phy_int_pins[] = {
1704 /* AVB_PHY_INT */
1705 RCAR_GP_PIN(2, 11),
1706};
1707static const unsigned int avb_phy_int_mux[] = {
1708 AVB_PHY_INT_MARK,
1709};
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1710static const unsigned int avb_mdio_pins[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1711 /* AVB_MDC, AVB_MDIO */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1712 RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1713};
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1714static const unsigned int avb_mdio_mux[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1715 AVB_MDC_MARK, AVB_MDIO_MARK,
1716};
1717static const unsigned int avb_mii_pins[] = {
1718 /*
1719 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1720 * AVB_TD1, AVB_TD2, AVB_TD3,
1721 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1722 * AVB_RD1, AVB_RD2, AVB_RD3,
1723 * AVB_TXCREFCLK
1724 */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1725 PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
1726 PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
1727 PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
1728 PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
1729 PIN_AVB_TXCREFCLK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1730};
1731static const unsigned int avb_mii_mux[] = {
1732 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1733 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1734 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1735 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1736 AVB_TXCREFCLK_MARK,
1737};
1738static const unsigned int avb_avtp_pps_pins[] = {
1739 /* AVB_AVTP_PPS */
1740 RCAR_GP_PIN(2, 6),
1741};
1742static const unsigned int avb_avtp_pps_mux[] = {
1743 AVB_AVTP_PPS_MARK,
1744};
1745static const unsigned int avb_avtp_match_a_pins[] = {
1746 /* AVB_AVTP_MATCH_A */
1747 RCAR_GP_PIN(2, 13),
1748};
1749static const unsigned int avb_avtp_match_a_mux[] = {
1750 AVB_AVTP_MATCH_A_MARK,
1751};
1752static const unsigned int avb_avtp_capture_a_pins[] = {
1753 /* AVB_AVTP_CAPTURE_A */
1754 RCAR_GP_PIN(2, 14),
1755};
1756static const unsigned int avb_avtp_capture_a_mux[] = {
1757 AVB_AVTP_CAPTURE_A_MARK,
1758};
1759static const unsigned int avb_avtp_match_b_pins[] = {
1760 /* AVB_AVTP_MATCH_B */
1761 RCAR_GP_PIN(1, 8),
1762};
1763static const unsigned int avb_avtp_match_b_mux[] = {
1764 AVB_AVTP_MATCH_B_MARK,
1765};
1766static const unsigned int avb_avtp_capture_b_pins[] = {
1767 /* AVB_AVTP_CAPTURE_B */
1768 RCAR_GP_PIN(1, 11),
1769};
1770static const unsigned int avb_avtp_capture_b_mux[] = {
1771 AVB_AVTP_CAPTURE_B_MARK,
1772};
1773
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]1774/* - CAN ------------------------------------------------------------------ */
1775static const unsigned int can0_data_a_pins[] = {
1776 /* TX, RX */
1777 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1778};
1779static const unsigned int can0_data_a_mux[] = {
1780 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1781};
1782static const unsigned int can0_data_b_pins[] = {
1783 /* TX, RX */
1784 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1785};
1786static const unsigned int can0_data_b_mux[] = {
1787 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1788};
1789static const unsigned int can1_data_pins[] = {
1790 /* TX, RX */
1791 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1792};
1793static const unsigned int can1_data_mux[] = {
1794 CAN1_TX_MARK, CAN1_RX_MARK,
1795};
1796
1797/* - CAN Clock -------------------------------------------------------------- */
1798static const unsigned int can_clk_pins[] = {
1799 /* CLK */
1800 RCAR_GP_PIN(1, 25),
1801};
1802static const unsigned int can_clk_mux[] = {
1803 CAN_CLK_MARK,
1804};
1805
1806/* - CAN FD --------------------------------------------------------------- */
1807static const unsigned int canfd0_data_a_pins[] = {
1808 /* TX, RX */
1809 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1810};
1811static const unsigned int canfd0_data_a_mux[] = {
1812 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1813};
1814static const unsigned int canfd0_data_b_pins[] = {
1815 /* TX, RX */
1816 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1817};
1818static const unsigned int canfd0_data_b_mux[] = {
1819 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1820};
1821static const unsigned int canfd1_data_pins[] = {
1822 /* TX, RX */
1823 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1824};
1825static const unsigned int canfd1_data_mux[] = {
1826 CANFD1_TX_MARK, CANFD1_RX_MARK,
1827};
1828
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]1829#ifdef CONFIG_PINCTRL_PFC_R8A77951
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]1830/* - DRIF0 --------------------------------------------------------------- */
1831static const unsigned int drif0_ctrl_a_pins[] = {
1832 /* CLK, SYNC */
1833 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1834};
1835static const unsigned int drif0_ctrl_a_mux[] = {
1836 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1837};
1838static const unsigned int drif0_data0_a_pins[] = {
1839 /* D0 */
1840 RCAR_GP_PIN(6, 10),
1841};
1842static const unsigned int drif0_data0_a_mux[] = {
1843 RIF0_D0_A_MARK,
1844};
1845static const unsigned int drif0_data1_a_pins[] = {
1846 /* D1 */
1847 RCAR_GP_PIN(6, 7),
1848};
1849static const unsigned int drif0_data1_a_mux[] = {
1850 RIF0_D1_A_MARK,
1851};
1852static const unsigned int drif0_ctrl_b_pins[] = {
1853 /* CLK, SYNC */
1854 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1855};
1856static const unsigned int drif0_ctrl_b_mux[] = {
1857 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1858};
1859static const unsigned int drif0_data0_b_pins[] = {
1860 /* D0 */
1861 RCAR_GP_PIN(5, 1),
1862};
1863static const unsigned int drif0_data0_b_mux[] = {
1864 RIF0_D0_B_MARK,
1865};
1866static const unsigned int drif0_data1_b_pins[] = {
1867 /* D1 */
1868 RCAR_GP_PIN(5, 2),
1869};
1870static const unsigned int drif0_data1_b_mux[] = {
1871 RIF0_D1_B_MARK,
1872};
1873static const unsigned int drif0_ctrl_c_pins[] = {
1874 /* CLK, SYNC */
1875 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1876};
1877static const unsigned int drif0_ctrl_c_mux[] = {
1878 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1879};
1880static const unsigned int drif0_data0_c_pins[] = {
1881 /* D0 */
1882 RCAR_GP_PIN(5, 13),
1883};
1884static const unsigned int drif0_data0_c_mux[] = {
1885 RIF0_D0_C_MARK,
1886};
1887static const unsigned int drif0_data1_c_pins[] = {
1888 /* D1 */
1889 RCAR_GP_PIN(5, 14),
1890};
1891static const unsigned int drif0_data1_c_mux[] = {
1892 RIF0_D1_C_MARK,
1893};
1894/* - DRIF1 --------------------------------------------------------------- */
1895static const unsigned int drif1_ctrl_a_pins[] = {
1896 /* CLK, SYNC */
1897 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1898};
1899static const unsigned int drif1_ctrl_a_mux[] = {
1900 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1901};
1902static const unsigned int drif1_data0_a_pins[] = {
1903 /* D0 */
1904 RCAR_GP_PIN(6, 19),
1905};
1906static const unsigned int drif1_data0_a_mux[] = {
1907 RIF1_D0_A_MARK,
1908};
1909static const unsigned int drif1_data1_a_pins[] = {
1910 /* D1 */
1911 RCAR_GP_PIN(6, 20),
1912};
1913static const unsigned int drif1_data1_a_mux[] = {
1914 RIF1_D1_A_MARK,
1915};
1916static const unsigned int drif1_ctrl_b_pins[] = {
1917 /* CLK, SYNC */
1918 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1919};
1920static const unsigned int drif1_ctrl_b_mux[] = {
1921 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1922};
1923static const unsigned int drif1_data0_b_pins[] = {
1924 /* D0 */
1925 RCAR_GP_PIN(5, 7),
1926};
1927static const unsigned int drif1_data0_b_mux[] = {
1928 RIF1_D0_B_MARK,
1929};
1930static const unsigned int drif1_data1_b_pins[] = {
1931 /* D1 */
1932 RCAR_GP_PIN(5, 8),
1933};
1934static const unsigned int drif1_data1_b_mux[] = {
1935 RIF1_D1_B_MARK,
1936};
1937static const unsigned int drif1_ctrl_c_pins[] = {
1938 /* CLK, SYNC */
1939 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1940};
1941static const unsigned int drif1_ctrl_c_mux[] = {
1942 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1943};
1944static const unsigned int drif1_data0_c_pins[] = {
1945 /* D0 */
1946 RCAR_GP_PIN(5, 6),
1947};
1948static const unsigned int drif1_data0_c_mux[] = {
1949 RIF1_D0_C_MARK,
1950};
1951static const unsigned int drif1_data1_c_pins[] = {
1952 /* D1 */
1953 RCAR_GP_PIN(5, 10),
1954};
1955static const unsigned int drif1_data1_c_mux[] = {
1956 RIF1_D1_C_MARK,
1957};
1958/* - DRIF2 --------------------------------------------------------------- */
1959static const unsigned int drif2_ctrl_a_pins[] = {
1960 /* CLK, SYNC */
1961 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1962};
1963static const unsigned int drif2_ctrl_a_mux[] = {
1964 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1965};
1966static const unsigned int drif2_data0_a_pins[] = {
1967 /* D0 */
1968 RCAR_GP_PIN(6, 7),
1969};
1970static const unsigned int drif2_data0_a_mux[] = {
1971 RIF2_D0_A_MARK,
1972};
1973static const unsigned int drif2_data1_a_pins[] = {
1974 /* D1 */
1975 RCAR_GP_PIN(6, 10),
1976};
1977static const unsigned int drif2_data1_a_mux[] = {
1978 RIF2_D1_A_MARK,
1979};
1980static const unsigned int drif2_ctrl_b_pins[] = {
1981 /* CLK, SYNC */
1982 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1983};
1984static const unsigned int drif2_ctrl_b_mux[] = {
1985 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1986};
1987static const unsigned int drif2_data0_b_pins[] = {
1988 /* D0 */
1989 RCAR_GP_PIN(6, 30),
1990};
1991static const unsigned int drif2_data0_b_mux[] = {
1992 RIF2_D0_B_MARK,
1993};
1994static const unsigned int drif2_data1_b_pins[] = {
1995 /* D1 */
1996 RCAR_GP_PIN(6, 31),
1997};
1998static const unsigned int drif2_data1_b_mux[] = {
1999 RIF2_D1_B_MARK,
2000};
2001/* - DRIF3 --------------------------------------------------------------- */
2002static const unsigned int drif3_ctrl_a_pins[] = {
2003 /* CLK, SYNC */
2004 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2005};
2006static const unsigned int drif3_ctrl_a_mux[] = {
2007 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2008};
2009static const unsigned int drif3_data0_a_pins[] = {
2010 /* D0 */
2011 RCAR_GP_PIN(6, 19),
2012};
2013static const unsigned int drif3_data0_a_mux[] = {
2014 RIF3_D0_A_MARK,
2015};
2016static const unsigned int drif3_data1_a_pins[] = {
2017 /* D1 */
2018 RCAR_GP_PIN(6, 20),
2019};
2020static const unsigned int drif3_data1_a_mux[] = {
2021 RIF3_D1_A_MARK,
2022};
2023static const unsigned int drif3_ctrl_b_pins[] = {
2024 /* CLK, SYNC */
2025 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2026};
2027static const unsigned int drif3_ctrl_b_mux[] = {
2028 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2029};
2030static const unsigned int drif3_data0_b_pins[] = {
2031 /* D0 */
2032 RCAR_GP_PIN(6, 28),
2033};
2034static const unsigned int drif3_data0_b_mux[] = {
2035 RIF3_D0_B_MARK,
2036};
2037static const unsigned int drif3_data1_b_pins[] = {
2038 /* D1 */
2039 RCAR_GP_PIN(6, 29),
2040};
2041static const unsigned int drif3_data1_b_mux[] = {
2042 RIF3_D1_B_MARK,
2043};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]2044#endif /* CONFIG_PINCTRL_PFC_R8A77951 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]2045
2046/* - DU --------------------------------------------------------------------- */
2047static const unsigned int du_rgb666_pins[] = {
2048 /* R[7:2], G[7:2], B[7:2] */
2049 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2050 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2051 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2052 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2053 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2054 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2055};
2056static const unsigned int du_rgb666_mux[] = {
2057 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2058 DU_DR3_MARK, DU_DR2_MARK,
2059 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2060 DU_DG3_MARK, DU_DG2_MARK,
2061 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2062 DU_DB3_MARK, DU_DB2_MARK,
2063};
2064static const unsigned int du_rgb888_pins[] = {
2065 /* R[7:0], G[7:0], B[7:0] */
2066 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2067 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2068 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
2069 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2070 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2071 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2072 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2073 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2074 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2075};
2076static const unsigned int du_rgb888_mux[] = {
2077 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2078 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2079 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2080 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2081 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2082 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2083};
2084static const unsigned int du_clk_out_0_pins[] = {
2085 /* CLKOUT */
2086 RCAR_GP_PIN(1, 27),
2087};
2088static const unsigned int du_clk_out_0_mux[] = {
2089 DU_DOTCLKOUT0_MARK
2090};
2091static const unsigned int du_clk_out_1_pins[] = {
2092 /* CLKOUT */
2093 RCAR_GP_PIN(2, 3),
2094};
2095static const unsigned int du_clk_out_1_mux[] = {
2096 DU_DOTCLKOUT1_MARK
2097};
2098static const unsigned int du_sync_pins[] = {
2099 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2100 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2101};
2102static const unsigned int du_sync_mux[] = {
2103 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2104};
2105static const unsigned int du_oddf_pins[] = {
2106 /* EXDISP/EXODDF/EXCDE */
2107 RCAR_GP_PIN(2, 2),
2108};
2109static const unsigned int du_oddf_mux[] = {
2110 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2111};
2112static const unsigned int du_cde_pins[] = {
2113 /* CDE */
2114 RCAR_GP_PIN(2, 0),
2115};
2116static const unsigned int du_cde_mux[] = {
2117 DU_CDE_MARK,
2118};
2119static const unsigned int du_disp_pins[] = {
2120 /* DISP */
2121 RCAR_GP_PIN(2, 1),
2122};
2123static const unsigned int du_disp_mux[] = {
2124 DU_DISP_MARK,
2125};
2126
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]2127/* - HSCIF0 ----------------------------------------------------------------- */
2128static const unsigned int hscif0_data_pins[] = {
2129 /* RX, TX */
2130 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2131};
2132static const unsigned int hscif0_data_mux[] = {
2133 HRX0_MARK, HTX0_MARK,
2134};
2135static const unsigned int hscif0_clk_pins[] = {
2136 /* SCK */
2137 RCAR_GP_PIN(5, 12),
2138};
2139static const unsigned int hscif0_clk_mux[] = {
2140 HSCK0_MARK,
2141};
2142static const unsigned int hscif0_ctrl_pins[] = {
2143 /* RTS, CTS */
2144 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2145};
2146static const unsigned int hscif0_ctrl_mux[] = {
2147 HRTS0_N_MARK, HCTS0_N_MARK,
2148};
2149/* - HSCIF1 ----------------------------------------------------------------- */
2150static const unsigned int hscif1_data_a_pins[] = {
2151 /* RX, TX */
2152 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2153};
2154static const unsigned int hscif1_data_a_mux[] = {
2155 HRX1_A_MARK, HTX1_A_MARK,
2156};
2157static const unsigned int hscif1_clk_a_pins[] = {
2158 /* SCK */
2159 RCAR_GP_PIN(6, 21),
2160};
2161static const unsigned int hscif1_clk_a_mux[] = {
2162 HSCK1_A_MARK,
2163};
2164static const unsigned int hscif1_ctrl_a_pins[] = {
2165 /* RTS, CTS */
2166 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2167};
2168static const unsigned int hscif1_ctrl_a_mux[] = {
2169 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2170};
2171
2172static const unsigned int hscif1_data_b_pins[] = {
2173 /* RX, TX */
2174 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2175};
2176static const unsigned int hscif1_data_b_mux[] = {
2177 HRX1_B_MARK, HTX1_B_MARK,
2178};
2179static const unsigned int hscif1_clk_b_pins[] = {
2180 /* SCK */
2181 RCAR_GP_PIN(5, 0),
2182};
2183static const unsigned int hscif1_clk_b_mux[] = {
2184 HSCK1_B_MARK,
2185};
2186static const unsigned int hscif1_ctrl_b_pins[] = {
2187 /* RTS, CTS */
2188 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2189};
2190static const unsigned int hscif1_ctrl_b_mux[] = {
2191 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2192};
2193/* - HSCIF2 ----------------------------------------------------------------- */
2194static const unsigned int hscif2_data_a_pins[] = {
2195 /* RX, TX */
2196 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2197};
2198static const unsigned int hscif2_data_a_mux[] = {
2199 HRX2_A_MARK, HTX2_A_MARK,
2200};
2201static const unsigned int hscif2_clk_a_pins[] = {
2202 /* SCK */
2203 RCAR_GP_PIN(6, 10),
2204};
2205static const unsigned int hscif2_clk_a_mux[] = {
2206 HSCK2_A_MARK,
2207};
2208static const unsigned int hscif2_ctrl_a_pins[] = {
2209 /* RTS, CTS */
2210 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2211};
2212static const unsigned int hscif2_ctrl_a_mux[] = {
2213 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2214};
2215
2216static const unsigned int hscif2_data_b_pins[] = {
2217 /* RX, TX */
2218 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2219};
2220static const unsigned int hscif2_data_b_mux[] = {
2221 HRX2_B_MARK, HTX2_B_MARK,
2222};
2223static const unsigned int hscif2_clk_b_pins[] = {
2224 /* SCK */
2225 RCAR_GP_PIN(6, 21),
2226};
2227static const unsigned int hscif2_clk_b_mux[] = {
2228 HSCK2_B_MARK,
2229};
2230static const unsigned int hscif2_ctrl_b_pins[] = {
2231 /* RTS, CTS */
2232 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2233};
2234static const unsigned int hscif2_ctrl_b_mux[] = {
2235 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2236};
2237
2238static const unsigned int hscif2_data_c_pins[] = {
2239 /* RX, TX */
2240 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2241};
2242static const unsigned int hscif2_data_c_mux[] = {
2243 HRX2_C_MARK, HTX2_C_MARK,
2244};
2245static const unsigned int hscif2_clk_c_pins[] = {
2246 /* SCK */
2247 RCAR_GP_PIN(6, 24),
2248};
2249static const unsigned int hscif2_clk_c_mux[] = {
2250 HSCK2_C_MARK,
2251};
2252static const unsigned int hscif2_ctrl_c_pins[] = {
2253 /* RTS, CTS */
2254 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2255};
2256static const unsigned int hscif2_ctrl_c_mux[] = {
2257 HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2258};
2259/* - HSCIF3 ----------------------------------------------------------------- */
2260static const unsigned int hscif3_data_a_pins[] = {
2261 /* RX, TX */
2262 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2263};
2264static const unsigned int hscif3_data_a_mux[] = {
2265 HRX3_A_MARK, HTX3_A_MARK,
2266};
2267static const unsigned int hscif3_clk_pins[] = {
2268 /* SCK */
2269 RCAR_GP_PIN(1, 22),
2270};
2271static const unsigned int hscif3_clk_mux[] = {
2272 HSCK3_MARK,
2273};
2274static const unsigned int hscif3_ctrl_pins[] = {
2275 /* RTS, CTS */
2276 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2277};
2278static const unsigned int hscif3_ctrl_mux[] = {
2279 HRTS3_N_MARK, HCTS3_N_MARK,
2280};
2281
2282static const unsigned int hscif3_data_b_pins[] = {
2283 /* RX, TX */
2284 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2285};
2286static const unsigned int hscif3_data_b_mux[] = {
2287 HRX3_B_MARK, HTX3_B_MARK,
2288};
2289static const unsigned int hscif3_data_c_pins[] = {
2290 /* RX, TX */
2291 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2292};
2293static const unsigned int hscif3_data_c_mux[] = {
2294 HRX3_C_MARK, HTX3_C_MARK,
2295};
2296static const unsigned int hscif3_data_d_pins[] = {
2297 /* RX, TX */
2298 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2299};
2300static const unsigned int hscif3_data_d_mux[] = {
2301 HRX3_D_MARK, HTX3_D_MARK,
2302};
2303/* - HSCIF4 ----------------------------------------------------------------- */
2304static const unsigned int hscif4_data_a_pins[] = {
2305 /* RX, TX */
2306 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2307};
2308static const unsigned int hscif4_data_a_mux[] = {
2309 HRX4_A_MARK, HTX4_A_MARK,
2310};
2311static const unsigned int hscif4_clk_pins[] = {
2312 /* SCK */
2313 RCAR_GP_PIN(1, 11),
2314};
2315static const unsigned int hscif4_clk_mux[] = {
2316 HSCK4_MARK,
2317};
2318static const unsigned int hscif4_ctrl_pins[] = {
2319 /* RTS, CTS */
2320 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2321};
2322static const unsigned int hscif4_ctrl_mux[] = {
2323 HRTS4_N_MARK, HCTS4_N_MARK,
2324};
2325
2326static const unsigned int hscif4_data_b_pins[] = {
2327 /* RX, TX */
2328 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2329};
2330static const unsigned int hscif4_data_b_mux[] = {
2331 HRX4_B_MARK, HTX4_B_MARK,
2332};
2333
2334/* - I2C -------------------------------------------------------------------- */
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]2335static const unsigned int i2c0_pins[] = {
2336 /* SCL, SDA */
2337 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2338};
2339
2340static const unsigned int i2c0_mux[] = {
2341 SCL0_MARK, SDA0_MARK,
2342};
2343
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]2344static const unsigned int i2c1_a_pins[] = {
2345 /* SDA, SCL */
2346 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2347};
2348static const unsigned int i2c1_a_mux[] = {
2349 SDA1_A_MARK, SCL1_A_MARK,
2350};
2351static const unsigned int i2c1_b_pins[] = {
2352 /* SDA, SCL */
2353 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2354};
2355static const unsigned int i2c1_b_mux[] = {
2356 SDA1_B_MARK, SCL1_B_MARK,
2357};
2358static const unsigned int i2c2_a_pins[] = {
2359 /* SDA, SCL */
2360 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2361};
2362static const unsigned int i2c2_a_mux[] = {
2363 SDA2_A_MARK, SCL2_A_MARK,
2364};
2365static const unsigned int i2c2_b_pins[] = {
2366 /* SDA, SCL */
2367 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2368};
2369static const unsigned int i2c2_b_mux[] = {
2370 SDA2_B_MARK, SCL2_B_MARK,
2371};
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]2372
2373static const unsigned int i2c3_pins[] = {
2374 /* SCL, SDA */
2375 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2376};
2377
2378static const unsigned int i2c3_mux[] = {
2379 SCL3_MARK, SDA3_MARK,
2380};
2381
2382static const unsigned int i2c5_pins[] = {
2383 /* SCL, SDA */
2384 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
2385};
2386
2387static const unsigned int i2c5_mux[] = {
2388 SCL5_MARK, SDA5_MARK,
2389};
2390
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]2391static const unsigned int i2c6_a_pins[] = {
2392 /* SDA, SCL */
2393 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2394};
2395static const unsigned int i2c6_a_mux[] = {
2396 SDA6_A_MARK, SCL6_A_MARK,
2397};
2398static const unsigned int i2c6_b_pins[] = {
2399 /* SDA, SCL */
2400 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2401};
2402static const unsigned int i2c6_b_mux[] = {
2403 SDA6_B_MARK, SCL6_B_MARK,
2404};
2405static const unsigned int i2c6_c_pins[] = {
2406 /* SDA, SCL */
2407 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2408};
2409static const unsigned int i2c6_c_mux[] = {
2410 SDA6_C_MARK, SCL6_C_MARK,
2411};
2412
2413/* - INTC-EX ---------------------------------------------------------------- */
2414static const unsigned int intc_ex_irq0_pins[] = {
2415 /* IRQ0 */
2416 RCAR_GP_PIN(2, 0),
2417};
2418static const unsigned int intc_ex_irq0_mux[] = {
2419 IRQ0_MARK,
2420};
2421static const unsigned int intc_ex_irq1_pins[] = {
2422 /* IRQ1 */
2423 RCAR_GP_PIN(2, 1),
2424};
2425static const unsigned int intc_ex_irq1_mux[] = {
2426 IRQ1_MARK,
2427};
2428static const unsigned int intc_ex_irq2_pins[] = {
2429 /* IRQ2 */
2430 RCAR_GP_PIN(2, 2),
2431};
2432static const unsigned int intc_ex_irq2_mux[] = {
2433 IRQ2_MARK,
2434};
2435static const unsigned int intc_ex_irq3_pins[] = {
2436 /* IRQ3 */
2437 RCAR_GP_PIN(2, 3),
2438};
2439static const unsigned int intc_ex_irq3_mux[] = {
2440 IRQ3_MARK,
2441};
2442static const unsigned int intc_ex_irq4_pins[] = {
2443 /* IRQ4 */
2444 RCAR_GP_PIN(2, 4),
2445};
2446static const unsigned int intc_ex_irq4_mux[] = {
2447 IRQ4_MARK,
2448};
2449static const unsigned int intc_ex_irq5_pins[] = {
2450 /* IRQ5 */
2451 RCAR_GP_PIN(2, 5),
2452};
2453static const unsigned int intc_ex_irq5_mux[] = {
2454 IRQ5_MARK,
2455};
2456
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]2457#ifdef CONFIG_PINCTRL_PFC_R8A77951
2458/* - MLB+ ------------------------------------------------------------------- */
2459static const unsigned int mlb_3pin_pins[] = {
2460 RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
2461};
2462static const unsigned int mlb_3pin_mux[] = {
2463 MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
2464};
2465#endif /* CONFIG_PINCTRL_PFC_R8A77951 */
2466
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]2467/* - MSIOF0 ----------------------------------------------------------------- */
2468static const unsigned int msiof0_clk_pins[] = {
2469 /* SCK */
2470 RCAR_GP_PIN(5, 17),
2471};
2472static const unsigned int msiof0_clk_mux[] = {
2473 MSIOF0_SCK_MARK,
2474};
2475static const unsigned int msiof0_sync_pins[] = {
2476 /* SYNC */
2477 RCAR_GP_PIN(5, 18),
2478};
2479static const unsigned int msiof0_sync_mux[] = {
2480 MSIOF0_SYNC_MARK,
2481};
2482static const unsigned int msiof0_ss1_pins[] = {
2483 /* SS1 */
2484 RCAR_GP_PIN(5, 19),
2485};
2486static const unsigned int msiof0_ss1_mux[] = {
2487 MSIOF0_SS1_MARK,
2488};
2489static const unsigned int msiof0_ss2_pins[] = {
2490 /* SS2 */
2491 RCAR_GP_PIN(5, 21),
2492};
2493static const unsigned int msiof0_ss2_mux[] = {
2494 MSIOF0_SS2_MARK,
2495};
2496static const unsigned int msiof0_txd_pins[] = {
2497 /* TXD */
2498 RCAR_GP_PIN(5, 20),
2499};
2500static const unsigned int msiof0_txd_mux[] = {
2501 MSIOF0_TXD_MARK,
2502};
2503static const unsigned int msiof0_rxd_pins[] = {
2504 /* RXD */
2505 RCAR_GP_PIN(5, 22),
2506};
2507static const unsigned int msiof0_rxd_mux[] = {
2508 MSIOF0_RXD_MARK,
2509};
2510/* - MSIOF1 ----------------------------------------------------------------- */
2511static const unsigned int msiof1_clk_a_pins[] = {
2512 /* SCK */
2513 RCAR_GP_PIN(6, 8),
2514};
2515static const unsigned int msiof1_clk_a_mux[] = {
2516 MSIOF1_SCK_A_MARK,
2517};
2518static const unsigned int msiof1_sync_a_pins[] = {
2519 /* SYNC */
2520 RCAR_GP_PIN(6, 9),
2521};
2522static const unsigned int msiof1_sync_a_mux[] = {
2523 MSIOF1_SYNC_A_MARK,
2524};
2525static const unsigned int msiof1_ss1_a_pins[] = {
2526 /* SS1 */
2527 RCAR_GP_PIN(6, 5),
2528};
2529static const unsigned int msiof1_ss1_a_mux[] = {
2530 MSIOF1_SS1_A_MARK,
2531};
2532static const unsigned int msiof1_ss2_a_pins[] = {
2533 /* SS2 */
2534 RCAR_GP_PIN(6, 6),
2535};
2536static const unsigned int msiof1_ss2_a_mux[] = {
2537 MSIOF1_SS2_A_MARK,
2538};
2539static const unsigned int msiof1_txd_a_pins[] = {
2540 /* TXD */
2541 RCAR_GP_PIN(6, 7),
2542};
2543static const unsigned int msiof1_txd_a_mux[] = {
2544 MSIOF1_TXD_A_MARK,
2545};
2546static const unsigned int msiof1_rxd_a_pins[] = {
2547 /* RXD */
2548 RCAR_GP_PIN(6, 10),
2549};
2550static const unsigned int msiof1_rxd_a_mux[] = {
2551 MSIOF1_RXD_A_MARK,
2552};
2553static const unsigned int msiof1_clk_b_pins[] = {
2554 /* SCK */
2555 RCAR_GP_PIN(5, 9),
2556};
2557static const unsigned int msiof1_clk_b_mux[] = {
2558 MSIOF1_SCK_B_MARK,
2559};
2560static const unsigned int msiof1_sync_b_pins[] = {
2561 /* SYNC */
2562 RCAR_GP_PIN(5, 3),
2563};
2564static const unsigned int msiof1_sync_b_mux[] = {
2565 MSIOF1_SYNC_B_MARK,
2566};
2567static const unsigned int msiof1_ss1_b_pins[] = {
2568 /* SS1 */
2569 RCAR_GP_PIN(5, 4),
2570};
2571static const unsigned int msiof1_ss1_b_mux[] = {
2572 MSIOF1_SS1_B_MARK,
2573};
2574static const unsigned int msiof1_ss2_b_pins[] = {
2575 /* SS2 */
2576 RCAR_GP_PIN(5, 0),
2577};
2578static const unsigned int msiof1_ss2_b_mux[] = {
2579 MSIOF1_SS2_B_MARK,
2580};
2581static const unsigned int msiof1_txd_b_pins[] = {
2582 /* TXD */
2583 RCAR_GP_PIN(5, 8),
2584};
2585static const unsigned int msiof1_txd_b_mux[] = {
2586 MSIOF1_TXD_B_MARK,
2587};
2588static const unsigned int msiof1_rxd_b_pins[] = {
2589 /* RXD */
2590 RCAR_GP_PIN(5, 7),
2591};
2592static const unsigned int msiof1_rxd_b_mux[] = {
2593 MSIOF1_RXD_B_MARK,
2594};
2595static const unsigned int msiof1_clk_c_pins[] = {
2596 /* SCK */
2597 RCAR_GP_PIN(6, 17),
2598};
2599static const unsigned int msiof1_clk_c_mux[] = {
2600 MSIOF1_SCK_C_MARK,
2601};
2602static const unsigned int msiof1_sync_c_pins[] = {
2603 /* SYNC */
2604 RCAR_GP_PIN(6, 18),
2605};
2606static const unsigned int msiof1_sync_c_mux[] = {
2607 MSIOF1_SYNC_C_MARK,
2608};
2609static const unsigned int msiof1_ss1_c_pins[] = {
2610 /* SS1 */
2611 RCAR_GP_PIN(6, 21),
2612};
2613static const unsigned int msiof1_ss1_c_mux[] = {
2614 MSIOF1_SS1_C_MARK,
2615};
2616static const unsigned int msiof1_ss2_c_pins[] = {
2617 /* SS2 */
2618 RCAR_GP_PIN(6, 27),
2619};
2620static const unsigned int msiof1_ss2_c_mux[] = {
2621 MSIOF1_SS2_C_MARK,
2622};
2623static const unsigned int msiof1_txd_c_pins[] = {
2624 /* TXD */
2625 RCAR_GP_PIN(6, 20),
2626};
2627static const unsigned int msiof1_txd_c_mux[] = {
2628 MSIOF1_TXD_C_MARK,
2629};
2630static const unsigned int msiof1_rxd_c_pins[] = {
2631 /* RXD */
2632 RCAR_GP_PIN(6, 19),
2633};
2634static const unsigned int msiof1_rxd_c_mux[] = {
2635 MSIOF1_RXD_C_MARK,
2636};
2637static const unsigned int msiof1_clk_d_pins[] = {
2638 /* SCK */
2639 RCAR_GP_PIN(5, 12),
2640};
2641static const unsigned int msiof1_clk_d_mux[] = {
2642 MSIOF1_SCK_D_MARK,
2643};
2644static const unsigned int msiof1_sync_d_pins[] = {
2645 /* SYNC */
2646 RCAR_GP_PIN(5, 15),
2647};
2648static const unsigned int msiof1_sync_d_mux[] = {
2649 MSIOF1_SYNC_D_MARK,
2650};
2651static const unsigned int msiof1_ss1_d_pins[] = {
2652 /* SS1 */
2653 RCAR_GP_PIN(5, 16),
2654};
2655static const unsigned int msiof1_ss1_d_mux[] = {
2656 MSIOF1_SS1_D_MARK,
2657};
2658static const unsigned int msiof1_ss2_d_pins[] = {
2659 /* SS2 */
2660 RCAR_GP_PIN(5, 21),
2661};
2662static const unsigned int msiof1_ss2_d_mux[] = {
2663 MSIOF1_SS2_D_MARK,
2664};
2665static const unsigned int msiof1_txd_d_pins[] = {
2666 /* TXD */
2667 RCAR_GP_PIN(5, 14),
2668};
2669static const unsigned int msiof1_txd_d_mux[] = {
2670 MSIOF1_TXD_D_MARK,
2671};
2672static const unsigned int msiof1_rxd_d_pins[] = {
2673 /* RXD */
2674 RCAR_GP_PIN(5, 13),
2675};
2676static const unsigned int msiof1_rxd_d_mux[] = {
2677 MSIOF1_RXD_D_MARK,
2678};
2679static const unsigned int msiof1_clk_e_pins[] = {
2680 /* SCK */
2681 RCAR_GP_PIN(3, 0),
2682};
2683static const unsigned int msiof1_clk_e_mux[] = {
2684 MSIOF1_SCK_E_MARK,
2685};
2686static const unsigned int msiof1_sync_e_pins[] = {
2687 /* SYNC */
2688 RCAR_GP_PIN(3, 1),
2689};
2690static const unsigned int msiof1_sync_e_mux[] = {
2691 MSIOF1_SYNC_E_MARK,
2692};
2693static const unsigned int msiof1_ss1_e_pins[] = {
2694 /* SS1 */
2695 RCAR_GP_PIN(3, 4),
2696};
2697static const unsigned int msiof1_ss1_e_mux[] = {
2698 MSIOF1_SS1_E_MARK,
2699};
2700static const unsigned int msiof1_ss2_e_pins[] = {
2701 /* SS2 */
2702 RCAR_GP_PIN(3, 5),
2703};
2704static const unsigned int msiof1_ss2_e_mux[] = {
2705 MSIOF1_SS2_E_MARK,
2706};
2707static const unsigned int msiof1_txd_e_pins[] = {
2708 /* TXD */
2709 RCAR_GP_PIN(3, 3),
2710};
2711static const unsigned int msiof1_txd_e_mux[] = {
2712 MSIOF1_TXD_E_MARK,
2713};
2714static const unsigned int msiof1_rxd_e_pins[] = {
2715 /* RXD */
2716 RCAR_GP_PIN(3, 2),
2717};
2718static const unsigned int msiof1_rxd_e_mux[] = {
2719 MSIOF1_RXD_E_MARK,
2720};
2721static const unsigned int msiof1_clk_f_pins[] = {
2722 /* SCK */
2723 RCAR_GP_PIN(5, 23),
2724};
2725static const unsigned int msiof1_clk_f_mux[] = {
2726 MSIOF1_SCK_F_MARK,
2727};
2728static const unsigned int msiof1_sync_f_pins[] = {
2729 /* SYNC */
2730 RCAR_GP_PIN(5, 24),
2731};
2732static const unsigned int msiof1_sync_f_mux[] = {
2733 MSIOF1_SYNC_F_MARK,
2734};
2735static const unsigned int msiof1_ss1_f_pins[] = {
2736 /* SS1 */
2737 RCAR_GP_PIN(6, 1),
2738};
2739static const unsigned int msiof1_ss1_f_mux[] = {
2740 MSIOF1_SS1_F_MARK,
2741};
2742static const unsigned int msiof1_ss2_f_pins[] = {
2743 /* SS2 */
2744 RCAR_GP_PIN(6, 2),
2745};
2746static const unsigned int msiof1_ss2_f_mux[] = {
2747 MSIOF1_SS2_F_MARK,
2748};
2749static const unsigned int msiof1_txd_f_pins[] = {
2750 /* TXD */
2751 RCAR_GP_PIN(6, 0),
2752};
2753static const unsigned int msiof1_txd_f_mux[] = {
2754 MSIOF1_TXD_F_MARK,
2755};
2756static const unsigned int msiof1_rxd_f_pins[] = {
2757 /* RXD */
2758 RCAR_GP_PIN(5, 25),
2759};
2760static const unsigned int msiof1_rxd_f_mux[] = {
2761 MSIOF1_RXD_F_MARK,
2762};
2763static const unsigned int msiof1_clk_g_pins[] = {
2764 /* SCK */
2765 RCAR_GP_PIN(3, 6),
2766};
2767static const unsigned int msiof1_clk_g_mux[] = {
2768 MSIOF1_SCK_G_MARK,
2769};
2770static const unsigned int msiof1_sync_g_pins[] = {
2771 /* SYNC */
2772 RCAR_GP_PIN(3, 7),
2773};
2774static const unsigned int msiof1_sync_g_mux[] = {
2775 MSIOF1_SYNC_G_MARK,
2776};
2777static const unsigned int msiof1_ss1_g_pins[] = {
2778 /* SS1 */
2779 RCAR_GP_PIN(3, 10),
2780};
2781static const unsigned int msiof1_ss1_g_mux[] = {
2782 MSIOF1_SS1_G_MARK,
2783};
2784static const unsigned int msiof1_ss2_g_pins[] = {
2785 /* SS2 */
2786 RCAR_GP_PIN(3, 11),
2787};
2788static const unsigned int msiof1_ss2_g_mux[] = {
2789 MSIOF1_SS2_G_MARK,
2790};
2791static const unsigned int msiof1_txd_g_pins[] = {
2792 /* TXD */
2793 RCAR_GP_PIN(3, 9),
2794};
2795static const unsigned int msiof1_txd_g_mux[] = {
2796 MSIOF1_TXD_G_MARK,
2797};
2798static const unsigned int msiof1_rxd_g_pins[] = {
2799 /* RXD */
2800 RCAR_GP_PIN(3, 8),
2801};
2802static const unsigned int msiof1_rxd_g_mux[] = {
2803 MSIOF1_RXD_G_MARK,
2804};
2805/* - MSIOF2 ----------------------------------------------------------------- */
2806static const unsigned int msiof2_clk_a_pins[] = {
2807 /* SCK */
2808 RCAR_GP_PIN(1, 9),
2809};
2810static const unsigned int msiof2_clk_a_mux[] = {
2811 MSIOF2_SCK_A_MARK,
2812};
2813static const unsigned int msiof2_sync_a_pins[] = {
2814 /* SYNC */
2815 RCAR_GP_PIN(1, 8),
2816};
2817static const unsigned int msiof2_sync_a_mux[] = {
2818 MSIOF2_SYNC_A_MARK,
2819};
2820static const unsigned int msiof2_ss1_a_pins[] = {
2821 /* SS1 */
2822 RCAR_GP_PIN(1, 6),
2823};
2824static const unsigned int msiof2_ss1_a_mux[] = {
2825 MSIOF2_SS1_A_MARK,
2826};
2827static const unsigned int msiof2_ss2_a_pins[] = {
2828 /* SS2 */
2829 RCAR_GP_PIN(1, 7),
2830};
2831static const unsigned int msiof2_ss2_a_mux[] = {
2832 MSIOF2_SS2_A_MARK,
2833};
2834static const unsigned int msiof2_txd_a_pins[] = {
2835 /* TXD */
2836 RCAR_GP_PIN(1, 11),
2837};
2838static const unsigned int msiof2_txd_a_mux[] = {
2839 MSIOF2_TXD_A_MARK,
2840};
2841static const unsigned int msiof2_rxd_a_pins[] = {
2842 /* RXD */
2843 RCAR_GP_PIN(1, 10),
2844};
2845static const unsigned int msiof2_rxd_a_mux[] = {
2846 MSIOF2_RXD_A_MARK,
2847};
2848static const unsigned int msiof2_clk_b_pins[] = {
2849 /* SCK */
2850 RCAR_GP_PIN(0, 4),
2851};
2852static const unsigned int msiof2_clk_b_mux[] = {
2853 MSIOF2_SCK_B_MARK,
2854};
2855static const unsigned int msiof2_sync_b_pins[] = {
2856 /* SYNC */
2857 RCAR_GP_PIN(0, 5),
2858};
2859static const unsigned int msiof2_sync_b_mux[] = {
2860 MSIOF2_SYNC_B_MARK,
2861};
2862static const unsigned int msiof2_ss1_b_pins[] = {
2863 /* SS1 */
2864 RCAR_GP_PIN(0, 0),
2865};
2866static const unsigned int msiof2_ss1_b_mux[] = {
2867 MSIOF2_SS1_B_MARK,
2868};
2869static const unsigned int msiof2_ss2_b_pins[] = {
2870 /* SS2 */
2871 RCAR_GP_PIN(0, 1),
2872};
2873static const unsigned int msiof2_ss2_b_mux[] = {
2874 MSIOF2_SS2_B_MARK,
2875};
2876static const unsigned int msiof2_txd_b_pins[] = {
2877 /* TXD */
2878 RCAR_GP_PIN(0, 7),
2879};
2880static const unsigned int msiof2_txd_b_mux[] = {
2881 MSIOF2_TXD_B_MARK,
2882};
2883static const unsigned int msiof2_rxd_b_pins[] = {
2884 /* RXD */
2885 RCAR_GP_PIN(0, 6),
2886};
2887static const unsigned int msiof2_rxd_b_mux[] = {
2888 MSIOF2_RXD_B_MARK,
2889};
2890static const unsigned int msiof2_clk_c_pins[] = {
2891 /* SCK */
2892 RCAR_GP_PIN(2, 12),
2893};
2894static const unsigned int msiof2_clk_c_mux[] = {
2895 MSIOF2_SCK_C_MARK,
2896};
2897static const unsigned int msiof2_sync_c_pins[] = {
2898 /* SYNC */
2899 RCAR_GP_PIN(2, 11),
2900};
2901static const unsigned int msiof2_sync_c_mux[] = {
2902 MSIOF2_SYNC_C_MARK,
2903};
2904static const unsigned int msiof2_ss1_c_pins[] = {
2905 /* SS1 */
2906 RCAR_GP_PIN(2, 10),
2907};
2908static const unsigned int msiof2_ss1_c_mux[] = {
2909 MSIOF2_SS1_C_MARK,
2910};
2911static const unsigned int msiof2_ss2_c_pins[] = {
2912 /* SS2 */
2913 RCAR_GP_PIN(2, 9),
2914};
2915static const unsigned int msiof2_ss2_c_mux[] = {
2916 MSIOF2_SS2_C_MARK,
2917};
2918static const unsigned int msiof2_txd_c_pins[] = {
2919 /* TXD */
2920 RCAR_GP_PIN(2, 14),
2921};
2922static const unsigned int msiof2_txd_c_mux[] = {
2923 MSIOF2_TXD_C_MARK,
2924};
2925static const unsigned int msiof2_rxd_c_pins[] = {
2926 /* RXD */
2927 RCAR_GP_PIN(2, 13),
2928};
2929static const unsigned int msiof2_rxd_c_mux[] = {
2930 MSIOF2_RXD_C_MARK,
2931};
2932static const unsigned int msiof2_clk_d_pins[] = {
2933 /* SCK */
2934 RCAR_GP_PIN(0, 8),
2935};
2936static const unsigned int msiof2_clk_d_mux[] = {
2937 MSIOF2_SCK_D_MARK,
2938};
2939static const unsigned int msiof2_sync_d_pins[] = {
2940 /* SYNC */
2941 RCAR_GP_PIN(0, 9),
2942};
2943static const unsigned int msiof2_sync_d_mux[] = {
2944 MSIOF2_SYNC_D_MARK,
2945};
2946static const unsigned int msiof2_ss1_d_pins[] = {
2947 /* SS1 */
2948 RCAR_GP_PIN(0, 12),
2949};
2950static const unsigned int msiof2_ss1_d_mux[] = {
2951 MSIOF2_SS1_D_MARK,
2952};
2953static const unsigned int msiof2_ss2_d_pins[] = {
2954 /* SS2 */
2955 RCAR_GP_PIN(0, 13),
2956};
2957static const unsigned int msiof2_ss2_d_mux[] = {
2958 MSIOF2_SS2_D_MARK,
2959};
2960static const unsigned int msiof2_txd_d_pins[] = {
2961 /* TXD */
2962 RCAR_GP_PIN(0, 11),
2963};
2964static const unsigned int msiof2_txd_d_mux[] = {
2965 MSIOF2_TXD_D_MARK,
2966};
2967static const unsigned int msiof2_rxd_d_pins[] = {
2968 /* RXD */
2969 RCAR_GP_PIN(0, 10),
2970};
2971static const unsigned int msiof2_rxd_d_mux[] = {
2972 MSIOF2_RXD_D_MARK,
2973};
2974/* - MSIOF3 ----------------------------------------------------------------- */
2975static const unsigned int msiof3_clk_a_pins[] = {
2976 /* SCK */
2977 RCAR_GP_PIN(0, 0),
2978};
2979static const unsigned int msiof3_clk_a_mux[] = {
2980 MSIOF3_SCK_A_MARK,
2981};
2982static const unsigned int msiof3_sync_a_pins[] = {
2983 /* SYNC */
2984 RCAR_GP_PIN(0, 1),
2985};
2986static const unsigned int msiof3_sync_a_mux[] = {
2987 MSIOF3_SYNC_A_MARK,
2988};
2989static const unsigned int msiof3_ss1_a_pins[] = {
2990 /* SS1 */
2991 RCAR_GP_PIN(0, 14),
2992};
2993static const unsigned int msiof3_ss1_a_mux[] = {
2994 MSIOF3_SS1_A_MARK,
2995};
2996static const unsigned int msiof3_ss2_a_pins[] = {
2997 /* SS2 */
2998 RCAR_GP_PIN(0, 15),
2999};
3000static const unsigned int msiof3_ss2_a_mux[] = {
3001 MSIOF3_SS2_A_MARK,
3002};
3003static const unsigned int msiof3_txd_a_pins[] = {
3004 /* TXD */
3005 RCAR_GP_PIN(0, 3),
3006};
3007static const unsigned int msiof3_txd_a_mux[] = {
3008 MSIOF3_TXD_A_MARK,
3009};
3010static const unsigned int msiof3_rxd_a_pins[] = {
3011 /* RXD */
3012 RCAR_GP_PIN(0, 2),
3013};
3014static const unsigned int msiof3_rxd_a_mux[] = {
3015 MSIOF3_RXD_A_MARK,
3016};
3017static const unsigned int msiof3_clk_b_pins[] = {
3018 /* SCK */
3019 RCAR_GP_PIN(1, 2),
3020};
3021static const unsigned int msiof3_clk_b_mux[] = {
3022 MSIOF3_SCK_B_MARK,
3023};
3024static const unsigned int msiof3_sync_b_pins[] = {
3025 /* SYNC */
3026 RCAR_GP_PIN(1, 0),
3027};
3028static const unsigned int msiof3_sync_b_mux[] = {
3029 MSIOF3_SYNC_B_MARK,
3030};
3031static const unsigned int msiof3_ss1_b_pins[] = {
3032 /* SS1 */
3033 RCAR_GP_PIN(1, 4),
3034};
3035static const unsigned int msiof3_ss1_b_mux[] = {
3036 MSIOF3_SS1_B_MARK,
3037};
3038static const unsigned int msiof3_ss2_b_pins[] = {
3039 /* SS2 */
3040 RCAR_GP_PIN(1, 5),
3041};
3042static const unsigned int msiof3_ss2_b_mux[] = {
3043 MSIOF3_SS2_B_MARK,
3044};
3045static const unsigned int msiof3_txd_b_pins[] = {
3046 /* TXD */
3047 RCAR_GP_PIN(1, 1),
3048};
3049static const unsigned int msiof3_txd_b_mux[] = {
3050 MSIOF3_TXD_B_MARK,
3051};
3052static const unsigned int msiof3_rxd_b_pins[] = {
3053 /* RXD */
3054 RCAR_GP_PIN(1, 3),
3055};
3056static const unsigned int msiof3_rxd_b_mux[] = {
3057 MSIOF3_RXD_B_MARK,
3058};
3059static const unsigned int msiof3_clk_c_pins[] = {
3060 /* SCK */
3061 RCAR_GP_PIN(1, 12),
3062};
3063static const unsigned int msiof3_clk_c_mux[] = {
3064 MSIOF3_SCK_C_MARK,
3065};
3066static const unsigned int msiof3_sync_c_pins[] = {
3067 /* SYNC */
3068 RCAR_GP_PIN(1, 13),
3069};
3070static const unsigned int msiof3_sync_c_mux[] = {
3071 MSIOF3_SYNC_C_MARK,
3072};
3073static const unsigned int msiof3_txd_c_pins[] = {
3074 /* TXD */
3075 RCAR_GP_PIN(1, 15),
3076};
3077static const unsigned int msiof3_txd_c_mux[] = {
3078 MSIOF3_TXD_C_MARK,
3079};
3080static const unsigned int msiof3_rxd_c_pins[] = {
3081 /* RXD */
3082 RCAR_GP_PIN(1, 14),
3083};
3084static const unsigned int msiof3_rxd_c_mux[] = {
3085 MSIOF3_RXD_C_MARK,
3086};
3087static const unsigned int msiof3_clk_d_pins[] = {
3088 /* SCK */
3089 RCAR_GP_PIN(1, 22),
3090};
3091static const unsigned int msiof3_clk_d_mux[] = {
3092 MSIOF3_SCK_D_MARK,
3093};
3094static const unsigned int msiof3_sync_d_pins[] = {
3095 /* SYNC */
3096 RCAR_GP_PIN(1, 23),
3097};
3098static const unsigned int msiof3_sync_d_mux[] = {
3099 MSIOF3_SYNC_D_MARK,
3100};
3101static const unsigned int msiof3_ss1_d_pins[] = {
3102 /* SS1 */
3103 RCAR_GP_PIN(1, 26),
3104};
3105static const unsigned int msiof3_ss1_d_mux[] = {
3106 MSIOF3_SS1_D_MARK,
3107};
3108static const unsigned int msiof3_txd_d_pins[] = {
3109 /* TXD */
3110 RCAR_GP_PIN(1, 25),
3111};
3112static const unsigned int msiof3_txd_d_mux[] = {
3113 MSIOF3_TXD_D_MARK,
3114};
3115static const unsigned int msiof3_rxd_d_pins[] = {
3116 /* RXD */
3117 RCAR_GP_PIN(1, 24),
3118};
3119static const unsigned int msiof3_rxd_d_mux[] = {
3120 MSIOF3_RXD_D_MARK,
3121};
3122static const unsigned int msiof3_clk_e_pins[] = {
3123 /* SCK */
3124 RCAR_GP_PIN(2, 3),
3125};
3126static const unsigned int msiof3_clk_e_mux[] = {
3127 MSIOF3_SCK_E_MARK,
3128};
3129static const unsigned int msiof3_sync_e_pins[] = {
3130 /* SYNC */
3131 RCAR_GP_PIN(2, 2),
3132};
3133static const unsigned int msiof3_sync_e_mux[] = {
3134 MSIOF3_SYNC_E_MARK,
3135};
3136static const unsigned int msiof3_ss1_e_pins[] = {
3137 /* SS1 */
3138 RCAR_GP_PIN(2, 1),
3139};
3140static const unsigned int msiof3_ss1_e_mux[] = {
3141 MSIOF3_SS1_E_MARK,
3142};
3143static const unsigned int msiof3_ss2_e_pins[] = {
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]3144 /* SS2 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3145 RCAR_GP_PIN(2, 0),
3146};
3147static const unsigned int msiof3_ss2_e_mux[] = {
3148 MSIOF3_SS2_E_MARK,
3149};
3150static const unsigned int msiof3_txd_e_pins[] = {
3151 /* TXD */
3152 RCAR_GP_PIN(2, 5),
3153};
3154static const unsigned int msiof3_txd_e_mux[] = {
3155 MSIOF3_TXD_E_MARK,
3156};
3157static const unsigned int msiof3_rxd_e_pins[] = {
3158 /* RXD */
3159 RCAR_GP_PIN(2, 4),
3160};
3161static const unsigned int msiof3_rxd_e_mux[] = {
3162 MSIOF3_RXD_E_MARK,
3163};
3164
3165/* - PWM0 --------------------------------------------------------------------*/
3166static const unsigned int pwm0_pins[] = {
3167 /* PWM */
3168 RCAR_GP_PIN(2, 6),
3169};
3170static const unsigned int pwm0_mux[] = {
3171 PWM0_MARK,
3172};
3173/* - PWM1 --------------------------------------------------------------------*/
3174static const unsigned int pwm1_a_pins[] = {
3175 /* PWM */
3176 RCAR_GP_PIN(2, 7),
3177};
3178static const unsigned int pwm1_a_mux[] = {
3179 PWM1_A_MARK,
3180};
3181static const unsigned int pwm1_b_pins[] = {
3182 /* PWM */
3183 RCAR_GP_PIN(1, 8),
3184};
3185static const unsigned int pwm1_b_mux[] = {
3186 PWM1_B_MARK,
3187};
3188/* - PWM2 --------------------------------------------------------------------*/
3189static const unsigned int pwm2_a_pins[] = {
3190 /* PWM */
3191 RCAR_GP_PIN(2, 8),
3192};
3193static const unsigned int pwm2_a_mux[] = {
3194 PWM2_A_MARK,
3195};
3196static const unsigned int pwm2_b_pins[] = {
3197 /* PWM */
3198 RCAR_GP_PIN(1, 11),
3199};
3200static const unsigned int pwm2_b_mux[] = {
3201 PWM2_B_MARK,
3202};
3203/* - PWM3 --------------------------------------------------------------------*/
3204static const unsigned int pwm3_a_pins[] = {
3205 /* PWM */
3206 RCAR_GP_PIN(1, 0),
3207};
3208static const unsigned int pwm3_a_mux[] = {
3209 PWM3_A_MARK,
3210};
3211static const unsigned int pwm3_b_pins[] = {
3212 /* PWM */
3213 RCAR_GP_PIN(2, 2),
3214};
3215static const unsigned int pwm3_b_mux[] = {
3216 PWM3_B_MARK,
3217};
3218/* - PWM4 --------------------------------------------------------------------*/
3219static const unsigned int pwm4_a_pins[] = {
3220 /* PWM */
3221 RCAR_GP_PIN(1, 1),
3222};
3223static const unsigned int pwm4_a_mux[] = {
3224 PWM4_A_MARK,
3225};
3226static const unsigned int pwm4_b_pins[] = {
3227 /* PWM */
3228 RCAR_GP_PIN(2, 3),
3229};
3230static const unsigned int pwm4_b_mux[] = {
3231 PWM4_B_MARK,
3232};
3233/* - PWM5 --------------------------------------------------------------------*/
3234static const unsigned int pwm5_a_pins[] = {
3235 /* PWM */
3236 RCAR_GP_PIN(1, 2),
3237};
3238static const unsigned int pwm5_a_mux[] = {
3239 PWM5_A_MARK,
3240};
3241static const unsigned int pwm5_b_pins[] = {
3242 /* PWM */
3243 RCAR_GP_PIN(2, 4),
3244};
3245static const unsigned int pwm5_b_mux[] = {
3246 PWM5_B_MARK,
3247};
3248/* - PWM6 --------------------------------------------------------------------*/
3249static const unsigned int pwm6_a_pins[] = {
3250 /* PWM */
3251 RCAR_GP_PIN(1, 3),
3252};
3253static const unsigned int pwm6_a_mux[] = {
3254 PWM6_A_MARK,
3255};
3256static const unsigned int pwm6_b_pins[] = {
3257 /* PWM */
3258 RCAR_GP_PIN(2, 5),
3259};
3260static const unsigned int pwm6_b_mux[] = {
3261 PWM6_B_MARK,
3262};
3263
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3264/* - QSPI0 ------------------------------------------------------------------ */
3265static const unsigned int qspi0_ctrl_pins[] = {
3266 /* QSPI0_SPCLK, QSPI0_SSL */
3267 PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,
3268};
3269static const unsigned int qspi0_ctrl_mux[] = {
3270 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
3271};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]3272static const unsigned int qspi0_data_pins[] = {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3273 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
3274 PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3275 /* QSPI0_IO2, QSPI0_IO3 */
3276 PIN_QSPI0_IO2, PIN_QSPI0_IO3,
3277};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]3278static const unsigned int qspi0_data_mux[] = {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3279 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3280 QSPI0_IO2_MARK, QSPI0_IO3_MARK,
3281};
3282/* - QSPI1 ------------------------------------------------------------------ */
3283static const unsigned int qspi1_ctrl_pins[] = {
3284 /* QSPI1_SPCLK, QSPI1_SSL */
3285 PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,
3286};
3287static const unsigned int qspi1_ctrl_mux[] = {
3288 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
3289};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]3290static const unsigned int qspi1_data_pins[] = {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3291 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
3292 PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
3293 /* QSPI1_IO2, QSPI1_IO3 */
3294 PIN_QSPI1_IO2, PIN_QSPI1_IO3,
3295};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]3296static const unsigned int qspi1_data_mux[] = {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3297 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3298 QSPI1_IO2_MARK, QSPI1_IO3_MARK,
3299};
3300
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3301/* - SATA --------------------------------------------------------------------*/
3302static const unsigned int sata0_devslp_a_pins[] = {
3303 /* DEVSLP */
3304 RCAR_GP_PIN(6, 16),
3305};
3306static const unsigned int sata0_devslp_a_mux[] = {
3307 SATA_DEVSLP_A_MARK,
3308};
3309static const unsigned int sata0_devslp_b_pins[] = {
3310 /* DEVSLP */
3311 RCAR_GP_PIN(4, 6),
3312};
3313static const unsigned int sata0_devslp_b_mux[] = {
3314 SATA_DEVSLP_B_MARK,
3315};
3316
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3317/* - SCIF0 ------------------------------------------------------------------ */
3318static const unsigned int scif0_data_pins[] = {
3319 /* RX, TX */
3320 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3321};
3322static const unsigned int scif0_data_mux[] = {
3323 RX0_MARK, TX0_MARK,
3324};
3325static const unsigned int scif0_clk_pins[] = {
3326 /* SCK */
3327 RCAR_GP_PIN(5, 0),
3328};
3329static const unsigned int scif0_clk_mux[] = {
3330 SCK0_MARK,
3331};
3332static const unsigned int scif0_ctrl_pins[] = {
3333 /* RTS, CTS */
3334 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3335};
3336static const unsigned int scif0_ctrl_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3337 RTS0_N_MARK, CTS0_N_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3338};
3339/* - SCIF1 ------------------------------------------------------------------ */
3340static const unsigned int scif1_data_a_pins[] = {
3341 /* RX, TX */
3342 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3343};
3344static const unsigned int scif1_data_a_mux[] = {
3345 RX1_A_MARK, TX1_A_MARK,
3346};
3347static const unsigned int scif1_clk_pins[] = {
3348 /* SCK */
3349 RCAR_GP_PIN(6, 21),
3350};
3351static const unsigned int scif1_clk_mux[] = {
3352 SCK1_MARK,
3353};
3354static const unsigned int scif1_ctrl_pins[] = {
3355 /* RTS, CTS */
3356 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3357};
3358static const unsigned int scif1_ctrl_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3359 RTS1_N_MARK, CTS1_N_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3360};
3361
3362static const unsigned int scif1_data_b_pins[] = {
3363 /* RX, TX */
3364 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3365};
3366static const unsigned int scif1_data_b_mux[] = {
3367 RX1_B_MARK, TX1_B_MARK,
3368};
3369/* - SCIF2 ------------------------------------------------------------------ */
3370static const unsigned int scif2_data_a_pins[] = {
3371 /* RX, TX */
3372 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3373};
3374static const unsigned int scif2_data_a_mux[] = {
3375 RX2_A_MARK, TX2_A_MARK,
3376};
3377static const unsigned int scif2_clk_pins[] = {
3378 /* SCK */
3379 RCAR_GP_PIN(5, 9),
3380};
3381static const unsigned int scif2_clk_mux[] = {
3382 SCK2_MARK,
3383};
3384static const unsigned int scif2_data_b_pins[] = {
3385 /* RX, TX */
3386 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3387};
3388static const unsigned int scif2_data_b_mux[] = {
3389 RX2_B_MARK, TX2_B_MARK,
3390};
3391/* - SCIF3 ------------------------------------------------------------------ */
3392static const unsigned int scif3_data_a_pins[] = {
3393 /* RX, TX */
3394 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3395};
3396static const unsigned int scif3_data_a_mux[] = {
3397 RX3_A_MARK, TX3_A_MARK,
3398};
3399static const unsigned int scif3_clk_pins[] = {
3400 /* SCK */
3401 RCAR_GP_PIN(1, 22),
3402};
3403static const unsigned int scif3_clk_mux[] = {
3404 SCK3_MARK,
3405};
3406static const unsigned int scif3_ctrl_pins[] = {
3407 /* RTS, CTS */
3408 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3409};
3410static const unsigned int scif3_ctrl_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3411 RTS3_N_MARK, CTS3_N_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3412};
3413static const unsigned int scif3_data_b_pins[] = {
3414 /* RX, TX */
3415 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3416};
3417static const unsigned int scif3_data_b_mux[] = {
3418 RX3_B_MARK, TX3_B_MARK,
3419};
3420/* - SCIF4 ------------------------------------------------------------------ */
3421static const unsigned int scif4_data_a_pins[] = {
3422 /* RX, TX */
3423 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3424};
3425static const unsigned int scif4_data_a_mux[] = {
3426 RX4_A_MARK, TX4_A_MARK,
3427};
3428static const unsigned int scif4_clk_a_pins[] = {
3429 /* SCK */
3430 RCAR_GP_PIN(2, 10),
3431};
3432static const unsigned int scif4_clk_a_mux[] = {
3433 SCK4_A_MARK,
3434};
3435static const unsigned int scif4_ctrl_a_pins[] = {
3436 /* RTS, CTS */
3437 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3438};
3439static const unsigned int scif4_ctrl_a_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3440 RTS4_N_A_MARK, CTS4_N_A_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3441};
3442static const unsigned int scif4_data_b_pins[] = {
3443 /* RX, TX */
3444 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3445};
3446static const unsigned int scif4_data_b_mux[] = {
3447 RX4_B_MARK, TX4_B_MARK,
3448};
3449static const unsigned int scif4_clk_b_pins[] = {
3450 /* SCK */
3451 RCAR_GP_PIN(1, 5),
3452};
3453static const unsigned int scif4_clk_b_mux[] = {
3454 SCK4_B_MARK,
3455};
3456static const unsigned int scif4_ctrl_b_pins[] = {
3457 /* RTS, CTS */
3458 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3459};
3460static const unsigned int scif4_ctrl_b_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3461 RTS4_N_B_MARK, CTS4_N_B_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3462};
3463static const unsigned int scif4_data_c_pins[] = {
3464 /* RX, TX */
3465 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3466};
3467static const unsigned int scif4_data_c_mux[] = {
3468 RX4_C_MARK, TX4_C_MARK,
3469};
3470static const unsigned int scif4_clk_c_pins[] = {
3471 /* SCK */
3472 RCAR_GP_PIN(0, 8),
3473};
3474static const unsigned int scif4_clk_c_mux[] = {
3475 SCK4_C_MARK,
3476};
3477static const unsigned int scif4_ctrl_c_pins[] = {
3478 /* RTS, CTS */
3479 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3480};
3481static const unsigned int scif4_ctrl_c_mux[] = {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3482 RTS4_N_C_MARK, CTS4_N_C_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3483};
3484/* - SCIF5 ------------------------------------------------------------------ */
3485static const unsigned int scif5_data_a_pins[] = {
3486 /* RX, TX */
3487 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3488};
3489static const unsigned int scif5_data_a_mux[] = {
3490 RX5_A_MARK, TX5_A_MARK,
3491};
3492static const unsigned int scif5_clk_a_pins[] = {
3493 /* SCK */
3494 RCAR_GP_PIN(6, 21),
3495};
3496static const unsigned int scif5_clk_a_mux[] = {
3497 SCK5_A_MARK,
3498};
3499static const unsigned int scif5_data_b_pins[] = {
3500 /* RX, TX */
3501 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3502};
3503static const unsigned int scif5_data_b_mux[] = {
3504 RX5_B_MARK, TX5_B_MARK,
3505};
3506static const unsigned int scif5_clk_b_pins[] = {
3507 /* SCK */
3508 RCAR_GP_PIN(5, 0),
3509};
3510static const unsigned int scif5_clk_b_mux[] = {
3511 SCK5_B_MARK,
3512};
3513
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3514/* - SCIF Clock ------------------------------------------------------------- */
3515static const unsigned int scif_clk_a_pins[] = {
3516 /* SCIF_CLK */
3517 RCAR_GP_PIN(6, 23),
3518};
3519static const unsigned int scif_clk_a_mux[] = {
3520 SCIF_CLK_A_MARK,
3521};
3522static const unsigned int scif_clk_b_pins[] = {
3523 /* SCIF_CLK */
3524 RCAR_GP_PIN(5, 9),
3525};
3526static const unsigned int scif_clk_b_mux[] = {
3527 SCIF_CLK_B_MARK,
3528};
3529
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3530/* - SDHI0 ------------------------------------------------------------------ */
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]3531static const unsigned int sdhi0_data_pins[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3532 /* D[0:3] */
3533 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3534 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3535};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]3536static const unsigned int sdhi0_data_mux[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3537 SD0_DAT0_MARK, SD0_DAT1_MARK,
3538 SD0_DAT2_MARK, SD0_DAT3_MARK,
3539};
3540static const unsigned int sdhi0_ctrl_pins[] = {
3541 /* CLK, CMD */
3542 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3543};
3544static const unsigned int sdhi0_ctrl_mux[] = {
3545 SD0_CLK_MARK, SD0_CMD_MARK,
3546};
3547static const unsigned int sdhi0_cd_pins[] = {
3548 /* CD */
3549 RCAR_GP_PIN(3, 12),
3550};
3551static const unsigned int sdhi0_cd_mux[] = {
3552 SD0_CD_MARK,
3553};
3554static const unsigned int sdhi0_wp_pins[] = {
3555 /* WP */
3556 RCAR_GP_PIN(3, 13),
3557};
3558static const unsigned int sdhi0_wp_mux[] = {
3559 SD0_WP_MARK,
3560};
3561/* - SDHI1 ------------------------------------------------------------------ */
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]3562static const unsigned int sdhi1_data_pins[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3563 /* D[0:3] */
3564 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3565 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3566};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]3567static const unsigned int sdhi1_data_mux[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3568 SD1_DAT0_MARK, SD1_DAT1_MARK,
3569 SD1_DAT2_MARK, SD1_DAT3_MARK,
3570};
3571static const unsigned int sdhi1_ctrl_pins[] = {
3572 /* CLK, CMD */
3573 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3574};
3575static const unsigned int sdhi1_ctrl_mux[] = {
3576 SD1_CLK_MARK, SD1_CMD_MARK,
3577};
3578static const unsigned int sdhi1_cd_pins[] = {
3579 /* CD */
3580 RCAR_GP_PIN(3, 14),
3581};
3582static const unsigned int sdhi1_cd_mux[] = {
3583 SD1_CD_MARK,
3584};
3585static const unsigned int sdhi1_wp_pins[] = {
3586 /* WP */
3587 RCAR_GP_PIN(3, 15),
3588};
3589static const unsigned int sdhi1_wp_mux[] = {
3590 SD1_WP_MARK,
3591};
3592/* - SDHI2 ------------------------------------------------------------------ */
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]3593static const unsigned int sdhi2_data_pins[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3594 /* D[0:7] */
3595 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3596 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3597 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3598 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3599};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]3600static const unsigned int sdhi2_data_mux[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3601 SD2_DAT0_MARK, SD2_DAT1_MARK,
3602 SD2_DAT2_MARK, SD2_DAT3_MARK,
3603 SD2_DAT4_MARK, SD2_DAT5_MARK,
3604 SD2_DAT6_MARK, SD2_DAT7_MARK,
3605};
3606static const unsigned int sdhi2_ctrl_pins[] = {
3607 /* CLK, CMD */
3608 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3609};
3610static const unsigned int sdhi2_ctrl_mux[] = {
3611 SD2_CLK_MARK, SD2_CMD_MARK,
3612};
3613static const unsigned int sdhi2_cd_a_pins[] = {
3614 /* CD */
3615 RCAR_GP_PIN(4, 13),
3616};
3617static const unsigned int sdhi2_cd_a_mux[] = {
3618 SD2_CD_A_MARK,
3619};
3620static const unsigned int sdhi2_cd_b_pins[] = {
3621 /* CD */
3622 RCAR_GP_PIN(5, 10),
3623};
3624static const unsigned int sdhi2_cd_b_mux[] = {
3625 SD2_CD_B_MARK,
3626};
3627static const unsigned int sdhi2_wp_a_pins[] = {
3628 /* WP */
3629 RCAR_GP_PIN(4, 14),
3630};
3631static const unsigned int sdhi2_wp_a_mux[] = {
3632 SD2_WP_A_MARK,
3633};
3634static const unsigned int sdhi2_wp_b_pins[] = {
3635 /* WP */
3636 RCAR_GP_PIN(5, 11),
3637};
3638static const unsigned int sdhi2_wp_b_mux[] = {
3639 SD2_WP_B_MARK,
3640};
3641static const unsigned int sdhi2_ds_pins[] = {
3642 /* DS */
3643 RCAR_GP_PIN(4, 6),
3644};
3645static const unsigned int sdhi2_ds_mux[] = {
3646 SD2_DS_MARK,
3647};
3648/* - SDHI3 ------------------------------------------------------------------ */
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]3649static const unsigned int sdhi3_data_pins[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3650 /* D[0:7] */
3651 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3652 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3653 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3654 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3655};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]3656static const unsigned int sdhi3_data_mux[] = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3657 SD3_DAT0_MARK, SD3_DAT1_MARK,
3658 SD3_DAT2_MARK, SD3_DAT3_MARK,
3659 SD3_DAT4_MARK, SD3_DAT5_MARK,
3660 SD3_DAT6_MARK, SD3_DAT7_MARK,
3661};
3662static const unsigned int sdhi3_ctrl_pins[] = {
3663 /* CLK, CMD */
3664 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3665};
3666static const unsigned int sdhi3_ctrl_mux[] = {
3667 SD3_CLK_MARK, SD3_CMD_MARK,
3668};
3669static const unsigned int sdhi3_cd_pins[] = {
3670 /* CD */
3671 RCAR_GP_PIN(4, 15),
3672};
3673static const unsigned int sdhi3_cd_mux[] = {
3674 SD3_CD_MARK,
3675};
3676static const unsigned int sdhi3_wp_pins[] = {
3677 /* WP */
3678 RCAR_GP_PIN(4, 16),
3679};
3680static const unsigned int sdhi3_wp_mux[] = {
3681 SD3_WP_MARK,
3682};
3683static const unsigned int sdhi3_ds_pins[] = {
3684 /* DS */
3685 RCAR_GP_PIN(4, 17),
3686};
3687static const unsigned int sdhi3_ds_mux[] = {
3688 SD3_DS_MARK,
3689};
3690
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3691/* - SSI -------------------------------------------------------------------- */
3692static const unsigned int ssi0_data_pins[] = {
3693 /* SDATA */
3694 RCAR_GP_PIN(6, 2),
3695};
3696static const unsigned int ssi0_data_mux[] = {
3697 SSI_SDATA0_MARK,
3698};
3699static const unsigned int ssi01239_ctrl_pins[] = {
3700 /* SCK, WS */
3701 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3702};
3703static const unsigned int ssi01239_ctrl_mux[] = {
3704 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3705};
3706static const unsigned int ssi1_data_a_pins[] = {
3707 /* SDATA */
3708 RCAR_GP_PIN(6, 3),
3709};
3710static const unsigned int ssi1_data_a_mux[] = {
3711 SSI_SDATA1_A_MARK,
3712};
3713static const unsigned int ssi1_data_b_pins[] = {
3714 /* SDATA */
3715 RCAR_GP_PIN(5, 12),
3716};
3717static const unsigned int ssi1_data_b_mux[] = {
3718 SSI_SDATA1_B_MARK,
3719};
3720static const unsigned int ssi1_ctrl_a_pins[] = {
3721 /* SCK, WS */
3722 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3723};
3724static const unsigned int ssi1_ctrl_a_mux[] = {
3725 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3726};
3727static const unsigned int ssi1_ctrl_b_pins[] = {
3728 /* SCK, WS */
3729 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3730};
3731static const unsigned int ssi1_ctrl_b_mux[] = {
3732 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3733};
3734static const unsigned int ssi2_data_a_pins[] = {
3735 /* SDATA */
3736 RCAR_GP_PIN(6, 4),
3737};
3738static const unsigned int ssi2_data_a_mux[] = {
3739 SSI_SDATA2_A_MARK,
3740};
3741static const unsigned int ssi2_data_b_pins[] = {
3742 /* SDATA */
3743 RCAR_GP_PIN(5, 13),
3744};
3745static const unsigned int ssi2_data_b_mux[] = {
3746 SSI_SDATA2_B_MARK,
3747};
3748static const unsigned int ssi2_ctrl_a_pins[] = {
3749 /* SCK, WS */
3750 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3751};
3752static const unsigned int ssi2_ctrl_a_mux[] = {
3753 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3754};
3755static const unsigned int ssi2_ctrl_b_pins[] = {
3756 /* SCK, WS */
3757 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3758};
3759static const unsigned int ssi2_ctrl_b_mux[] = {
3760 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3761};
3762static const unsigned int ssi3_data_pins[] = {
3763 /* SDATA */
3764 RCAR_GP_PIN(6, 7),
3765};
3766static const unsigned int ssi3_data_mux[] = {
3767 SSI_SDATA3_MARK,
3768};
3769static const unsigned int ssi349_ctrl_pins[] = {
3770 /* SCK, WS */
3771 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3772};
3773static const unsigned int ssi349_ctrl_mux[] = {
3774 SSI_SCK349_MARK, SSI_WS349_MARK,
3775};
3776static const unsigned int ssi4_data_pins[] = {
3777 /* SDATA */
3778 RCAR_GP_PIN(6, 10),
3779};
3780static const unsigned int ssi4_data_mux[] = {
3781 SSI_SDATA4_MARK,
3782};
3783static const unsigned int ssi4_ctrl_pins[] = {
3784 /* SCK, WS */
3785 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3786};
3787static const unsigned int ssi4_ctrl_mux[] = {
3788 SSI_SCK4_MARK, SSI_WS4_MARK,
3789};
3790static const unsigned int ssi5_data_pins[] = {
3791 /* SDATA */
3792 RCAR_GP_PIN(6, 13),
3793};
3794static const unsigned int ssi5_data_mux[] = {
3795 SSI_SDATA5_MARK,
3796};
3797static const unsigned int ssi5_ctrl_pins[] = {
3798 /* SCK, WS */
3799 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3800};
3801static const unsigned int ssi5_ctrl_mux[] = {
3802 SSI_SCK5_MARK, SSI_WS5_MARK,
3803};
3804static const unsigned int ssi6_data_pins[] = {
3805 /* SDATA */
3806 RCAR_GP_PIN(6, 16),
3807};
3808static const unsigned int ssi6_data_mux[] = {
3809 SSI_SDATA6_MARK,
3810};
3811static const unsigned int ssi6_ctrl_pins[] = {
3812 /* SCK, WS */
3813 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3814};
3815static const unsigned int ssi6_ctrl_mux[] = {
3816 SSI_SCK6_MARK, SSI_WS6_MARK,
3817};
3818static const unsigned int ssi7_data_pins[] = {
3819 /* SDATA */
3820 RCAR_GP_PIN(6, 19),
3821};
3822static const unsigned int ssi7_data_mux[] = {
3823 SSI_SDATA7_MARK,
3824};
3825static const unsigned int ssi78_ctrl_pins[] = {
3826 /* SCK, WS */
3827 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3828};
3829static const unsigned int ssi78_ctrl_mux[] = {
3830 SSI_SCK78_MARK, SSI_WS78_MARK,
3831};
3832static const unsigned int ssi8_data_pins[] = {
3833 /* SDATA */
3834 RCAR_GP_PIN(6, 20),
3835};
3836static const unsigned int ssi8_data_mux[] = {
3837 SSI_SDATA8_MARK,
3838};
3839static const unsigned int ssi9_data_a_pins[] = {
3840 /* SDATA */
3841 RCAR_GP_PIN(6, 21),
3842};
3843static const unsigned int ssi9_data_a_mux[] = {
3844 SSI_SDATA9_A_MARK,
3845};
3846static const unsigned int ssi9_data_b_pins[] = {
3847 /* SDATA */
3848 RCAR_GP_PIN(5, 14),
3849};
3850static const unsigned int ssi9_data_b_mux[] = {
3851 SSI_SDATA9_B_MARK,
3852};
3853static const unsigned int ssi9_ctrl_a_pins[] = {
3854 /* SCK, WS */
3855 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3856};
3857static const unsigned int ssi9_ctrl_a_mux[] = {
3858 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3859};
3860static const unsigned int ssi9_ctrl_b_pins[] = {
3861 /* SCK, WS */
3862 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3863};
3864static const unsigned int ssi9_ctrl_b_mux[] = {
3865 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3866};
3867
3868/* - TMU -------------------------------------------------------------------- */
3869static const unsigned int tmu_tclk1_a_pins[] = {
3870 /* TCLK */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3871 RCAR_GP_PIN(6, 23),
3872};
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3873static const unsigned int tmu_tclk1_a_mux[] = {
3874 TCLK1_A_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3875};
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3876static const unsigned int tmu_tclk1_b_pins[] = {
3877 /* TCLK */
3878 RCAR_GP_PIN(5, 19),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3879};
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3880static const unsigned int tmu_tclk1_b_mux[] = {
3881 TCLK1_B_MARK,
3882};
3883static const unsigned int tmu_tclk2_a_pins[] = {
3884 /* TCLK */
3885 RCAR_GP_PIN(6, 19),
3886};
3887static const unsigned int tmu_tclk2_a_mux[] = {
3888 TCLK2_A_MARK,
3889};
3890static const unsigned int tmu_tclk2_b_pins[] = {
3891 /* TCLK */
3892 RCAR_GP_PIN(6, 28),
3893};
3894static const unsigned int tmu_tclk2_b_mux[] = {
3895 TCLK2_B_MARK,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3896};
3897
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]3898/* - TPU ------------------------------------------------------------------- */
3899static const unsigned int tpu_to0_pins[] = {
3900 /* TPU0TO0 */
3901 RCAR_GP_PIN(6, 28),
3902};
3903static const unsigned int tpu_to0_mux[] = {
3904 TPU0TO0_MARK,
3905};
3906static const unsigned int tpu_to1_pins[] = {
3907 /* TPU0TO1 */
3908 RCAR_GP_PIN(6, 29),
3909};
3910static const unsigned int tpu_to1_mux[] = {
3911 TPU0TO1_MARK,
3912};
3913static const unsigned int tpu_to2_pins[] = {
3914 /* TPU0TO2 */
3915 RCAR_GP_PIN(6, 30),
3916};
3917static const unsigned int tpu_to2_mux[] = {
3918 TPU0TO2_MARK,
3919};
3920static const unsigned int tpu_to3_pins[] = {
3921 /* TPU0TO3 */
3922 RCAR_GP_PIN(6, 31),
3923};
3924static const unsigned int tpu_to3_mux[] = {
3925 TPU0TO3_MARK,
3926};
3927
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]3928/* - USB0 ------------------------------------------------------------------- */
3929static const unsigned int usb0_pins[] = {
3930 /* PWEN, OVC */
3931 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3932};
3933static const unsigned int usb0_mux[] = {
3934 USB0_PWEN_MARK, USB0_OVC_MARK,
3935};
3936/* - USB1 ------------------------------------------------------------------- */
3937static const unsigned int usb1_pins[] = {
3938 /* PWEN, OVC */
3939 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3940};
3941static const unsigned int usb1_mux[] = {
3942 USB1_PWEN_MARK, USB1_OVC_MARK,
3943};
3944/* - USB2 ------------------------------------------------------------------- */
3945static const unsigned int usb2_pins[] = {
3946 /* PWEN, OVC */
3947 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3948};
3949static const unsigned int usb2_mux[] = {
3950 USB2_PWEN_MARK, USB2_OVC_MARK,
3951};
3952/* - USB2_CH3 --------------------------------------------------------------- */
3953static const unsigned int usb2_ch3_pins[] = {
3954 /* PWEN, OVC */
3955 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3956};
3957static const unsigned int usb2_ch3_mux[] = {
3958 USB2_CH3_PWEN_MARK, USB2_CH3_OVC_MARK,
3959};
3960
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]3961/* - USB30 ------------------------------------------------------------------ */
3962static const unsigned int usb30_pins[] = {
3963 /* PWEN, OVC */
3964 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3965};
3966static const unsigned int usb30_mux[] = {
3967 USB30_PWEN_MARK, USB30_OVC_MARK,
3968};
3969
3970/* - VIN4 ------------------------------------------------------------------- */
3971static const unsigned int vin4_data18_a_pins[] = {
3972 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3973 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3974 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3975 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3976 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3977 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3978 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3979 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3980 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3981};
3982static const unsigned int vin4_data18_a_mux[] = {
3983 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3984 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3985 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3986 VI4_DATA10_MARK, VI4_DATA11_MARK,
3987 VI4_DATA12_MARK, VI4_DATA13_MARK,
3988 VI4_DATA14_MARK, VI4_DATA15_MARK,
3989 VI4_DATA18_MARK, VI4_DATA19_MARK,
3990 VI4_DATA20_MARK, VI4_DATA21_MARK,
3991 VI4_DATA22_MARK, VI4_DATA23_MARK,
3992};
3993static const unsigned int vin4_data18_b_pins[] = {
3994 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
3995 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
3996 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3997 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3998 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3999 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4000 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4001 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4002 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4003};
4004static const unsigned int vin4_data18_b_mux[] = {
4005 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4006 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4007 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4008 VI4_DATA10_MARK, VI4_DATA11_MARK,
4009 VI4_DATA12_MARK, VI4_DATA13_MARK,
4010 VI4_DATA14_MARK, VI4_DATA15_MARK,
4011 VI4_DATA18_MARK, VI4_DATA19_MARK,
4012 VI4_DATA20_MARK, VI4_DATA21_MARK,
4013 VI4_DATA22_MARK, VI4_DATA23_MARK,
4014};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4015static const unsigned int vin4_data_a_pins[] = {
4016 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
4017 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
4018 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
4019 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
4020 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4021 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4022 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4023 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4024 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4025 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4026 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4027 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4028};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4029static const unsigned int vin4_data_a_mux[] = {
4030 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
4031 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4032 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4033 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4034 VI4_DATA8_MARK, VI4_DATA9_MARK,
4035 VI4_DATA10_MARK, VI4_DATA11_MARK,
4036 VI4_DATA12_MARK, VI4_DATA13_MARK,
4037 VI4_DATA14_MARK, VI4_DATA15_MARK,
4038 VI4_DATA16_MARK, VI4_DATA17_MARK,
4039 VI4_DATA18_MARK, VI4_DATA19_MARK,
4040 VI4_DATA20_MARK, VI4_DATA21_MARK,
4041 VI4_DATA22_MARK, VI4_DATA23_MARK,
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4042};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4043static const unsigned int vin4_data_b_pins[] = {
4044 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4045 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4046 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4047 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4048 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4049 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4050 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4051 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4052 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4053 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4054 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4055 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4056};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4057static const unsigned int vin4_data_b_mux[] = {
4058 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
4059 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4060 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4061 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4062 VI4_DATA8_MARK, VI4_DATA9_MARK,
4063 VI4_DATA10_MARK, VI4_DATA11_MARK,
4064 VI4_DATA12_MARK, VI4_DATA13_MARK,
4065 VI4_DATA14_MARK, VI4_DATA15_MARK,
4066 VI4_DATA16_MARK, VI4_DATA17_MARK,
4067 VI4_DATA18_MARK, VI4_DATA19_MARK,
4068 VI4_DATA20_MARK, VI4_DATA21_MARK,
4069 VI4_DATA22_MARK, VI4_DATA23_MARK,
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4070};
4071static const unsigned int vin4_sync_pins[] = {
4072 /* HSYNC#, VSYNC# */
4073 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
4074};
4075static const unsigned int vin4_sync_mux[] = {
4076 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
4077};
4078static const unsigned int vin4_field_pins[] = {
4079 /* FIELD */
4080 RCAR_GP_PIN(1, 16),
4081};
4082static const unsigned int vin4_field_mux[] = {
4083 VI4_FIELD_MARK,
4084};
4085static const unsigned int vin4_clkenb_pins[] = {
4086 /* CLKENB */
4087 RCAR_GP_PIN(1, 19),
4088};
4089static const unsigned int vin4_clkenb_mux[] = {
4090 VI4_CLKENB_MARK,
4091};
4092static const unsigned int vin4_clk_pins[] = {
4093 /* CLK */
4094 RCAR_GP_PIN(1, 27),
4095};
4096static const unsigned int vin4_clk_mux[] = {
4097 VI4_CLK_MARK,
4098};
4099
4100/* - VIN5 ------------------------------------------------------------------- */
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4101static const unsigned int vin5_data_pins[] = {
4102 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4103 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4104 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4105 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4106 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4107 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4108 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4109 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4110};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4111static const unsigned int vin5_data_mux[] = {
4112 VI5_DATA0_MARK, VI5_DATA1_MARK,
4113 VI5_DATA2_MARK, VI5_DATA3_MARK,
4114 VI5_DATA4_MARK, VI5_DATA5_MARK,
4115 VI5_DATA6_MARK, VI5_DATA7_MARK,
4116 VI5_DATA8_MARK, VI5_DATA9_MARK,
4117 VI5_DATA10_MARK, VI5_DATA11_MARK,
4118 VI5_DATA12_MARK, VI5_DATA13_MARK,
4119 VI5_DATA14_MARK, VI5_DATA15_MARK,
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4120};
4121static const unsigned int vin5_sync_pins[] = {
4122 /* HSYNC#, VSYNC# */
4123 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
4124};
4125static const unsigned int vin5_sync_mux[] = {
4126 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
4127};
4128static const unsigned int vin5_field_pins[] = {
4129 RCAR_GP_PIN(1, 11),
4130};
4131static const unsigned int vin5_field_mux[] = {
4132 /* FIELD */
4133 VI5_FIELD_MARK,
4134};
4135static const unsigned int vin5_clkenb_pins[] = {
4136 RCAR_GP_PIN(1, 20),
4137};
4138static const unsigned int vin5_clkenb_mux[] = {
4139 /* CLKENB */
4140 VI5_CLKENB_MARK,
4141};
4142static const unsigned int vin5_clk_pins[] = {
4143 RCAR_GP_PIN(1, 21),
4144};
4145static const unsigned int vin5_clk_mux[] = {
4146 /* CLK */
4147 VI5_CLK_MARK,
4148};
4149
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4150static const struct {
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4151 struct sh_pfc_pin_group common[328];
4152#ifdef CONFIG_PINCTRL_PFC_R8A77951
4153 struct sh_pfc_pin_group automotive[31];
Biju Dasd2288272020-10-28 10:34:25 +0000[diff] [blame]4154#endif
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4155} pinmux_groups = {
4156 .common = {
4157 SH_PFC_PIN_GROUP(audio_clk_a_a),
4158 SH_PFC_PIN_GROUP(audio_clk_a_b),
4159 SH_PFC_PIN_GROUP(audio_clk_a_c),
4160 SH_PFC_PIN_GROUP(audio_clk_b_a),
4161 SH_PFC_PIN_GROUP(audio_clk_b_b),
4162 SH_PFC_PIN_GROUP(audio_clk_c_a),
4163 SH_PFC_PIN_GROUP(audio_clk_c_b),
4164 SH_PFC_PIN_GROUP(audio_clkout_a),
4165 SH_PFC_PIN_GROUP(audio_clkout_b),
4166 SH_PFC_PIN_GROUP(audio_clkout_c),
4167 SH_PFC_PIN_GROUP(audio_clkout_d),
4168 SH_PFC_PIN_GROUP(audio_clkout1_a),
4169 SH_PFC_PIN_GROUP(audio_clkout1_b),
4170 SH_PFC_PIN_GROUP(audio_clkout2_a),
4171 SH_PFC_PIN_GROUP(audio_clkout2_b),
4172 SH_PFC_PIN_GROUP(audio_clkout3_a),
4173 SH_PFC_PIN_GROUP(audio_clkout3_b),
4174 SH_PFC_PIN_GROUP(avb_link),
4175 SH_PFC_PIN_GROUP(avb_magic),
4176 SH_PFC_PIN_GROUP(avb_phy_int),
4177 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
4178 SH_PFC_PIN_GROUP(avb_mdio),
4179 SH_PFC_PIN_GROUP(avb_mii),
4180 SH_PFC_PIN_GROUP(avb_avtp_pps),
4181 SH_PFC_PIN_GROUP(avb_avtp_match_a),
4182 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4183 SH_PFC_PIN_GROUP(avb_avtp_match_b),
4184 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
4185 SH_PFC_PIN_GROUP(can0_data_a),
4186 SH_PFC_PIN_GROUP(can0_data_b),
4187 SH_PFC_PIN_GROUP(can1_data),
4188 SH_PFC_PIN_GROUP(can_clk),
4189 SH_PFC_PIN_GROUP(canfd0_data_a),
4190 SH_PFC_PIN_GROUP(canfd0_data_b),
4191 SH_PFC_PIN_GROUP(canfd1_data),
4192 SH_PFC_PIN_GROUP(du_rgb666),
4193 SH_PFC_PIN_GROUP(du_rgb888),
4194 SH_PFC_PIN_GROUP(du_clk_out_0),
4195 SH_PFC_PIN_GROUP(du_clk_out_1),
4196 SH_PFC_PIN_GROUP(du_sync),
4197 SH_PFC_PIN_GROUP(du_oddf),
4198 SH_PFC_PIN_GROUP(du_cde),
4199 SH_PFC_PIN_GROUP(du_disp),
4200 SH_PFC_PIN_GROUP(hscif0_data),
4201 SH_PFC_PIN_GROUP(hscif0_clk),
4202 SH_PFC_PIN_GROUP(hscif0_ctrl),
4203 SH_PFC_PIN_GROUP(hscif1_data_a),
4204 SH_PFC_PIN_GROUP(hscif1_clk_a),
4205 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
4206 SH_PFC_PIN_GROUP(hscif1_data_b),
4207 SH_PFC_PIN_GROUP(hscif1_clk_b),
4208 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4209 SH_PFC_PIN_GROUP(hscif2_data_a),
4210 SH_PFC_PIN_GROUP(hscif2_clk_a),
4211 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4212 SH_PFC_PIN_GROUP(hscif2_data_b),
4213 SH_PFC_PIN_GROUP(hscif2_clk_b),
4214 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4215 SH_PFC_PIN_GROUP(hscif2_data_c),
4216 SH_PFC_PIN_GROUP(hscif2_clk_c),
4217 SH_PFC_PIN_GROUP(hscif2_ctrl_c),
4218 SH_PFC_PIN_GROUP(hscif3_data_a),
4219 SH_PFC_PIN_GROUP(hscif3_clk),
4220 SH_PFC_PIN_GROUP(hscif3_ctrl),
4221 SH_PFC_PIN_GROUP(hscif3_data_b),
4222 SH_PFC_PIN_GROUP(hscif3_data_c),
4223 SH_PFC_PIN_GROUP(hscif3_data_d),
4224 SH_PFC_PIN_GROUP(hscif4_data_a),
4225 SH_PFC_PIN_GROUP(hscif4_clk),
4226 SH_PFC_PIN_GROUP(hscif4_ctrl),
4227 SH_PFC_PIN_GROUP(hscif4_data_b),
4228 SH_PFC_PIN_GROUP(i2c0),
4229 SH_PFC_PIN_GROUP(i2c1_a),
4230 SH_PFC_PIN_GROUP(i2c1_b),
4231 SH_PFC_PIN_GROUP(i2c2_a),
4232 SH_PFC_PIN_GROUP(i2c2_b),
4233 SH_PFC_PIN_GROUP(i2c3),
4234 SH_PFC_PIN_GROUP(i2c5),
4235 SH_PFC_PIN_GROUP(i2c6_a),
4236 SH_PFC_PIN_GROUP(i2c6_b),
4237 SH_PFC_PIN_GROUP(i2c6_c),
4238 SH_PFC_PIN_GROUP(intc_ex_irq0),
4239 SH_PFC_PIN_GROUP(intc_ex_irq1),
4240 SH_PFC_PIN_GROUP(intc_ex_irq2),
4241 SH_PFC_PIN_GROUP(intc_ex_irq3),
4242 SH_PFC_PIN_GROUP(intc_ex_irq4),
4243 SH_PFC_PIN_GROUP(intc_ex_irq5),
4244 SH_PFC_PIN_GROUP(msiof0_clk),
4245 SH_PFC_PIN_GROUP(msiof0_sync),
4246 SH_PFC_PIN_GROUP(msiof0_ss1),
4247 SH_PFC_PIN_GROUP(msiof0_ss2),
4248 SH_PFC_PIN_GROUP(msiof0_txd),
4249 SH_PFC_PIN_GROUP(msiof0_rxd),
4250 SH_PFC_PIN_GROUP(msiof1_clk_a),
4251 SH_PFC_PIN_GROUP(msiof1_sync_a),
4252 SH_PFC_PIN_GROUP(msiof1_ss1_a),
4253 SH_PFC_PIN_GROUP(msiof1_ss2_a),
4254 SH_PFC_PIN_GROUP(msiof1_txd_a),
4255 SH_PFC_PIN_GROUP(msiof1_rxd_a),
4256 SH_PFC_PIN_GROUP(msiof1_clk_b),
4257 SH_PFC_PIN_GROUP(msiof1_sync_b),
4258 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4259 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4260 SH_PFC_PIN_GROUP(msiof1_txd_b),
4261 SH_PFC_PIN_GROUP(msiof1_rxd_b),
4262 SH_PFC_PIN_GROUP(msiof1_clk_c),
4263 SH_PFC_PIN_GROUP(msiof1_sync_c),
4264 SH_PFC_PIN_GROUP(msiof1_ss1_c),
4265 SH_PFC_PIN_GROUP(msiof1_ss2_c),
4266 SH_PFC_PIN_GROUP(msiof1_txd_c),
4267 SH_PFC_PIN_GROUP(msiof1_rxd_c),
4268 SH_PFC_PIN_GROUP(msiof1_clk_d),
4269 SH_PFC_PIN_GROUP(msiof1_sync_d),
4270 SH_PFC_PIN_GROUP(msiof1_ss1_d),
4271 SH_PFC_PIN_GROUP(msiof1_ss2_d),
4272 SH_PFC_PIN_GROUP(msiof1_txd_d),
4273 SH_PFC_PIN_GROUP(msiof1_rxd_d),
4274 SH_PFC_PIN_GROUP(msiof1_clk_e),
4275 SH_PFC_PIN_GROUP(msiof1_sync_e),
4276 SH_PFC_PIN_GROUP(msiof1_ss1_e),
4277 SH_PFC_PIN_GROUP(msiof1_ss2_e),
4278 SH_PFC_PIN_GROUP(msiof1_txd_e),
4279 SH_PFC_PIN_GROUP(msiof1_rxd_e),
4280 SH_PFC_PIN_GROUP(msiof1_clk_f),
4281 SH_PFC_PIN_GROUP(msiof1_sync_f),
4282 SH_PFC_PIN_GROUP(msiof1_ss1_f),
4283 SH_PFC_PIN_GROUP(msiof1_ss2_f),
4284 SH_PFC_PIN_GROUP(msiof1_txd_f),
4285 SH_PFC_PIN_GROUP(msiof1_rxd_f),
4286 SH_PFC_PIN_GROUP(msiof1_clk_g),
4287 SH_PFC_PIN_GROUP(msiof1_sync_g),
4288 SH_PFC_PIN_GROUP(msiof1_ss1_g),
4289 SH_PFC_PIN_GROUP(msiof1_ss2_g),
4290 SH_PFC_PIN_GROUP(msiof1_txd_g),
4291 SH_PFC_PIN_GROUP(msiof1_rxd_g),
4292 SH_PFC_PIN_GROUP(msiof2_clk_a),
4293 SH_PFC_PIN_GROUP(msiof2_sync_a),
4294 SH_PFC_PIN_GROUP(msiof2_ss1_a),
4295 SH_PFC_PIN_GROUP(msiof2_ss2_a),
4296 SH_PFC_PIN_GROUP(msiof2_txd_a),
4297 SH_PFC_PIN_GROUP(msiof2_rxd_a),
4298 SH_PFC_PIN_GROUP(msiof2_clk_b),
4299 SH_PFC_PIN_GROUP(msiof2_sync_b),
4300 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4301 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4302 SH_PFC_PIN_GROUP(msiof2_txd_b),
4303 SH_PFC_PIN_GROUP(msiof2_rxd_b),
4304 SH_PFC_PIN_GROUP(msiof2_clk_c),
4305 SH_PFC_PIN_GROUP(msiof2_sync_c),
4306 SH_PFC_PIN_GROUP(msiof2_ss1_c),
4307 SH_PFC_PIN_GROUP(msiof2_ss2_c),
4308 SH_PFC_PIN_GROUP(msiof2_txd_c),
4309 SH_PFC_PIN_GROUP(msiof2_rxd_c),
4310 SH_PFC_PIN_GROUP(msiof2_clk_d),
4311 SH_PFC_PIN_GROUP(msiof2_sync_d),
4312 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4313 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4314 SH_PFC_PIN_GROUP(msiof2_txd_d),
4315 SH_PFC_PIN_GROUP(msiof2_rxd_d),
4316 SH_PFC_PIN_GROUP(msiof3_clk_a),
4317 SH_PFC_PIN_GROUP(msiof3_sync_a),
4318 SH_PFC_PIN_GROUP(msiof3_ss1_a),
4319 SH_PFC_PIN_GROUP(msiof3_ss2_a),
4320 SH_PFC_PIN_GROUP(msiof3_txd_a),
4321 SH_PFC_PIN_GROUP(msiof3_rxd_a),
4322 SH_PFC_PIN_GROUP(msiof3_clk_b),
4323 SH_PFC_PIN_GROUP(msiof3_sync_b),
4324 SH_PFC_PIN_GROUP(msiof3_ss1_b),
4325 SH_PFC_PIN_GROUP(msiof3_ss2_b),
4326 SH_PFC_PIN_GROUP(msiof3_txd_b),
4327 SH_PFC_PIN_GROUP(msiof3_rxd_b),
4328 SH_PFC_PIN_GROUP(msiof3_clk_c),
4329 SH_PFC_PIN_GROUP(msiof3_sync_c),
4330 SH_PFC_PIN_GROUP(msiof3_txd_c),
4331 SH_PFC_PIN_GROUP(msiof3_rxd_c),
4332 SH_PFC_PIN_GROUP(msiof3_clk_d),
4333 SH_PFC_PIN_GROUP(msiof3_sync_d),
4334 SH_PFC_PIN_GROUP(msiof3_ss1_d),
4335 SH_PFC_PIN_GROUP(msiof3_txd_d),
4336 SH_PFC_PIN_GROUP(msiof3_rxd_d),
4337 SH_PFC_PIN_GROUP(msiof3_clk_e),
4338 SH_PFC_PIN_GROUP(msiof3_sync_e),
4339 SH_PFC_PIN_GROUP(msiof3_ss1_e),
4340 SH_PFC_PIN_GROUP(msiof3_ss2_e),
4341 SH_PFC_PIN_GROUP(msiof3_txd_e),
4342 SH_PFC_PIN_GROUP(msiof3_rxd_e),
4343 SH_PFC_PIN_GROUP(pwm0),
4344 SH_PFC_PIN_GROUP(pwm1_a),
4345 SH_PFC_PIN_GROUP(pwm1_b),
4346 SH_PFC_PIN_GROUP(pwm2_a),
4347 SH_PFC_PIN_GROUP(pwm2_b),
4348 SH_PFC_PIN_GROUP(pwm3_a),
4349 SH_PFC_PIN_GROUP(pwm3_b),
4350 SH_PFC_PIN_GROUP(pwm4_a),
4351 SH_PFC_PIN_GROUP(pwm4_b),
4352 SH_PFC_PIN_GROUP(pwm5_a),
4353 SH_PFC_PIN_GROUP(pwm5_b),
4354 SH_PFC_PIN_GROUP(pwm6_a),
4355 SH_PFC_PIN_GROUP(pwm6_b),
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]4356 SH_PFC_PIN_GROUP(qspi0_ctrl),
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4357 BUS_DATA_PIN_GROUP(qspi0_data, 2),
4358 BUS_DATA_PIN_GROUP(qspi0_data, 4),
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]4359 SH_PFC_PIN_GROUP(qspi1_ctrl),
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4360 BUS_DATA_PIN_GROUP(qspi1_data, 2),
4361 BUS_DATA_PIN_GROUP(qspi1_data, 4),
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4362 SH_PFC_PIN_GROUP(sata0_devslp_a),
4363 SH_PFC_PIN_GROUP(sata0_devslp_b),
4364 SH_PFC_PIN_GROUP(scif0_data),
4365 SH_PFC_PIN_GROUP(scif0_clk),
4366 SH_PFC_PIN_GROUP(scif0_ctrl),
4367 SH_PFC_PIN_GROUP(scif1_data_a),
4368 SH_PFC_PIN_GROUP(scif1_clk),
4369 SH_PFC_PIN_GROUP(scif1_ctrl),
4370 SH_PFC_PIN_GROUP(scif1_data_b),
4371 SH_PFC_PIN_GROUP(scif2_data_a),
4372 SH_PFC_PIN_GROUP(scif2_clk),
4373 SH_PFC_PIN_GROUP(scif2_data_b),
4374 SH_PFC_PIN_GROUP(scif3_data_a),
4375 SH_PFC_PIN_GROUP(scif3_clk),
4376 SH_PFC_PIN_GROUP(scif3_ctrl),
4377 SH_PFC_PIN_GROUP(scif3_data_b),
4378 SH_PFC_PIN_GROUP(scif4_data_a),
4379 SH_PFC_PIN_GROUP(scif4_clk_a),
4380 SH_PFC_PIN_GROUP(scif4_ctrl_a),
4381 SH_PFC_PIN_GROUP(scif4_data_b),
4382 SH_PFC_PIN_GROUP(scif4_clk_b),
4383 SH_PFC_PIN_GROUP(scif4_ctrl_b),
4384 SH_PFC_PIN_GROUP(scif4_data_c),
4385 SH_PFC_PIN_GROUP(scif4_clk_c),
4386 SH_PFC_PIN_GROUP(scif4_ctrl_c),
4387 SH_PFC_PIN_GROUP(scif5_data_a),
4388 SH_PFC_PIN_GROUP(scif5_clk_a),
4389 SH_PFC_PIN_GROUP(scif5_data_b),
4390 SH_PFC_PIN_GROUP(scif5_clk_b),
4391 SH_PFC_PIN_GROUP(scif_clk_a),
4392 SH_PFC_PIN_GROUP(scif_clk_b),
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4393 BUS_DATA_PIN_GROUP(sdhi0_data, 1),
4394 BUS_DATA_PIN_GROUP(sdhi0_data, 4),
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4395 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4396 SH_PFC_PIN_GROUP(sdhi0_cd),
4397 SH_PFC_PIN_GROUP(sdhi0_wp),
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4398 BUS_DATA_PIN_GROUP(sdhi1_data, 1),
4399 BUS_DATA_PIN_GROUP(sdhi1_data, 4),
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4400 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4401 SH_PFC_PIN_GROUP(sdhi1_cd),
4402 SH_PFC_PIN_GROUP(sdhi1_wp),
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4403 BUS_DATA_PIN_GROUP(sdhi2_data, 1),
4404 BUS_DATA_PIN_GROUP(sdhi2_data, 4),
4405 BUS_DATA_PIN_GROUP(sdhi2_data, 8),
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4406 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4407 SH_PFC_PIN_GROUP(sdhi2_cd_a),
4408 SH_PFC_PIN_GROUP(sdhi2_wp_a),
4409 SH_PFC_PIN_GROUP(sdhi2_cd_b),
4410 SH_PFC_PIN_GROUP(sdhi2_wp_b),
4411 SH_PFC_PIN_GROUP(sdhi2_ds),
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4412 BUS_DATA_PIN_GROUP(sdhi3_data, 1),
4413 BUS_DATA_PIN_GROUP(sdhi3_data, 4),
4414 BUS_DATA_PIN_GROUP(sdhi3_data, 8),
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4415 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4416 SH_PFC_PIN_GROUP(sdhi3_cd),
4417 SH_PFC_PIN_GROUP(sdhi3_wp),
4418 SH_PFC_PIN_GROUP(sdhi3_ds),
4419 SH_PFC_PIN_GROUP(ssi0_data),
4420 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4421 SH_PFC_PIN_GROUP(ssi1_data_a),
4422 SH_PFC_PIN_GROUP(ssi1_data_b),
4423 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4424 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4425 SH_PFC_PIN_GROUP(ssi2_data_a),
4426 SH_PFC_PIN_GROUP(ssi2_data_b),
4427 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4428 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4429 SH_PFC_PIN_GROUP(ssi3_data),
4430 SH_PFC_PIN_GROUP(ssi349_ctrl),
4431 SH_PFC_PIN_GROUP(ssi4_data),
4432 SH_PFC_PIN_GROUP(ssi4_ctrl),
4433 SH_PFC_PIN_GROUP(ssi5_data),
4434 SH_PFC_PIN_GROUP(ssi5_ctrl),
4435 SH_PFC_PIN_GROUP(ssi6_data),
4436 SH_PFC_PIN_GROUP(ssi6_ctrl),
4437 SH_PFC_PIN_GROUP(ssi7_data),
4438 SH_PFC_PIN_GROUP(ssi78_ctrl),
4439 SH_PFC_PIN_GROUP(ssi8_data),
4440 SH_PFC_PIN_GROUP(ssi9_data_a),
4441 SH_PFC_PIN_GROUP(ssi9_data_b),
4442 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4443 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4444 SH_PFC_PIN_GROUP(tmu_tclk1_a),
4445 SH_PFC_PIN_GROUP(tmu_tclk1_b),
4446 SH_PFC_PIN_GROUP(tmu_tclk2_a),
4447 SH_PFC_PIN_GROUP(tmu_tclk2_b),
4448 SH_PFC_PIN_GROUP(tpu_to0),
4449 SH_PFC_PIN_GROUP(tpu_to1),
4450 SH_PFC_PIN_GROUP(tpu_to2),
4451 SH_PFC_PIN_GROUP(tpu_to3),
4452 SH_PFC_PIN_GROUP(usb0),
4453 SH_PFC_PIN_GROUP(usb1),
4454 SH_PFC_PIN_GROUP(usb2),
4455 SH_PFC_PIN_GROUP(usb2_ch3),
4456 SH_PFC_PIN_GROUP(usb30),
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4457 BUS_DATA_PIN_GROUP(vin4_data, 8, _a),
4458 BUS_DATA_PIN_GROUP(vin4_data, 10, _a),
4459 BUS_DATA_PIN_GROUP(vin4_data, 12, _a),
4460 BUS_DATA_PIN_GROUP(vin4_data, 16, _a),
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4461 SH_PFC_PIN_GROUP(vin4_data18_a),
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4462 BUS_DATA_PIN_GROUP(vin4_data, 20, _a),
4463 BUS_DATA_PIN_GROUP(vin4_data, 24, _a),
4464 BUS_DATA_PIN_GROUP(vin4_data, 8, _b),
4465 BUS_DATA_PIN_GROUP(vin4_data, 10, _b),
4466 BUS_DATA_PIN_GROUP(vin4_data, 12, _b),
4467 BUS_DATA_PIN_GROUP(vin4_data, 16, _b),
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4468 SH_PFC_PIN_GROUP(vin4_data18_b),
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4469 BUS_DATA_PIN_GROUP(vin4_data, 20, _b),
4470 BUS_DATA_PIN_GROUP(vin4_data, 24, _b),
4471 SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8),
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4472 SH_PFC_PIN_GROUP(vin4_sync),
4473 SH_PFC_PIN_GROUP(vin4_field),
4474 SH_PFC_PIN_GROUP(vin4_clkenb),
4475 SH_PFC_PIN_GROUP(vin4_clk),
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4476 BUS_DATA_PIN_GROUP(vin5_data, 8),
4477 BUS_DATA_PIN_GROUP(vin5_data, 10),
4478 BUS_DATA_PIN_GROUP(vin5_data, 12),
4479 BUS_DATA_PIN_GROUP(vin5_data, 16),
4480 SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data, 8, 8),
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4481 SH_PFC_PIN_GROUP(vin5_sync),
4482 SH_PFC_PIN_GROUP(vin5_field),
4483 SH_PFC_PIN_GROUP(vin5_clkenb),
4484 SH_PFC_PIN_GROUP(vin5_clk),
4485 },
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4486#ifdef CONFIG_PINCTRL_PFC_R8A77951
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4487 .automotive = {
4488 SH_PFC_PIN_GROUP(drif0_ctrl_a),
4489 SH_PFC_PIN_GROUP(drif0_data0_a),
4490 SH_PFC_PIN_GROUP(drif0_data1_a),
4491 SH_PFC_PIN_GROUP(drif0_ctrl_b),
4492 SH_PFC_PIN_GROUP(drif0_data0_b),
4493 SH_PFC_PIN_GROUP(drif0_data1_b),
4494 SH_PFC_PIN_GROUP(drif0_ctrl_c),
4495 SH_PFC_PIN_GROUP(drif0_data0_c),
4496 SH_PFC_PIN_GROUP(drif0_data1_c),
4497 SH_PFC_PIN_GROUP(drif1_ctrl_a),
4498 SH_PFC_PIN_GROUP(drif1_data0_a),
4499 SH_PFC_PIN_GROUP(drif1_data1_a),
4500 SH_PFC_PIN_GROUP(drif1_ctrl_b),
4501 SH_PFC_PIN_GROUP(drif1_data0_b),
4502 SH_PFC_PIN_GROUP(drif1_data1_b),
4503 SH_PFC_PIN_GROUP(drif1_ctrl_c),
4504 SH_PFC_PIN_GROUP(drif1_data0_c),
4505 SH_PFC_PIN_GROUP(drif1_data1_c),
4506 SH_PFC_PIN_GROUP(drif2_ctrl_a),
4507 SH_PFC_PIN_GROUP(drif2_data0_a),
4508 SH_PFC_PIN_GROUP(drif2_data1_a),
4509 SH_PFC_PIN_GROUP(drif2_ctrl_b),
4510 SH_PFC_PIN_GROUP(drif2_data0_b),
4511 SH_PFC_PIN_GROUP(drif2_data1_b),
4512 SH_PFC_PIN_GROUP(drif3_ctrl_a),
4513 SH_PFC_PIN_GROUP(drif3_data0_a),
4514 SH_PFC_PIN_GROUP(drif3_data1_a),
4515 SH_PFC_PIN_GROUP(drif3_ctrl_b),
4516 SH_PFC_PIN_GROUP(drif3_data0_b),
4517 SH_PFC_PIN_GROUP(drif3_data1_b),
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4518 SH_PFC_PIN_GROUP(mlb_3pin),
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]4519 }
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4520#endif /* CONFIG_PINCTRL_PFC_R8A77951 */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4521};
4522
4523static const char * const audio_clk_groups[] = {
4524 "audio_clk_a_a",
4525 "audio_clk_a_b",
4526 "audio_clk_a_c",
4527 "audio_clk_b_a",
4528 "audio_clk_b_b",
4529 "audio_clk_c_a",
4530 "audio_clk_c_b",
4531 "audio_clkout_a",
4532 "audio_clkout_b",
4533 "audio_clkout_c",
4534 "audio_clkout_d",
4535 "audio_clkout1_a",
4536 "audio_clkout1_b",
4537 "audio_clkout2_a",
4538 "audio_clkout2_b",
4539 "audio_clkout3_a",
4540 "audio_clkout3_b",
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4541};
4542
4543static const char * const avb_groups[] = {
4544 "avb_link",
4545 "avb_magic",
4546 "avb_phy_int",
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4547 "avb_mdc", /* Deprecated, please use "avb_mdio" instead */
4548 "avb_mdio",
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4549 "avb_mii",
4550 "avb_avtp_pps",
4551 "avb_avtp_match_a",
4552 "avb_avtp_capture_a",
4553 "avb_avtp_match_b",
4554 "avb_avtp_capture_b",
4555};
4556
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4557static const char * const can0_groups[] = {
4558 "can0_data_a",
4559 "can0_data_b",
4560};
4561
4562static const char * const can1_groups[] = {
4563 "can1_data",
4564};
4565
4566static const char * const can_clk_groups[] = {
4567 "can_clk",
4568};
4569
4570static const char * const canfd0_groups[] = {
4571 "canfd0_data_a",
4572 "canfd0_data_b",
4573};
4574
4575static const char * const canfd1_groups[] = {
4576 "canfd1_data",
4577};
4578
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4579#ifdef CONFIG_PINCTRL_PFC_R8A77951
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4580static const char * const drif0_groups[] = {
4581 "drif0_ctrl_a",
4582 "drif0_data0_a",
4583 "drif0_data1_a",
4584 "drif0_ctrl_b",
4585 "drif0_data0_b",
4586 "drif0_data1_b",
4587 "drif0_ctrl_c",
4588 "drif0_data0_c",
4589 "drif0_data1_c",
4590};
4591
4592static const char * const drif1_groups[] = {
4593 "drif1_ctrl_a",
4594 "drif1_data0_a",
4595 "drif1_data1_a",
4596 "drif1_ctrl_b",
4597 "drif1_data0_b",
4598 "drif1_data1_b",
4599 "drif1_ctrl_c",
4600 "drif1_data0_c",
4601 "drif1_data1_c",
4602};
4603
4604static const char * const drif2_groups[] = {
4605 "drif2_ctrl_a",
4606 "drif2_data0_a",
4607 "drif2_data1_a",
4608 "drif2_ctrl_b",
4609 "drif2_data0_b",
4610 "drif2_data1_b",
4611};
4612
4613static const char * const drif3_groups[] = {
4614 "drif3_ctrl_a",
4615 "drif3_data0_a",
4616 "drif3_data1_a",
4617 "drif3_ctrl_b",
4618 "drif3_data0_b",
4619 "drif3_data1_b",
4620};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4621#endif /* CONFIG_PINCTRL_PFC_R8A77951 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4622
4623static const char * const du_groups[] = {
4624 "du_rgb666",
4625 "du_rgb888",
4626 "du_clk_out_0",
4627 "du_clk_out_1",
4628 "du_sync",
4629 "du_oddf",
4630 "du_cde",
4631 "du_disp",
4632};
4633
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4634static const char * const hscif0_groups[] = {
4635 "hscif0_data",
4636 "hscif0_clk",
4637 "hscif0_ctrl",
4638};
4639
4640static const char * const hscif1_groups[] = {
4641 "hscif1_data_a",
4642 "hscif1_clk_a",
4643 "hscif1_ctrl_a",
4644 "hscif1_data_b",
4645 "hscif1_clk_b",
4646 "hscif1_ctrl_b",
4647};
4648
4649static const char * const hscif2_groups[] = {
4650 "hscif2_data_a",
4651 "hscif2_clk_a",
4652 "hscif2_ctrl_a",
4653 "hscif2_data_b",
4654 "hscif2_clk_b",
4655 "hscif2_ctrl_b",
4656 "hscif2_data_c",
4657 "hscif2_clk_c",
4658 "hscif2_ctrl_c",
4659};
4660
4661static const char * const hscif3_groups[] = {
4662 "hscif3_data_a",
4663 "hscif3_clk",
4664 "hscif3_ctrl",
4665 "hscif3_data_b",
4666 "hscif3_data_c",
4667 "hscif3_data_d",
4668};
4669
4670static const char * const hscif4_groups[] = {
4671 "hscif4_data_a",
4672 "hscif4_clk",
4673 "hscif4_ctrl",
4674 "hscif4_data_b",
4675};
4676
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4677static const char * const i2c0_groups[] = {
4678 "i2c0",
4679};
4680
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4681static const char * const i2c1_groups[] = {
4682 "i2c1_a",
4683 "i2c1_b",
4684};
4685
4686static const char * const i2c2_groups[] = {
4687 "i2c2_a",
4688 "i2c2_b",
4689};
4690
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4691static const char * const i2c3_groups[] = {
4692 "i2c3",
4693};
4694
4695static const char * const i2c5_groups[] = {
4696 "i2c5",
4697};
4698
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4699static const char * const i2c6_groups[] = {
4700 "i2c6_a",
4701 "i2c6_b",
4702 "i2c6_c",
4703};
4704
4705static const char * const intc_ex_groups[] = {
4706 "intc_ex_irq0",
4707 "intc_ex_irq1",
4708 "intc_ex_irq2",
4709 "intc_ex_irq3",
4710 "intc_ex_irq4",
4711 "intc_ex_irq5",
4712};
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]4713
4714#ifdef CONFIG_PINCTRL_PFC_R8A77951
4715static const char * const mlb_3pin_groups[] = {
4716 "mlb_3pin",
4717};
4718#endif /* CONFIG_PINCTRL_PFC_R8A77951 */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4719
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4720static const char * const msiof0_groups[] = {
4721 "msiof0_clk",
4722 "msiof0_sync",
4723 "msiof0_ss1",
4724 "msiof0_ss2",
4725 "msiof0_txd",
4726 "msiof0_rxd",
4727};
4728
4729static const char * const msiof1_groups[] = {
4730 "msiof1_clk_a",
4731 "msiof1_sync_a",
4732 "msiof1_ss1_a",
4733 "msiof1_ss2_a",
4734 "msiof1_txd_a",
4735 "msiof1_rxd_a",
4736 "msiof1_clk_b",
4737 "msiof1_sync_b",
4738 "msiof1_ss1_b",
4739 "msiof1_ss2_b",
4740 "msiof1_txd_b",
4741 "msiof1_rxd_b",
4742 "msiof1_clk_c",
4743 "msiof1_sync_c",
4744 "msiof1_ss1_c",
4745 "msiof1_ss2_c",
4746 "msiof1_txd_c",
4747 "msiof1_rxd_c",
4748 "msiof1_clk_d",
4749 "msiof1_sync_d",
4750 "msiof1_ss1_d",
4751 "msiof1_ss2_d",
4752 "msiof1_txd_d",
4753 "msiof1_rxd_d",
4754 "msiof1_clk_e",
4755 "msiof1_sync_e",
4756 "msiof1_ss1_e",
4757 "msiof1_ss2_e",
4758 "msiof1_txd_e",
4759 "msiof1_rxd_e",
4760 "msiof1_clk_f",
4761 "msiof1_sync_f",
4762 "msiof1_ss1_f",
4763 "msiof1_ss2_f",
4764 "msiof1_txd_f",
4765 "msiof1_rxd_f",
4766 "msiof1_clk_g",
4767 "msiof1_sync_g",
4768 "msiof1_ss1_g",
4769 "msiof1_ss2_g",
4770 "msiof1_txd_g",
4771 "msiof1_rxd_g",
4772};
4773
4774static const char * const msiof2_groups[] = {
4775 "msiof2_clk_a",
4776 "msiof2_sync_a",
4777 "msiof2_ss1_a",
4778 "msiof2_ss2_a",
4779 "msiof2_txd_a",
4780 "msiof2_rxd_a",
4781 "msiof2_clk_b",
4782 "msiof2_sync_b",
4783 "msiof2_ss1_b",
4784 "msiof2_ss2_b",
4785 "msiof2_txd_b",
4786 "msiof2_rxd_b",
4787 "msiof2_clk_c",
4788 "msiof2_sync_c",
4789 "msiof2_ss1_c",
4790 "msiof2_ss2_c",
4791 "msiof2_txd_c",
4792 "msiof2_rxd_c",
4793 "msiof2_clk_d",
4794 "msiof2_sync_d",
4795 "msiof2_ss1_d",
4796 "msiof2_ss2_d",
4797 "msiof2_txd_d",
4798 "msiof2_rxd_d",
4799};
4800
4801static const char * const msiof3_groups[] = {
4802 "msiof3_clk_a",
4803 "msiof3_sync_a",
4804 "msiof3_ss1_a",
4805 "msiof3_ss2_a",
4806 "msiof3_txd_a",
4807 "msiof3_rxd_a",
4808 "msiof3_clk_b",
4809 "msiof3_sync_b",
4810 "msiof3_ss1_b",
4811 "msiof3_ss2_b",
4812 "msiof3_txd_b",
4813 "msiof3_rxd_b",
4814 "msiof3_clk_c",
4815 "msiof3_sync_c",
4816 "msiof3_txd_c",
4817 "msiof3_rxd_c",
4818 "msiof3_clk_d",
4819 "msiof3_sync_d",
4820 "msiof3_ss1_d",
4821 "msiof3_txd_d",
4822 "msiof3_rxd_d",
4823 "msiof3_clk_e",
4824 "msiof3_sync_e",
4825 "msiof3_ss1_e",
4826 "msiof3_ss2_e",
4827 "msiof3_txd_e",
4828 "msiof3_rxd_e",
4829};
4830
4831static const char * const pwm0_groups[] = {
4832 "pwm0",
4833};
4834
4835static const char * const pwm1_groups[] = {
4836 "pwm1_a",
4837 "pwm1_b",
4838};
4839
4840static const char * const pwm2_groups[] = {
4841 "pwm2_a",
4842 "pwm2_b",
4843};
4844
4845static const char * const pwm3_groups[] = {
4846 "pwm3_a",
4847 "pwm3_b",
4848};
4849
4850static const char * const pwm4_groups[] = {
4851 "pwm4_a",
4852 "pwm4_b",
4853};
4854
4855static const char * const pwm5_groups[] = {
4856 "pwm5_a",
4857 "pwm5_b",
4858};
4859
4860static const char * const pwm6_groups[] = {
4861 "pwm6_a",
4862 "pwm6_b",
4863};
4864
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]4865static const char * const qspi0_groups[] = {
4866 "qspi0_ctrl",
4867 "qspi0_data2",
4868 "qspi0_data4",
4869};
4870
4871static const char * const qspi1_groups[] = {
4872 "qspi1_ctrl",
4873 "qspi1_data2",
4874 "qspi1_data4",
4875};
4876
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4877static const char * const sata0_groups[] = {
4878 "sata0_devslp_a",
4879 "sata0_devslp_b",
4880};
4881
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]4882static const char * const scif0_groups[] = {
4883 "scif0_data",
4884 "scif0_clk",
4885 "scif0_ctrl",
4886};
4887
4888static const char * const scif1_groups[] = {
4889 "scif1_data_a",
4890 "scif1_clk",
4891 "scif1_ctrl",
4892 "scif1_data_b",
4893};
4894
4895static const char * const scif2_groups[] = {
4896 "scif2_data_a",
4897 "scif2_clk",
4898 "scif2_data_b",
4899};
4900
4901static const char * const scif3_groups[] = {
4902 "scif3_data_a",
4903 "scif3_clk",
4904 "scif3_ctrl",
4905 "scif3_data_b",
4906};
4907
4908static const char * const scif4_groups[] = {
4909 "scif4_data_a",
4910 "scif4_clk_a",
4911 "scif4_ctrl_a",
4912 "scif4_data_b",
4913 "scif4_clk_b",
4914 "scif4_ctrl_b",
4915 "scif4_data_c",
4916 "scif4_clk_c",
4917 "scif4_ctrl_c",
4918};
4919
4920static const char * const scif5_groups[] = {
4921 "scif5_data_a",
4922 "scif5_clk_a",
4923 "scif5_data_b",
4924 "scif5_clk_b",
4925};
4926
4927static const char * const scif_clk_groups[] = {
4928 "scif_clk_a",
4929 "scif_clk_b",
4930};
4931
4932static const char * const sdhi0_groups[] = {
4933 "sdhi0_data1",
4934 "sdhi0_data4",
4935 "sdhi0_ctrl",
4936 "sdhi0_cd",
4937 "sdhi0_wp",
4938};
4939
4940static const char * const sdhi1_groups[] = {
4941 "sdhi1_data1",
4942 "sdhi1_data4",
4943 "sdhi1_ctrl",
4944 "sdhi1_cd",
4945 "sdhi1_wp",
4946};
4947
4948static const char * const sdhi2_groups[] = {
4949 "sdhi2_data1",
4950 "sdhi2_data4",
4951 "sdhi2_data8",
4952 "sdhi2_ctrl",
4953 "sdhi2_cd_a",
4954 "sdhi2_wp_a",
4955 "sdhi2_cd_b",
4956 "sdhi2_wp_b",
4957 "sdhi2_ds",
4958};
4959
4960static const char * const sdhi3_groups[] = {
4961 "sdhi3_data1",
4962 "sdhi3_data4",
4963 "sdhi3_data8",
4964 "sdhi3_ctrl",
4965 "sdhi3_cd",
4966 "sdhi3_wp",
4967 "sdhi3_ds",
4968};
4969
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]4970static const char * const ssi_groups[] = {
4971 "ssi0_data",
4972 "ssi01239_ctrl",
4973 "ssi1_data_a",
4974 "ssi1_data_b",
4975 "ssi1_ctrl_a",
4976 "ssi1_ctrl_b",
4977 "ssi2_data_a",
4978 "ssi2_data_b",
4979 "ssi2_ctrl_a",
4980 "ssi2_ctrl_b",
4981 "ssi3_data",
4982 "ssi349_ctrl",
4983 "ssi4_data",
4984 "ssi4_ctrl",
4985 "ssi5_data",
4986 "ssi5_ctrl",
4987 "ssi6_data",
4988 "ssi6_ctrl",
4989 "ssi7_data",
4990 "ssi78_ctrl",
4991 "ssi8_data",
4992 "ssi9_data_a",
4993 "ssi9_data_b",
4994 "ssi9_ctrl_a",
4995 "ssi9_ctrl_b",
4996};
4997
4998static const char * const tmu_groups[] = {
4999 "tmu_tclk1_a",
5000 "tmu_tclk1_b",
5001 "tmu_tclk2_a",
5002 "tmu_tclk2_b",
5003};
5004
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]5005static const char * const tpu_groups[] = {
5006 "tpu_to0",
5007 "tpu_to1",
5008 "tpu_to2",
5009 "tpu_to3",
5010};
5011
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5012static const char * const usb0_groups[] = {
5013 "usb0",
5014};
5015
5016static const char * const usb1_groups[] = {
5017 "usb1",
5018};
5019
5020static const char * const usb2_groups[] = {
5021 "usb2",
5022};
5023
5024static const char * const usb2_ch3_groups[] = {
5025 "usb2_ch3",
5026};
5027
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5028static const char * const usb30_groups[] = {
5029 "usb30",
5030};
5031
5032static const char * const vin4_groups[] = {
5033 "vin4_data8_a",
5034 "vin4_data10_a",
5035 "vin4_data12_a",
5036 "vin4_data16_a",
5037 "vin4_data18_a",
5038 "vin4_data20_a",
5039 "vin4_data24_a",
5040 "vin4_data8_b",
5041 "vin4_data10_b",
5042 "vin4_data12_b",
5043 "vin4_data16_b",
5044 "vin4_data18_b",
5045 "vin4_data20_b",
5046 "vin4_data24_b",
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5047 "vin4_g8",
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5048 "vin4_sync",
5049 "vin4_field",
5050 "vin4_clkenb",
5051 "vin4_clk",
5052};
5053
5054static const char * const vin5_groups[] = {
5055 "vin5_data8",
5056 "vin5_data10",
5057 "vin5_data12",
5058 "vin5_data16",
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5059 "vin5_high8",
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5060 "vin5_sync",
5061 "vin5_field",
5062 "vin5_clkenb",
5063 "vin5_clk",
5064};
5065
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]5066static const struct {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5067 struct sh_pfc_function common[55];
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5068#ifdef CONFIG_PINCTRL_PFC_R8A77951
5069 struct sh_pfc_function automotive[5];
Biju Dasd2288272020-10-28 10:34:25 +0000[diff] [blame]5070#endif
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]5071} pinmux_functions = {
5072 .common = {
5073 SH_PFC_FUNCTION(audio_clk),
5074 SH_PFC_FUNCTION(avb),
5075 SH_PFC_FUNCTION(can0),
5076 SH_PFC_FUNCTION(can1),
5077 SH_PFC_FUNCTION(can_clk),
5078 SH_PFC_FUNCTION(canfd0),
5079 SH_PFC_FUNCTION(canfd1),
5080 SH_PFC_FUNCTION(du),
5081 SH_PFC_FUNCTION(hscif0),
5082 SH_PFC_FUNCTION(hscif1),
5083 SH_PFC_FUNCTION(hscif2),
5084 SH_PFC_FUNCTION(hscif3),
5085 SH_PFC_FUNCTION(hscif4),
5086 SH_PFC_FUNCTION(i2c0),
5087 SH_PFC_FUNCTION(i2c1),
5088 SH_PFC_FUNCTION(i2c2),
5089 SH_PFC_FUNCTION(i2c3),
5090 SH_PFC_FUNCTION(i2c5),
5091 SH_PFC_FUNCTION(i2c6),
5092 SH_PFC_FUNCTION(intc_ex),
5093 SH_PFC_FUNCTION(msiof0),
5094 SH_PFC_FUNCTION(msiof1),
5095 SH_PFC_FUNCTION(msiof2),
5096 SH_PFC_FUNCTION(msiof3),
5097 SH_PFC_FUNCTION(pwm0),
5098 SH_PFC_FUNCTION(pwm1),
5099 SH_PFC_FUNCTION(pwm2),
5100 SH_PFC_FUNCTION(pwm3),
5101 SH_PFC_FUNCTION(pwm4),
5102 SH_PFC_FUNCTION(pwm5),
5103 SH_PFC_FUNCTION(pwm6),
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5104 SH_PFC_FUNCTION(qspi0),
5105 SH_PFC_FUNCTION(qspi1),
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]5106 SH_PFC_FUNCTION(sata0),
5107 SH_PFC_FUNCTION(scif0),
5108 SH_PFC_FUNCTION(scif1),
5109 SH_PFC_FUNCTION(scif2),
5110 SH_PFC_FUNCTION(scif3),
5111 SH_PFC_FUNCTION(scif4),
5112 SH_PFC_FUNCTION(scif5),
5113 SH_PFC_FUNCTION(scif_clk),
5114 SH_PFC_FUNCTION(sdhi0),
5115 SH_PFC_FUNCTION(sdhi1),
5116 SH_PFC_FUNCTION(sdhi2),
5117 SH_PFC_FUNCTION(sdhi3),
5118 SH_PFC_FUNCTION(ssi),
5119 SH_PFC_FUNCTION(tmu),
5120 SH_PFC_FUNCTION(tpu),
5121 SH_PFC_FUNCTION(usb0),
5122 SH_PFC_FUNCTION(usb1),
5123 SH_PFC_FUNCTION(usb2),
5124 SH_PFC_FUNCTION(usb2_ch3),
5125 SH_PFC_FUNCTION(usb30),
5126 SH_PFC_FUNCTION(vin4),
5127 SH_PFC_FUNCTION(vin5),
5128 },
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5129#ifdef CONFIG_PINCTRL_PFC_R8A77951
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]5130 .automotive = {
5131 SH_PFC_FUNCTION(drif0),
5132 SH_PFC_FUNCTION(drif1),
5133 SH_PFC_FUNCTION(drif2),
5134 SH_PFC_FUNCTION(drif3),
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5135 SH_PFC_FUNCTION(mlb_3pin),
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]5136 }
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5137#endif /* CONFIG_PINCTRL_PFC_R8A77951 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5138};
5139
5140static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5141#define F_(x, y) FN_##y
5142#define FM(x) FN_##x
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5143 { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
5144 GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5145 1, 1, 1, 1, 1),
5146 GROUP(
5147 /* GP0_31_16 RESERVED */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5148 GP_0_15_FN, GPSR0_15,
5149 GP_0_14_FN, GPSR0_14,
5150 GP_0_13_FN, GPSR0_13,
5151 GP_0_12_FN, GPSR0_12,
5152 GP_0_11_FN, GPSR0_11,
5153 GP_0_10_FN, GPSR0_10,
5154 GP_0_9_FN, GPSR0_9,
5155 GP_0_8_FN, GPSR0_8,
5156 GP_0_7_FN, GPSR0_7,
5157 GP_0_6_FN, GPSR0_6,
5158 GP_0_5_FN, GPSR0_5,
5159 GP_0_4_FN, GPSR0_4,
5160 GP_0_3_FN, GPSR0_3,
5161 GP_0_2_FN, GPSR0_2,
5162 GP_0_1_FN, GPSR0_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5163 GP_0_0_FN, GPSR0_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5164 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5165 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5166 0, 0,
5167 0, 0,
5168 0, 0,
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5169 GP_1_28_FN, GPSR1_28,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5170 GP_1_27_FN, GPSR1_27,
5171 GP_1_26_FN, GPSR1_26,
5172 GP_1_25_FN, GPSR1_25,
5173 GP_1_24_FN, GPSR1_24,
5174 GP_1_23_FN, GPSR1_23,
5175 GP_1_22_FN, GPSR1_22,
5176 GP_1_21_FN, GPSR1_21,
5177 GP_1_20_FN, GPSR1_20,
5178 GP_1_19_FN, GPSR1_19,
5179 GP_1_18_FN, GPSR1_18,
5180 GP_1_17_FN, GPSR1_17,
5181 GP_1_16_FN, GPSR1_16,
5182 GP_1_15_FN, GPSR1_15,
5183 GP_1_14_FN, GPSR1_14,
5184 GP_1_13_FN, GPSR1_13,
5185 GP_1_12_FN, GPSR1_12,
5186 GP_1_11_FN, GPSR1_11,
5187 GP_1_10_FN, GPSR1_10,
5188 GP_1_9_FN, GPSR1_9,
5189 GP_1_8_FN, GPSR1_8,
5190 GP_1_7_FN, GPSR1_7,
5191 GP_1_6_FN, GPSR1_6,
5192 GP_1_5_FN, GPSR1_5,
5193 GP_1_4_FN, GPSR1_4,
5194 GP_1_3_FN, GPSR1_3,
5195 GP_1_2_FN, GPSR1_2,
5196 GP_1_1_FN, GPSR1_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5197 GP_1_0_FN, GPSR1_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5198 },
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5199 { PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32,
5200 GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5201 1, 1, 1, 1),
5202 GROUP(
5203 /* GP2_31_15 RESERVED */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5204 GP_2_14_FN, GPSR2_14,
5205 GP_2_13_FN, GPSR2_13,
5206 GP_2_12_FN, GPSR2_12,
5207 GP_2_11_FN, GPSR2_11,
5208 GP_2_10_FN, GPSR2_10,
5209 GP_2_9_FN, GPSR2_9,
5210 GP_2_8_FN, GPSR2_8,
5211 GP_2_7_FN, GPSR2_7,
5212 GP_2_6_FN, GPSR2_6,
5213 GP_2_5_FN, GPSR2_5,
5214 GP_2_4_FN, GPSR2_4,
5215 GP_2_3_FN, GPSR2_3,
5216 GP_2_2_FN, GPSR2_2,
5217 GP_2_1_FN, GPSR2_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5218 GP_2_0_FN, GPSR2_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5219 },
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5220 { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
5221 GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5222 1, 1, 1, 1, 1),
5223 GROUP(
5224 /* GP3_31_16 RESERVED */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5225 GP_3_15_FN, GPSR3_15,
5226 GP_3_14_FN, GPSR3_14,
5227 GP_3_13_FN, GPSR3_13,
5228 GP_3_12_FN, GPSR3_12,
5229 GP_3_11_FN, GPSR3_11,
5230 GP_3_10_FN, GPSR3_10,
5231 GP_3_9_FN, GPSR3_9,
5232 GP_3_8_FN, GPSR3_8,
5233 GP_3_7_FN, GPSR3_7,
5234 GP_3_6_FN, GPSR3_6,
5235 GP_3_5_FN, GPSR3_5,
5236 GP_3_4_FN, GPSR3_4,
5237 GP_3_3_FN, GPSR3_3,
5238 GP_3_2_FN, GPSR3_2,
5239 GP_3_1_FN, GPSR3_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5240 GP_3_0_FN, GPSR3_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5241 },
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5242 { PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
5243 GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5244 1, 1, 1, 1, 1, 1, 1),
5245 GROUP(
5246 /* GP4_31_18 RESERVED */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5247 GP_4_17_FN, GPSR4_17,
5248 GP_4_16_FN, GPSR4_16,
5249 GP_4_15_FN, GPSR4_15,
5250 GP_4_14_FN, GPSR4_14,
5251 GP_4_13_FN, GPSR4_13,
5252 GP_4_12_FN, GPSR4_12,
5253 GP_4_11_FN, GPSR4_11,
5254 GP_4_10_FN, GPSR4_10,
5255 GP_4_9_FN, GPSR4_9,
5256 GP_4_8_FN, GPSR4_8,
5257 GP_4_7_FN, GPSR4_7,
5258 GP_4_6_FN, GPSR4_6,
5259 GP_4_5_FN, GPSR4_5,
5260 GP_4_4_FN, GPSR4_4,
5261 GP_4_3_FN, GPSR4_3,
5262 GP_4_2_FN, GPSR4_2,
5263 GP_4_1_FN, GPSR4_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5264 GP_4_0_FN, GPSR4_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5265 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5266 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5267 0, 0,
5268 0, 0,
5269 0, 0,
5270 0, 0,
5271 0, 0,
5272 0, 0,
5273 GP_5_25_FN, GPSR5_25,
5274 GP_5_24_FN, GPSR5_24,
5275 GP_5_23_FN, GPSR5_23,
5276 GP_5_22_FN, GPSR5_22,
5277 GP_5_21_FN, GPSR5_21,
5278 GP_5_20_FN, GPSR5_20,
5279 GP_5_19_FN, GPSR5_19,
5280 GP_5_18_FN, GPSR5_18,
5281 GP_5_17_FN, GPSR5_17,
5282 GP_5_16_FN, GPSR5_16,
5283 GP_5_15_FN, GPSR5_15,
5284 GP_5_14_FN, GPSR5_14,
5285 GP_5_13_FN, GPSR5_13,
5286 GP_5_12_FN, GPSR5_12,
5287 GP_5_11_FN, GPSR5_11,
5288 GP_5_10_FN, GPSR5_10,
5289 GP_5_9_FN, GPSR5_9,
5290 GP_5_8_FN, GPSR5_8,
5291 GP_5_7_FN, GPSR5_7,
5292 GP_5_6_FN, GPSR5_6,
5293 GP_5_5_FN, GPSR5_5,
5294 GP_5_4_FN, GPSR5_4,
5295 GP_5_3_FN, GPSR5_3,
5296 GP_5_2_FN, GPSR5_2,
5297 GP_5_1_FN, GPSR5_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5298 GP_5_0_FN, GPSR5_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5299 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5300 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5301 GP_6_31_FN, GPSR6_31,
5302 GP_6_30_FN, GPSR6_30,
5303 GP_6_29_FN, GPSR6_29,
5304 GP_6_28_FN, GPSR6_28,
5305 GP_6_27_FN, GPSR6_27,
5306 GP_6_26_FN, GPSR6_26,
5307 GP_6_25_FN, GPSR6_25,
5308 GP_6_24_FN, GPSR6_24,
5309 GP_6_23_FN, GPSR6_23,
5310 GP_6_22_FN, GPSR6_22,
5311 GP_6_21_FN, GPSR6_21,
5312 GP_6_20_FN, GPSR6_20,
5313 GP_6_19_FN, GPSR6_19,
5314 GP_6_18_FN, GPSR6_18,
5315 GP_6_17_FN, GPSR6_17,
5316 GP_6_16_FN, GPSR6_16,
5317 GP_6_15_FN, GPSR6_15,
5318 GP_6_14_FN, GPSR6_14,
5319 GP_6_13_FN, GPSR6_13,
5320 GP_6_12_FN, GPSR6_12,
5321 GP_6_11_FN, GPSR6_11,
5322 GP_6_10_FN, GPSR6_10,
5323 GP_6_9_FN, GPSR6_9,
5324 GP_6_8_FN, GPSR6_8,
5325 GP_6_7_FN, GPSR6_7,
5326 GP_6_6_FN, GPSR6_6,
5327 GP_6_5_FN, GPSR6_5,
5328 GP_6_4_FN, GPSR6_4,
5329 GP_6_3_FN, GPSR6_3,
5330 GP_6_2_FN, GPSR6_2,
5331 GP_6_1_FN, GPSR6_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5332 GP_6_0_FN, GPSR6_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5333 },
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5334 { PINMUX_CFG_REG_VAR("GPSR7", 0xe606011c, 32,
5335 GROUP(-28, 1, 1, 1, 1),
5336 GROUP(
5337 /* GP7_31_4 RESERVED */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5338 GP_7_3_FN, GPSR7_3,
5339 GP_7_2_FN, GPSR7_2,
5340 GP_7_1_FN, GPSR7_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5341 GP_7_0_FN, GPSR7_0, ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5342 },
5343#undef F_
5344#undef FM
5345
5346#define F_(x, y) x,
5347#define FM(x) FN_##x,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5348 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5349 IP0_31_28
5350 IP0_27_24
5351 IP0_23_20
5352 IP0_19_16
5353 IP0_15_12
5354 IP0_11_8
5355 IP0_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5356 IP0_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5357 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5358 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5359 IP1_31_28
5360 IP1_27_24
5361 IP1_23_20
5362 IP1_19_16
5363 IP1_15_12
5364 IP1_11_8
5365 IP1_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5366 IP1_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5367 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5368 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5369 IP2_31_28
5370 IP2_27_24
5371 IP2_23_20
5372 IP2_19_16
5373 IP2_15_12
5374 IP2_11_8
5375 IP2_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5376 IP2_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5377 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5378 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5379 IP3_31_28
5380 IP3_27_24
5381 IP3_23_20
5382 IP3_19_16
5383 IP3_15_12
5384 IP3_11_8
5385 IP3_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5386 IP3_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5387 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5388 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5389 IP4_31_28
5390 IP4_27_24
5391 IP4_23_20
5392 IP4_19_16
5393 IP4_15_12
5394 IP4_11_8
5395 IP4_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5396 IP4_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5397 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5398 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5399 IP5_31_28
5400 IP5_27_24
5401 IP5_23_20
5402 IP5_19_16
5403 IP5_15_12
5404 IP5_11_8
5405 IP5_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5406 IP5_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5407 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5408 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5409 IP6_31_28
5410 IP6_27_24
5411 IP6_23_20
5412 IP6_19_16
5413 IP6_15_12
5414 IP6_11_8
5415 IP6_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5416 IP6_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5417 },
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5418 { PINMUX_CFG_REG_VAR("IPSR7", 0xe606021c, 32,
5419 GROUP(4, 4, 4, 4, -4, 4, 4, 4),
5420 GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5421 IP7_31_28
5422 IP7_27_24
5423 IP7_23_20
5424 IP7_19_16
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5425 /* IP7_15_12 RESERVED */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5426 IP7_11_8
5427 IP7_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5428 IP7_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5429 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5430 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5431 IP8_31_28
5432 IP8_27_24
5433 IP8_23_20
5434 IP8_19_16
5435 IP8_15_12
5436 IP8_11_8
5437 IP8_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5438 IP8_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5439 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5440 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5441 IP9_31_28
5442 IP9_27_24
5443 IP9_23_20
5444 IP9_19_16
5445 IP9_15_12
5446 IP9_11_8
5447 IP9_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5448 IP9_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5449 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5450 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5451 IP10_31_28
5452 IP10_27_24
5453 IP10_23_20
5454 IP10_19_16
5455 IP10_15_12
5456 IP10_11_8
5457 IP10_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5458 IP10_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5459 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5460 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5461 IP11_31_28
5462 IP11_27_24
5463 IP11_23_20
5464 IP11_19_16
5465 IP11_15_12
5466 IP11_11_8
5467 IP11_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5468 IP11_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5469 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5470 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5471 IP12_31_28
5472 IP12_27_24
5473 IP12_23_20
5474 IP12_19_16
5475 IP12_15_12
5476 IP12_11_8
5477 IP12_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5478 IP12_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5479 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5480 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5481 IP13_31_28
5482 IP13_27_24
5483 IP13_23_20
5484 IP13_19_16
5485 IP13_15_12
5486 IP13_11_8
5487 IP13_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5488 IP13_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5489 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5490 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5491 IP14_31_28
5492 IP14_27_24
5493 IP14_23_20
5494 IP14_19_16
5495 IP14_15_12
5496 IP14_11_8
5497 IP14_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5498 IP14_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5499 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5500 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5501 IP15_31_28
5502 IP15_27_24
5503 IP15_23_20
5504 IP15_19_16
5505 IP15_15_12
5506 IP15_11_8
5507 IP15_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5508 IP15_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5509 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5510 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5511 IP16_31_28
5512 IP16_27_24
5513 IP16_23_20
5514 IP16_19_16
5515 IP16_15_12
5516 IP16_11_8
5517 IP16_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5518 IP16_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5519 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5520 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5521 IP17_31_28
5522 IP17_27_24
5523 IP17_23_20
5524 IP17_19_16
5525 IP17_15_12
5526 IP17_11_8
5527 IP17_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5528 IP17_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5529 },
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5530 { PINMUX_CFG_REG_VAR("IPSR18", 0xe6060248, 32,
5531 GROUP(-24, 4, 4),
5532 GROUP(
5533 /* IP18_31_8 RESERVED */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5534 IP18_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5535 IP18_3_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5536 },
5537#undef F_
5538#undef FM
5539
5540#define F_(x, y) x,
5541#define FM(x) FN_##x,
5542 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5543 GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, -1, 2,
5544 1, 1, 1, 2, 2, 1, 2, -3),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5545 GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5546 MOD_SEL0_31_30_29
5547 MOD_SEL0_28_27
5548 MOD_SEL0_26_25_24
5549 MOD_SEL0_23
5550 MOD_SEL0_22
5551 MOD_SEL0_21
5552 MOD_SEL0_20
5553 MOD_SEL0_19
5554 MOD_SEL0_18_17
5555 MOD_SEL0_16
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5556 /* RESERVED 15 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5557 MOD_SEL0_14_13
5558 MOD_SEL0_12
5559 MOD_SEL0_11
5560 MOD_SEL0_10
5561 MOD_SEL0_9_8
5562 MOD_SEL0_7_6
5563 MOD_SEL0_5
5564 MOD_SEL0_4_3
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5565 /* RESERVED 2, 1, 0 */ ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5566 },
5567 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5568 GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5569 1, 1, 1, -2, 1, 1, 1, 1, 1, 1, 1),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5570 GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5571 MOD_SEL1_31_30
5572 MOD_SEL1_29_28_27
5573 MOD_SEL1_26
5574 MOD_SEL1_25_24
5575 MOD_SEL1_23_22_21
5576 MOD_SEL1_20
5577 MOD_SEL1_19
5578 MOD_SEL1_18_17
5579 MOD_SEL1_16
5580 MOD_SEL1_15_14
5581 MOD_SEL1_13
5582 MOD_SEL1_12
5583 MOD_SEL1_11
5584 MOD_SEL1_10
5585 MOD_SEL1_9
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5586 /* RESERVED 8, 7 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5587 MOD_SEL1_6
5588 MOD_SEL1_5
5589 MOD_SEL1_4
5590 MOD_SEL1_3
5591 MOD_SEL1_2
5592 MOD_SEL1_1
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5593 MOD_SEL1_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5594 },
5595 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5596 GROUP(1, 1, 1, 2, 1, 3, -1, 1, 1, 1, 1, 1,
5597 -16, 1),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5598 GROUP(
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5599 MOD_SEL2_31
5600 MOD_SEL2_30
5601 MOD_SEL2_29
5602 MOD_SEL2_28_27
5603 MOD_SEL2_26
5604 MOD_SEL2_25_24_23
5605 /* RESERVED 22 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5606 MOD_SEL2_21
5607 MOD_SEL2_20
5608 MOD_SEL2_19
5609 MOD_SEL2_18
5610 MOD_SEL2_17
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5611 /* RESERVED 16-1 */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5612 MOD_SEL2_0 ))
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5613 },
Marek Vasut14dfdd62023-09-17 16:08:40 +0200[diff] [blame]5614 { /* sentinel */ }
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5615};
5616
5617static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5618 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5619 { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
5620 { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */
5621 { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */
5622 { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */
5623 { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */
5624 { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */
5625 { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */
5626 { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5627 } },
5628 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5629 { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
5630 { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */
5631 { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */
5632 { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */
5633 { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */
5634 { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */
5635 { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */
5636 { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5637 } },
5638 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5639 { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
5640 { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
5641 { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */
5642 { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */
5643 { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
5644 { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
5645 { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */
5646 { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5647 } },
5648 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5649 { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
5650 { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */
5651 { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */
5652 { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */
5653 { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */
5654 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5655 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
5656 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5657 } },
5658 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5659 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
5660 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
5661 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
5662 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
5663 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
5664 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
5665 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
5666 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
5667 } },
5668 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5669 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
5670 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
5671 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
5672 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
5673 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
5674 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
5675 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
5676 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
5677 } },
5678 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5679 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
5680 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
5681 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
5682 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
5683 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
5684 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
5685 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
5686 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
5687 } },
5688 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5689 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
5690 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
5691 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
5692 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
5693 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
5694 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
5695 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
5696 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
5697 } },
5698 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5699 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5700 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
5701 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
5702 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
5703 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
5704 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
5705 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
5706 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
5707 } },
5708 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5709 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5710 { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5711 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
5712 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
5713 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
5714 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
5715 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
5716 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
5717 } },
5718 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5719 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
5720 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
5721 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
5722 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
5723 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
5724 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
5725 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
5726 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
5727 } },
5728 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5729 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5730 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5731 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5732 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
5733 { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
5734 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
5735 { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */
5736 { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5737 } },
5738 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5739#ifdef CONFIG_PINCTRL_PFC_R8A77951
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5740 { PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */
5741#endif
5742 { PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */
5743 { PIN_FSCLKST_N, 20, 2 }, /* FSCLKST# */
5744 { PIN_TMS, 4, 2 }, /* TMS */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5745 } },
5746 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5747 { PIN_TDO, 28, 2 }, /* TDO */
5748 { PIN_ASEBRK, 24, 2 }, /* ASEBRK */
5749 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5750 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
5751 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
5752 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
5753 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
5754 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5755 } },
5756 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5757 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
5758 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
5759 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
5760 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
5761 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
5762 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
5763 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
5764 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
5765 } },
5766 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5767 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
5768 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
5769 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
5770 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
5771 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
5772 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
5773 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
5774 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
5775 } },
5776 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5777 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
5778 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
5779 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
5780 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
5781 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
5782 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
5783 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
5784 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
5785 } },
5786 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5787 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
5788 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
5789 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
5790 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
5791 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
5792 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
5793 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
5794 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
5795 } },
5796 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5797 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5798 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
5799 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
5800 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5801 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5802 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
5803 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
5804 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
5805 } },
5806 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5807 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
5808 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
5809 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
5810 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
5811 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
5812 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
5813 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
5814 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
5815 } },
5816 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5817 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
5818 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
5819 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
5820 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
5821 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
5822 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5823 { PIN_MLB_REF, 4, 3 }, /* MLB_REF */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5824 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
5825 } },
5826 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5827 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
5828 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
5829 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
5830 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
5831 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
5832 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
5833 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
5834 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
5835 } },
5836 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5837 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
5838 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
5839 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
5840 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
5841 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
5842 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
5843 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
5844 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
5845 } },
5846 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5847 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
5848 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
5849 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
5850 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
5851 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
5852 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
5853 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
5854 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
5855 } },
5856 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5857 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
5858 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
5859 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
5860 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
5861 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5862 { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30/USB2_CH3_PWEN */
5863 { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31/USB2_CH3_OVC */
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5864 } },
Marek Vasut14dfdd62023-09-17 16:08:40 +0200[diff] [blame]5865 { /* sentinel */ }
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5866};
5867
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5868enum ioctrl_regs {
5869 POCCTRL,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5870 TDSELCTRL,
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5871};
5872
5873static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5874 [POCCTRL] = { 0xe6060380, },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5875 [TDSELCTRL] = { 0xe60603c0, },
Marek Vasut14dfdd62023-09-17 16:08:40 +0200[diff] [blame]5876 { /* sentinel */ }
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5877};
5878
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]5879static int r8a77951_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5880{
5881 int bit = -EINVAL;
5882
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5883 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]5884
5885 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5886 bit = pin & 0x1f;
5887
5888 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5889 bit = (pin & 0x1f) + 12;
5890
5891 return bit;
5892}
5893
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5894static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5895 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5896 [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */
5897 [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */
5898 [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */
5899 [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */
5900 [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */
5901 [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */
5902 [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */
5903 [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */
5904 [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */
5905 [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */
5906 [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */
5907 [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */
5908 [12] = PIN_RPC_INT_N, /* RPC_INT# */
5909 [13] = PIN_RPC_WP_N, /* RPC_WP# */
5910 [14] = PIN_RPC_RESET_N, /* RPC_RESET# */
5911 [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */
5912 [16] = PIN_AVB_RXC, /* AVB_RXC */
5913 [17] = PIN_AVB_RD0, /* AVB_RD0 */
5914 [18] = PIN_AVB_RD1, /* AVB_RD1 */
5915 [19] = PIN_AVB_RD2, /* AVB_RD2 */
5916 [20] = PIN_AVB_RD3, /* AVB_RD3 */
5917 [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
5918 [22] = PIN_AVB_TXC, /* AVB_TXC */
5919 [23] = PIN_AVB_TD0, /* AVB_TD0 */
5920 [24] = PIN_AVB_TD1, /* AVB_TD1 */
5921 [25] = PIN_AVB_TD2, /* AVB_TD2 */
5922 [26] = PIN_AVB_TD3, /* AVB_TD3 */
5923 [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */
5924 [28] = PIN_AVB_MDIO, /* AVB_MDIO */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5925 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
5926 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
5927 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
5928 } },
5929 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5930 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
5931 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
5932 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
5933 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
5934 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
5935 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
5936 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
5937 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
5938 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
5939 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
5940 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
5941 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
5942 [12] = RCAR_GP_PIN(1, 0), /* A0 */
5943 [13] = RCAR_GP_PIN(1, 1), /* A1 */
5944 [14] = RCAR_GP_PIN(1, 2), /* A2 */
5945 [15] = RCAR_GP_PIN(1, 3), /* A3 */
5946 [16] = RCAR_GP_PIN(1, 4), /* A4 */
5947 [17] = RCAR_GP_PIN(1, 5), /* A5 */
5948 [18] = RCAR_GP_PIN(1, 6), /* A6 */
5949 [19] = RCAR_GP_PIN(1, 7), /* A7 */
5950 [20] = RCAR_GP_PIN(1, 8), /* A8 */
5951 [21] = RCAR_GP_PIN(1, 9), /* A9 */
5952 [22] = RCAR_GP_PIN(1, 10), /* A10 */
5953 [23] = RCAR_GP_PIN(1, 11), /* A11 */
5954 [24] = RCAR_GP_PIN(1, 12), /* A12 */
5955 [25] = RCAR_GP_PIN(1, 13), /* A13 */
5956 [26] = RCAR_GP_PIN(1, 14), /* A14 */
5957 [27] = RCAR_GP_PIN(1, 15), /* A15 */
5958 [28] = RCAR_GP_PIN(1, 16), /* A16 */
5959 [29] = RCAR_GP_PIN(1, 17), /* A17 */
5960 [30] = RCAR_GP_PIN(1, 18), /* A18 */
5961 [31] = RCAR_GP_PIN(1, 19), /* A19 */
5962 } },
5963 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5964 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
5965 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
5966 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
5967 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
5968 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
5969 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
5970 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
5971 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
5972 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5973 [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5974 [10] = RCAR_GP_PIN(0, 0), /* D0 */
5975 [11] = RCAR_GP_PIN(0, 1), /* D1 */
5976 [12] = RCAR_GP_PIN(0, 2), /* D2 */
5977 [13] = RCAR_GP_PIN(0, 3), /* D3 */
5978 [14] = RCAR_GP_PIN(0, 4), /* D4 */
5979 [15] = RCAR_GP_PIN(0, 5), /* D5 */
5980 [16] = RCAR_GP_PIN(0, 6), /* D6 */
5981 [17] = RCAR_GP_PIN(0, 7), /* D7 */
5982 [18] = RCAR_GP_PIN(0, 8), /* D8 */
5983 [19] = RCAR_GP_PIN(0, 9), /* D9 */
5984 [20] = RCAR_GP_PIN(0, 10), /* D10 */
5985 [21] = RCAR_GP_PIN(0, 11), /* D11 */
5986 [22] = RCAR_GP_PIN(0, 12), /* D12 */
5987 [23] = RCAR_GP_PIN(0, 13), /* D13 */
5988 [24] = RCAR_GP_PIN(0, 14), /* D14 */
5989 [25] = RCAR_GP_PIN(0, 15), /* D15 */
5990 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
5991 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5992 [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
5993 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5994 [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
5995 [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]5996 } },
5997 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5998 [ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */
5999 [ 1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */
6000 [ 2] = PIN_FSCLKST_N, /* FSCLKST# */
6001 [ 3] = PIN_EXTALR, /* EXTALR*/
6002 [ 4] = PIN_TRST_N, /* TRST# */
6003 [ 5] = PIN_TCK, /* TCK */
6004 [ 6] = PIN_TMS, /* TMS */
6005 [ 7] = PIN_TDI, /* TDI */
6006 [ 8] = SH_PFC_PIN_NONE,
6007 [ 9] = PIN_ASEBRK, /* ASEBRK */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6008 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
6009 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
6010 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
6011 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
6012 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
6013 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
6014 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
6015 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
6016 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
6017 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
6018 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
6019 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
6020 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
6021 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
6022 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
6023 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
6024 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
6025 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
6026 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
6027 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
6028 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
6029 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
6030 } },
6031 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
6032 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
6033 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
6034 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
6035 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
6036 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
6037 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
6038 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
6039 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
6040 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
6041 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
6042 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
6043 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
6044 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
6045 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
6046 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
6047 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
6048 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
6049 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
6050 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
6051 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
6052 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
6053 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
6054 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
6055 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
6056 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
6057 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
6058 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
6059 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
6060 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
6061 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
6062 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
6063 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
6064 } },
6065 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
6066 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
6067 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
6068 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
6069 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
6070 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
6071 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]6072 [ 6] = PIN_MLB_REF, /* MLB_REF */
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6073 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
6074 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
6075 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
6076 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
6077 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
6078 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
6079 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
6080 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
6081 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
6082 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
6083 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
6084 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
6085 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
6086 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
6087 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
6088 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
6089 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
6090 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
6091 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
6092 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
6093 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
6094 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
6095 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
6096 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
6097 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
6098 } },
6099 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
6100 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
6101 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
6102 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
6103 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
6104 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
6105 [ 5] = RCAR_GP_PIN(6, 30), /* USB2_CH3_PWEN */
6106 [ 6] = RCAR_GP_PIN(6, 31), /* USB2_CH3_OVC */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]6107 [ 7] = SH_PFC_PIN_NONE,
6108 [ 8] = SH_PFC_PIN_NONE,
6109 [ 9] = SH_PFC_PIN_NONE,
6110 [10] = SH_PFC_PIN_NONE,
6111 [11] = SH_PFC_PIN_NONE,
6112 [12] = SH_PFC_PIN_NONE,
6113 [13] = SH_PFC_PIN_NONE,
6114 [14] = SH_PFC_PIN_NONE,
6115 [15] = SH_PFC_PIN_NONE,
6116 [16] = SH_PFC_PIN_NONE,
6117 [17] = SH_PFC_PIN_NONE,
6118 [18] = SH_PFC_PIN_NONE,
6119 [19] = SH_PFC_PIN_NONE,
6120 [20] = SH_PFC_PIN_NONE,
6121 [21] = SH_PFC_PIN_NONE,
6122 [22] = SH_PFC_PIN_NONE,
6123 [23] = SH_PFC_PIN_NONE,
6124 [24] = SH_PFC_PIN_NONE,
6125 [25] = SH_PFC_PIN_NONE,
6126 [26] = SH_PFC_PIN_NONE,
6127 [27] = SH_PFC_PIN_NONE,
6128 [28] = SH_PFC_PIN_NONE,
6129 [29] = SH_PFC_PIN_NONE,
6130 [30] = SH_PFC_PIN_NONE,
6131 [31] = SH_PFC_PIN_NONE,
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6132 } },
Marek Vasut14dfdd62023-09-17 16:08:40 +0200[diff] [blame]6133 { /* sentinel */ }
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6134};
6135
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]6136static const struct sh_pfc_soc_operations r8a77951_pfc_ops = {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]6137 .pin_to_pocctrl = r8a77951_pin_to_pocctrl,
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]6138 .get_bias = rcar_pinmux_get_bias,
6139 .set_bias = rcar_pinmux_set_bias,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6140};
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]6141
6142#ifdef CONFIG_PINCTRL_PFC_R8A774E1
6143const struct sh_pfc_soc_info r8a774e1_pinmux_info = {
6144 .name = "r8a774e1_pfc",
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]6145 .ops = &r8a77951_pfc_ops,
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]6146 .unlock_reg = 0xe6060000, /* PMMR */
6147
6148 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6149
6150 .pins = pinmux_pins,
6151 .nr_pins = ARRAY_SIZE(pinmux_pins),
6152 .groups = pinmux_groups.common,
6153 .nr_groups = ARRAY_SIZE(pinmux_groups.common),
6154 .functions = pinmux_functions.common,
6155 .nr_functions = ARRAY_SIZE(pinmux_functions.common),
6156
6157 .cfg_regs = pinmux_config_regs,
6158 .drive_regs = pinmux_drive_regs,
6159 .bias_regs = pinmux_bias_regs,
6160 .ioctrl_regs = pinmux_ioctrl_regs,
6161
6162 .pinmux_data = pinmux_data,
6163 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6164};
6165#endif
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6166
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]6167#ifdef CONFIG_PINCTRL_PFC_R8A77951
6168const struct sh_pfc_soc_info r8a77951_pinmux_info = {
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6169 .name = "r8a77951_pfc",
Marek Vasutc02d50a2023-01-26 21:01:40 +0100[diff] [blame]6170 .ops = &r8a77951_pfc_ops,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6171 .unlock_reg = 0xe6060000, /* PMMR */
6172
6173 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6174
6175 .pins = pinmux_pins,
6176 .nr_pins = ARRAY_SIZE(pinmux_pins),
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]6177 .groups = pinmux_groups.common,
6178 .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6179 ARRAY_SIZE(pinmux_groups.automotive),
6180 .functions = pinmux_functions.common,
6181 .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6182 ARRAY_SIZE(pinmux_functions.automotive),
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6183
6184 .cfg_regs = pinmux_config_regs,
6185 .drive_regs = pinmux_drive_regs,
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200[diff] [blame]6186 .bias_regs = pinmux_bias_regs,
6187 .ioctrl_regs = pinmux_ioctrl_regs,
Marek Vasut3066a062017-09-15 21:13:55 +0200[diff] [blame]6188
6189 .pinmux_data = pinmux_data,
6190 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6191};
Biju Das121bd002020-10-28 10:34:22 +0000[diff] [blame]6192#endif