| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| Prabhakar Kushwaha | 768e120 | 2013-09-12 11:11:28 +0530 | [diff] [blame] | 2 | /* |
| 3 | * Copyright 2013 Freescale Semiconductor, Inc. |
| Prabhakar Kushwaha | 768e120 | 2013-09-12 11:11:28 +0530 | [diff] [blame] | 4 | */ |
| 5 | #include <common.h> |
| 6 | #include <phy.h> |
| 7 | #include <fm_eth.h> |
| 8 | #include <asm/io.h> |
| 9 | #include <asm/immap_85xx.h> |
| 10 | #include <asm/fsl_serdes.h> |
| 11 | |
| 12 | phy_interface_t fman_port_enet_if(enum fm_port port) |
| 13 | { |
| Tom Rini | d5c3bf2 | 2022-10-28 20:27:12 -0400 | [diff] [blame] | 14 | ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); |
| Prabhakar Kushwaha | e70cd8d | 2014-01-27 15:55:20 +0530 | [diff] [blame] | 15 | u32 rcwsr13 = in_be32(&gur->rcwsr[13]); |
| 16 | |
| 17 | /* handle RGMII first */ |
| 18 | if ((port == FM1_DTSEC2) && |
| 19 | ((rcwsr13 & FSL_CORENET_RCWSR13_MAC2_GMII_SEL) == |
| 20 | FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT)) { |
| 21 | if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == |
| 22 | FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII) |
| 23 | return PHY_INTERFACE_MODE_RGMII; |
| 24 | else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == |
| 25 | FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII) |
| 26 | return PHY_INTERFACE_MODE_MII; |
| Prabhakar Kushwaha | e70cd8d | 2014-01-27 15:55:20 +0530 | [diff] [blame] | 27 | } |
| 28 | |
| 29 | if ((port == FM1_DTSEC4) && |
| 30 | ((rcwsr13 & FSL_CORENET_RCWSR13_MAC2_GMII_SEL) == |
| 31 | FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH)) { |
| 32 | if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == |
| 33 | FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII) |
| 34 | return PHY_INTERFACE_MODE_RGMII; |
| 35 | else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == |
| 36 | FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII) |
| 37 | return PHY_INTERFACE_MODE_MII; |
| Prabhakar Kushwaha | e70cd8d | 2014-01-27 15:55:20 +0530 | [diff] [blame] | 38 | } |
| 39 | |
| 40 | if (port == FM1_DTSEC5) { |
| 41 | if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == |
| 42 | FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII) |
| 43 | return PHY_INTERFACE_MODE_RGMII; |
| Prabhakar Kushwaha | e70cd8d | 2014-01-27 15:55:20 +0530 | [diff] [blame] | 44 | } |
| 45 | |
| 46 | switch (port) { |
| 47 | case FM1_DTSEC1: |
| 48 | case FM1_DTSEC2: |
| Codrin Ciubotariu | 045dcbf | 2015-01-12 14:08:32 +0200 | [diff] [blame] | 49 | if (is_serdes_configured(QSGMII_SW1_A + port - FM1_DTSEC1) || |
| 50 | is_serdes_configured(SGMII_SW1_MAC1 + port - FM1_DTSEC1)) |
| Prabhakar Kushwaha | e70cd8d | 2014-01-27 15:55:20 +0530 | [diff] [blame] | 51 | return PHY_INTERFACE_MODE_QSGMII; |
| 52 | case FM1_DTSEC3: |
| 53 | case FM1_DTSEC4: |
| 54 | case FM1_DTSEC5: |
| 55 | if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) |
| 56 | return PHY_INTERFACE_MODE_SGMII; |
| 57 | break; |
| 58 | default: |
| Marek Behún | 48631e4 | 2022-04-07 00:33:03 +0200 | [diff] [blame] | 59 | return PHY_INTERFACE_MODE_NA; |
| Prabhakar Kushwaha | e70cd8d | 2014-01-27 15:55:20 +0530 | [diff] [blame] | 60 | } |
| 61 | |
| Marek Behún | 48631e4 | 2022-04-07 00:33:03 +0200 | [diff] [blame] | 62 | return PHY_INTERFACE_MODE_NA; |
| Prabhakar Kushwaha | 768e120 | 2013-09-12 11:11:28 +0530 | [diff] [blame] | 63 | } |