| Paul Barker | d5e2e69 | 2023-10-16 10:25:41 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Renesas RZ/G2L family memory map tables |
| 4 | * |
| 5 | * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com> |
| 6 | * Copyright (C) 2023 Renesas Electronics Corp. |
| 7 | */ |
| 8 | |
| 9 | #include <common.h> |
| 10 | #include <asm/armv8/mmu.h> |
| 11 | #include <asm/global_data.h> |
| 12 | #include <cpu_func.h> |
| 13 | |
| 14 | #define RZG2L_NR_REGIONS 16 |
| 15 | |
| 16 | /* |
| 17 | * RZ/G2L supports up to 4 GiB RAM starting at 0x40000000, of |
| 18 | * which the first 128 MiB is reserved by TF-A. |
| 19 | */ |
| 20 | static struct mm_region rzg2l_mem_map[RZG2L_NR_REGIONS] = { |
| 21 | { |
| 22 | .virt = 0x0UL, |
| 23 | .phys = 0x0UL, |
| 24 | .size = 0x40000000UL, |
| 25 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 26 | PTE_BLOCK_NON_SHARE | |
| 27 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 28 | }, { |
| 29 | .virt = 0x40000000UL, |
| 30 | .phys = 0x40000000UL, |
| 31 | .size = 0x03F00000UL, |
| 32 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 33 | PTE_BLOCK_INNER_SHARE |
| 34 | }, { |
| 35 | .virt = 0x47E00000UL, |
| 36 | .phys = 0x47E00000UL, |
| 37 | .size = 0xF8200000UL, |
| 38 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 39 | PTE_BLOCK_INNER_SHARE |
| 40 | }, { |
| 41 | /* List terminator */ |
| 42 | 0, |
| 43 | } |
| 44 | }; |
| 45 | |
| 46 | struct mm_region *mem_map = rzg2l_mem_map; |
| 47 | |
| 48 | DECLARE_GLOBAL_DATA_PTR; |
| 49 | |
| 50 | #define debug_memmap(i, map) \ |
| 51 | debug("memmap %d: virt 0x%llx -> phys 0x%llx, size=0x%llx, attrs=0x%llx\n", \ |
| 52 | i, map[i].virt, map[i].phys, map[i].size, map[i].attrs) |
| 53 | |
| 54 | void enable_caches(void) |
| 55 | { |
| 56 | unsigned int bank, i = 0; |
| 57 | u64 start, size; |
| 58 | |
| 59 | /* Create map for register access */ |
| 60 | rzg2l_mem_map[i].virt = 0x0ULL; |
| 61 | rzg2l_mem_map[i].phys = 0x0ULL; |
| 62 | rzg2l_mem_map[i].size = 0x40000000ULL; |
| 63 | rzg2l_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 64 | PTE_BLOCK_NON_SHARE | |
| 65 | PTE_BLOCK_PXN | PTE_BLOCK_UXN; |
| 66 | debug_memmap(i, rzg2l_mem_map); |
| 67 | i++; |
| 68 | |
| 69 | /* Generate entries for DRAM in 32bit address space */ |
| 70 | for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { |
| 71 | start = gd->bd->bi_dram[bank].start; |
| 72 | size = gd->bd->bi_dram[bank].size; |
| 73 | |
| 74 | /* Skip empty DRAM banks */ |
| 75 | if (!size) |
| 76 | continue; |
| 77 | |
| 78 | /* Mark memory reserved by ATF as cacheable too. */ |
| 79 | if (start == 0x48000000) { |
| 80 | /* Unmark protection area (0x43F00000 to 0x47DFFFFF) */ |
| 81 | rzg2l_mem_map[i].virt = 0x40000000ULL; |
| 82 | rzg2l_mem_map[i].phys = 0x40000000ULL; |
| 83 | rzg2l_mem_map[i].size = 0x03F00000ULL; |
| 84 | rzg2l_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 85 | PTE_BLOCK_INNER_SHARE; |
| 86 | debug_memmap(i, rzg2l_mem_map); |
| 87 | i++; |
| 88 | |
| 89 | start = 0x47E00000ULL; |
| 90 | size += 0x00200000ULL; |
| 91 | } |
| 92 | |
| 93 | rzg2l_mem_map[i].virt = start; |
| 94 | rzg2l_mem_map[i].phys = start; |
| 95 | rzg2l_mem_map[i].size = size; |
| 96 | rzg2l_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 97 | PTE_BLOCK_INNER_SHARE; |
| 98 | debug_memmap(i, rzg2l_mem_map); |
| 99 | i++; |
| 100 | } |
| 101 | |
| 102 | /* Zero out the remaining regions. */ |
| 103 | for (; i < RZG2L_NR_REGIONS; i++) { |
| 104 | rzg2l_mem_map[i].virt = 0; |
| 105 | rzg2l_mem_map[i].phys = 0; |
| 106 | rzg2l_mem_map[i].size = 0; |
| 107 | rzg2l_mem_map[i].attrs = 0; |
| 108 | debug_memmap(i, rzg2l_mem_map); |
| 109 | } |
| 110 | |
| 111 | if (!icache_status()) |
| 112 | icache_enable(); |
| 113 | |
| 114 | dcache_enable(); |
| 115 | } |
| 116 | |
| 117 | int dram_init(void) |
| 118 | { |
| 119 | return fdtdec_setup_mem_size_base(); |
| 120 | } |
| 121 | |
| 122 | int dram_init_banksize(void) |
| 123 | { |
| 124 | fdtdec_setup_memory_banksize(); |
| 125 | |
| 126 | return 0; |
| 127 | } |