blob: 084f8f5b669931a784dbd9e7d5e5ec5ac9e86fd4 [file] [log] [blame]
Aswath Govindraju0e548f02022-01-25 20:56:40 +05301// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for J721S2 SoC Family Main Domain peripherals
4 *
5 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
Manorit Chawdhry377cc642023-10-06 10:15:58 +05308#include <dt-bindings/phy/phy-cadence.h>
9#include <dt-bindings/phy/phy-ti.h>
10
11/ {
12 serdes_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
16 };
17};
18
Aswath Govindraju0e548f02022-01-25 20:56:40 +053019&cbass_main {
20 msmc_ram: sram@70000000 {
21 compatible = "mmio-sram";
22 reg = <0x0 0x70000000 0x0 0x400000>;
23 #address-cells = <1>;
24 #size-cells = <1>;
25 ranges = <0x0 0x0 0x70000000 0x400000>;
26
27 atf-sram@0 {
28 reg = <0x0 0x20000>;
29 };
30
31 tifs-sram@1f0000 {
32 reg = <0x1f0000 0x10000>;
33 };
34
35 l3cache-sram@200000 {
36 reg = <0x200000 0x200000>;
37 };
38 };
39
Manorit Chawdhry377cc642023-10-06 10:15:58 +053040 scm_conf: syscon@104000 {
41 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
42 reg = <0x00 0x00104000 0x00 0x18000>;
43 #address-cells = <1>;
44 #size-cells = <1>;
45 ranges = <0x00 0x00 0x00104000 0x18000>;
46
47 usb_serdes_mux: mux-controller@0 {
48 compatible = "mmio-mux";
49 reg = <0x0 0x4>;
50 #mux-control-cells = <1>;
51 mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
52 };
53
54 phy_gmii_sel_cpsw: phy@34 {
55 compatible = "ti,am654-phy-gmii-sel";
56 reg = <0x34 0x4>;
57 #phy-cells = <1>;
58 };
59
60 serdes_ln_ctrl: mux-controller@80 {
61 compatible = "mmio-mux";
62 reg = <0x80 0x10>;
63 #mux-control-cells = <1>;
64 mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */
65 <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */
66 };
67
68 ehrpwm_tbclk: clock-controller@140 {
69 compatible = "ti,am654-ehrpwm-tbclk";
70 reg = <0x140 0x18>;
71 #clock-cells = <1>;
72 };
73 };
74
75 main_ehrpwm0: pwm@3000000 {
76 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
77 #pwm-cells = <3>;
78 reg = <0x00 0x3000000 0x00 0x100>;
79 power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
80 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 160 0>;
81 clock-names = "tbclk", "fck";
82 status = "disabled";
83 };
84
85 main_ehrpwm1: pwm@3010000 {
86 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
87 #pwm-cells = <3>;
88 reg = <0x00 0x3010000 0x00 0x100>;
89 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
90 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 161 0>;
91 clock-names = "tbclk", "fck";
92 status = "disabled";
93 };
94
95 main_ehrpwm2: pwm@3020000 {
96 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
97 #pwm-cells = <3>;
98 reg = <0x00 0x3020000 0x00 0x100>;
99 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
100 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 162 0>;
101 clock-names = "tbclk", "fck";
102 status = "disabled";
103 };
104
105 main_ehrpwm3: pwm@3030000 {
106 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
107 #pwm-cells = <3>;
108 reg = <0x00 0x3030000 0x00 0x100>;
109 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
110 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 163 0>;
111 clock-names = "tbclk", "fck";
112 status = "disabled";
113 };
114
115 main_ehrpwm4: pwm@3040000 {
116 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
117 #pwm-cells = <3>;
118 reg = <0x00 0x3040000 0x00 0x100>;
119 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
120 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 164 0>;
121 clock-names = "tbclk", "fck";
122 status = "disabled";
123 };
124
125 main_ehrpwm5: pwm@3050000 {
126 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
127 #pwm-cells = <3>;
128 reg = <0x00 0x3050000 0x00 0x100>;
129 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
130 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 165 0>;
131 clock-names = "tbclk", "fck";
132 status = "disabled";
133 };
134
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530135 gic500: interrupt-controller@1800000 {
136 compatible = "arm,gic-v3";
137 #address-cells = <2>;
138 #size-cells = <2>;
139 ranges;
140 #interrupt-cells = <3>;
141 interrupt-controller;
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530142 reg = <0x00 0x01800000 0x00 0x100000>, /* GICD */
143 <0x00 0x01900000 0x00 0x100000>, /* GICR */
144 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
145 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
146 <0x00 0x6f020000 0x00 0x2000>; /* GICV */
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530147
148 /* vcpumntirq: virtual CPU interface maintenance interrupt */
149 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
150
151 gic_its: msi-controller@1820000 {
152 compatible = "arm,gic-v3-its";
153 reg = <0x00 0x01820000 0x00 0x10000>;
154 socionext,synquacer-pre-its = <0x1000000 0x400000>;
155 msi-controller;
156 #msi-cells = <1>;
157 };
158 };
159
160 main_gpio_intr: interrupt-controller@a00000 {
161 compatible = "ti,sci-intr";
162 reg = <0x00 0x00a00000 0x00 0x800>;
163 ti,intr-trigger-type = <1>;
164 interrupt-controller;
165 interrupt-parent = <&gic500>;
166 #interrupt-cells = <1>;
167 ti,sci = <&sms>;
168 ti,sci-dev-id = <148>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530169 ti,interrupt-ranges = <8 392 56>;
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530170 };
171
172 main_pmx0: pinctrl@11c000 {
173 compatible = "pinctrl-single";
174 /* Proxy 0 addressing */
175 reg = <0x0 0x11c000 0x0 0x120>;
176 #pinctrl-cells = <1>;
177 pinctrl-single,register-width = <32>;
178 pinctrl-single,function-mask = <0xffffffff>;
179 };
180
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530181 /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
182 main_timerio_input: pinctrl@104200 {
183 compatible = "pinctrl-single";
184 reg = <0x00 0x104200 0x00 0x50>;
185 #pinctrl-cells = <1>;
186 pinctrl-single,register-width = <32>;
187 pinctrl-single,function-mask = <0x00000007>;
188 };
189
190 /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
191 main_timerio_output: pinctrl@104280 {
192 compatible = "pinctrl-single";
193 reg = <0x00 0x104280 0x00 0x20>;
194 #pinctrl-cells = <1>;
195 pinctrl-single,register-width = <32>;
196 pinctrl-single,function-mask = <0x0000001f>;
197 };
198
199 main_crypto: crypto@4e00000 {
200 compatible = "ti,j721e-sa2ul";
201 reg = <0x00 0x04e00000 0x00 0x1200>;
202 power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
203 #address-cells = <2>;
204 #size-cells = <2>;
205 ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>;
206
207 dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>,
208 <&main_udmap 0x4a41>;
209 dma-names = "tx", "rx1", "rx2";
210
211 rng: rng@4e10000 {
212 compatible = "inside-secure,safexcel-eip76";
213 reg = <0x00 0x04e10000 0x00 0x7d>;
214 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
215 };
216 };
217
218 main_timer0: timer@2400000 {
219 compatible = "ti,am654-timer";
220 reg = <0x00 0x2400000 0x00 0x400>;
221 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&k3_clks 63 1>;
223 clock-names = "fck";
224 assigned-clocks = <&k3_clks 63 1>;
225 assigned-clock-parents = <&k3_clks 63 2>;
226 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
227 ti,timer-pwm;
228 };
229
230 main_timer1: timer@2410000 {
231 compatible = "ti,am654-timer";
232 reg = <0x00 0x2410000 0x00 0x400>;
233 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&k3_clks 64 1>;
235 clock-names = "fck";
236 assigned-clocks = <&k3_clks 64 1>;
237 assigned-clock-parents = <&k3_clks 64 2>;
238 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
239 ti,timer-pwm;
240 };
241
242 main_timer2: timer@2420000 {
243 compatible = "ti,am654-timer";
244 reg = <0x00 0x2420000 0x00 0x400>;
245 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
246 clocks = <&k3_clks 65 1>;
247 clock-names = "fck";
248 assigned-clocks = <&k3_clks 65 1>;
249 assigned-clock-parents = <&k3_clks 65 2>;
250 power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
251 ti,timer-pwm;
252 };
253
254 main_timer3: timer@2430000 {
255 compatible = "ti,am654-timer";
256 reg = <0x00 0x2430000 0x00 0x400>;
257 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
258 clocks = <&k3_clks 66 1>;
259 clock-names = "fck";
260 assigned-clocks = <&k3_clks 66 1>;
261 assigned-clock-parents = <&k3_clks 66 2>;
262 power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>;
263 ti,timer-pwm;
264 };
265
266 main_timer4: timer@2440000 {
267 compatible = "ti,am654-timer";
268 reg = <0x00 0x2440000 0x00 0x400>;
269 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&k3_clks 67 1>;
271 clock-names = "fck";
272 assigned-clocks = <&k3_clks 67 1>;
273 assigned-clock-parents = <&k3_clks 67 2>;
274 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
275 ti,timer-pwm;
276 };
277
278 main_timer5: timer@2450000 {
279 compatible = "ti,am654-timer";
280 reg = <0x00 0x2450000 0x00 0x400>;
281 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
282 clocks = <&k3_clks 68 1>;
283 clock-names = "fck";
284 assigned-clocks = <&k3_clks 68 1>;
285 assigned-clock-parents = <&k3_clks 68 2>;
286 power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>;
287 ti,timer-pwm;
288 };
289
290 main_timer6: timer@2460000 {
291 compatible = "ti,am654-timer";
292 reg = <0x00 0x2460000 0x00 0x400>;
293 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
294 clocks = <&k3_clks 69 1>;
295 clock-names = "fck";
296 assigned-clocks = <&k3_clks 69 1>;
297 assigned-clock-parents = <&k3_clks 69 2>;
298 power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>;
299 ti,timer-pwm;
300 };
301
302 main_timer7: timer@2470000 {
303 compatible = "ti,am654-timer";
304 reg = <0x00 0x2470000 0x00 0x400>;
305 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&k3_clks 70 1>;
307 clock-names = "fck";
308 assigned-clocks = <&k3_clks 70 1>;
309 assigned-clock-parents = <&k3_clks 70 2>;
310 power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>;
311 ti,timer-pwm;
312 };
313
314 main_timer8: timer@2480000 {
315 compatible = "ti,am654-timer";
316 reg = <0x00 0x2480000 0x00 0x400>;
317 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&k3_clks 71 1>;
319 clock-names = "fck";
320 assigned-clocks = <&k3_clks 71 1>;
321 assigned-clock-parents = <&k3_clks 71 2>;
322 power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>;
323 ti,timer-pwm;
324 };
325
326 main_timer9: timer@2490000 {
327 compatible = "ti,am654-timer";
328 reg = <0x00 0x2490000 0x00 0x400>;
329 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
330 clocks = <&k3_clks 72 1>;
331 clock-names = "fck";
332 assigned-clocks = <&k3_clks 72 1>;
333 assigned-clock-parents = <&k3_clks 72 2>;
334 power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>;
335 ti,timer-pwm;
336 };
337
338 main_timer10: timer@24a0000 {
339 compatible = "ti,am654-timer";
340 reg = <0x00 0x24a0000 0x00 0x400>;
341 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
342 clocks = <&k3_clks 73 1>;
343 clock-names = "fck";
344 assigned-clocks = <&k3_clks 73 1>;
345 assigned-clock-parents = <&k3_clks 73 2>;
346 power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>;
347 ti,timer-pwm;
348 };
349
350 main_timer11: timer@24b0000 {
351 compatible = "ti,am654-timer";
352 reg = <0x00 0x24b0000 0x00 0x400>;
353 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
354 clocks = <&k3_clks 74 1>;
355 clock-names = "fck";
356 assigned-clocks = <&k3_clks 74 1>;
357 assigned-clock-parents = <&k3_clks 74 2>;
358 power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>;
359 ti,timer-pwm;
360 };
361
362 main_timer12: timer@24c0000 {
363 compatible = "ti,am654-timer";
364 reg = <0x00 0x24c0000 0x00 0x400>;
365 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
366 clocks = <&k3_clks 75 1>;
367 clock-names = "fck";
368 assigned-clocks = <&k3_clks 75 1>;
369 assigned-clock-parents = <&k3_clks 75 2>;
370 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
371 ti,timer-pwm;
372 };
373
374 main_timer13: timer@24d0000 {
375 compatible = "ti,am654-timer";
376 reg = <0x00 0x24d0000 0x00 0x400>;
377 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
378 clocks = <&k3_clks 76 1>;
379 clock-names = "fck";
380 assigned-clocks = <&k3_clks 76 1>;
381 assigned-clock-parents = <&k3_clks 76 2>;
382 power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>;
383 ti,timer-pwm;
384 };
385
386 main_timer14: timer@24e0000 {
387 compatible = "ti,am654-timer";
388 reg = <0x00 0x24e0000 0x00 0x400>;
389 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
390 clocks = <&k3_clks 77 1>;
391 clock-names = "fck";
392 assigned-clocks = <&k3_clks 77 1>;
393 assigned-clock-parents = <&k3_clks 77 2>;
394 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
395 ti,timer-pwm;
396 };
397
398 main_timer15: timer@24f0000 {
399 compatible = "ti,am654-timer";
400 reg = <0x00 0x24f0000 0x00 0x400>;
401 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
402 clocks = <&k3_clks 78 1>;
403 clock-names = "fck";
404 assigned-clocks = <&k3_clks 78 1>;
405 assigned-clock-parents = <&k3_clks 78 2>;
406 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
407 ti,timer-pwm;
408 };
409
410 main_timer16: timer@2500000 {
411 compatible = "ti,am654-timer";
412 reg = <0x00 0x2500000 0x00 0x400>;
413 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
414 clocks = <&k3_clks 79 1>;
415 clock-names = "fck";
416 assigned-clocks = <&k3_clks 79 1>;
417 assigned-clock-parents = <&k3_clks 79 2>;
418 power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
419 ti,timer-pwm;
420 };
421
422 main_timer17: timer@2510000 {
423 compatible = "ti,am654-timer";
424 reg = <0x00 0x2510000 0x00 0x400>;
425 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
426 clocks = <&k3_clks 80 1>;
427 clock-names = "fck";
428 assigned-clocks = <&k3_clks 80 1>;
429 assigned-clock-parents = <&k3_clks 80 2>;
430 power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
431 ti,timer-pwm;
432 };
433
434 main_timer18: timer@2520000 {
435 compatible = "ti,am654-timer";
436 reg = <0x00 0x2520000 0x00 0x400>;
437 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
438 clocks = <&k3_clks 81 1>;
439 clock-names = "fck";
440 assigned-clocks = <&k3_clks 81 1>;
441 assigned-clock-parents = <&k3_clks 81 2>;
442 power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>;
443 ti,timer-pwm;
444 };
445
446 main_timer19: timer@2530000 {
447 compatible = "ti,am654-timer";
448 reg = <0x00 0x2530000 0x00 0x400>;
449 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
450 clocks = <&k3_clks 82 1>;
451 clock-names = "fck";
452 assigned-clocks = <&k3_clks 82 1>;
453 assigned-clock-parents = <&k3_clks 82 2>;
454 power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>;
455 ti,timer-pwm;
456 };
457
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530458 main_uart0: serial@2800000 {
459 compatible = "ti,j721e-uart", "ti,am654-uart";
460 reg = <0x00 0x02800000 0x00 0x200>;
461 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
462 current-speed = <115200>;
463 clocks = <&k3_clks 146 3>;
464 clock-names = "fclk";
465 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530466 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530467 };
468
469 main_uart1: serial@2810000 {
470 compatible = "ti,j721e-uart", "ti,am654-uart";
471 reg = <0x00 0x02810000 0x00 0x200>;
472 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
473 current-speed = <115200>;
474 clocks = <&k3_clks 350 3>;
475 clock-names = "fclk";
476 power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530477 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530478 };
479
480 main_uart2: serial@2820000 {
481 compatible = "ti,j721e-uart", "ti,am654-uart";
482 reg = <0x00 0x02820000 0x00 0x200>;
483 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
484 current-speed = <115200>;
485 clocks = <&k3_clks 351 3>;
486 clock-names = "fclk";
487 power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530488 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530489 };
490
491 main_uart3: serial@2830000 {
492 compatible = "ti,j721e-uart", "ti,am654-uart";
493 reg = <0x00 0x02830000 0x00 0x200>;
494 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
495 current-speed = <115200>;
496 clocks = <&k3_clks 352 3>;
497 clock-names = "fclk";
498 power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530499 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530500 };
501
502 main_uart4: serial@2840000 {
503 compatible = "ti,j721e-uart", "ti,am654-uart";
504 reg = <0x00 0x02840000 0x00 0x200>;
505 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
506 current-speed = <115200>;
507 clocks = <&k3_clks 353 3>;
508 clock-names = "fclk";
509 power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530510 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530511 };
512
513 main_uart5: serial@2850000 {
514 compatible = "ti,j721e-uart", "ti,am654-uart";
515 reg = <0x00 0x02850000 0x00 0x200>;
516 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
517 current-speed = <115200>;
518 clocks = <&k3_clks 354 3>;
519 clock-names = "fclk";
520 power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530521 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530522 };
523
524 main_uart6: serial@2860000 {
525 compatible = "ti,j721e-uart", "ti,am654-uart";
526 reg = <0x00 0x02860000 0x00 0x200>;
527 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
528 current-speed = <115200>;
529 clocks = <&k3_clks 355 3>;
530 clock-names = "fclk";
531 power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530532 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530533 };
534
535 main_uart7: serial@2870000 {
536 compatible = "ti,j721e-uart", "ti,am654-uart";
537 reg = <0x00 0x02870000 0x00 0x200>;
538 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
539 current-speed = <115200>;
540 clocks = <&k3_clks 356 3>;
541 clock-names = "fclk";
542 power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530543 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530544 };
545
546 main_uart8: serial@2880000 {
547 compatible = "ti,j721e-uart", "ti,am654-uart";
548 reg = <0x00 0x02880000 0x00 0x200>;
549 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
550 current-speed = <115200>;
551 clocks = <&k3_clks 357 3>;
552 clock-names = "fclk";
553 power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530554 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530555 };
556
557 main_uart9: serial@2890000 {
558 compatible = "ti,j721e-uart", "ti,am654-uart";
559 reg = <0x00 0x02890000 0x00 0x200>;
560 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
561 current-speed = <115200>;
562 clocks = <&k3_clks 358 3>;
563 clock-names = "fclk";
564 power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530565 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530566 };
567
568 main_gpio0: gpio@600000 {
569 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
570 reg = <0x00 0x00600000 0x00 0x100>;
571 gpio-controller;
572 #gpio-cells = <2>;
573 interrupt-parent = <&main_gpio_intr>;
574 interrupts = <145>, <146>, <147>, <148>, <149>;
575 interrupt-controller;
576 #interrupt-cells = <2>;
577 ti,ngpio = <66>;
578 ti,davinci-gpio-unbanked = <0>;
579 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
580 clocks = <&k3_clks 111 0>;
581 clock-names = "gpio";
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530582 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530583 };
584
585 main_gpio2: gpio@610000 {
586 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
587 reg = <0x00 0x00610000 0x00 0x100>;
588 gpio-controller;
589 #gpio-cells = <2>;
590 interrupt-parent = <&main_gpio_intr>;
591 interrupts = <154>, <155>, <156>, <157>, <158>;
592 interrupt-controller;
593 #interrupt-cells = <2>;
594 ti,ngpio = <66>;
595 ti,davinci-gpio-unbanked = <0>;
596 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
597 clocks = <&k3_clks 112 0>;
598 clock-names = "gpio";
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530599 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530600 };
601
602 main_gpio4: gpio@620000 {
603 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
604 reg = <0x00 0x00620000 0x00 0x100>;
605 gpio-controller;
606 #gpio-cells = <2>;
607 interrupt-parent = <&main_gpio_intr>;
608 interrupts = <163>, <164>, <165>, <166>, <167>;
609 interrupt-controller;
610 #interrupt-cells = <2>;
611 ti,ngpio = <66>;
612 ti,davinci-gpio-unbanked = <0>;
613 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
614 clocks = <&k3_clks 113 0>;
615 clock-names = "gpio";
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530616 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530617 };
618
619 main_gpio6: gpio@630000 {
620 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
621 reg = <0x00 0x00630000 0x00 0x100>;
622 gpio-controller;
623 #gpio-cells = <2>;
624 interrupt-parent = <&main_gpio_intr>;
625 interrupts = <172>, <173>, <174>, <175>, <176>;
626 interrupt-controller;
627 #interrupt-cells = <2>;
628 ti,ngpio = <66>;
629 ti,davinci-gpio-unbanked = <0>;
630 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
631 clocks = <&k3_clks 114 0>;
632 clock-names = "gpio";
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530633 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530634 };
635
636 main_i2c0: i2c@2000000 {
637 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
638 reg = <0x00 0x02000000 0x00 0x100>;
639 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
640 #address-cells = <1>;
641 #size-cells = <0>;
642 clocks = <&k3_clks 214 1>;
643 clock-names = "fck";
644 power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>;
645 };
646
647 main_i2c1: i2c@2010000 {
648 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
649 reg = <0x00 0x02010000 0x00 0x100>;
650 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
651 #address-cells = <1>;
652 #size-cells = <0>;
653 clocks = <&k3_clks 215 1>;
654 clock-names = "fck";
655 power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530656 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530657 };
658
659 main_i2c2: i2c@2020000 {
660 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
661 reg = <0x00 0x02020000 0x00 0x100>;
662 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
663 #address-cells = <1>;
664 #size-cells = <0>;
665 clocks = <&k3_clks 216 1>;
666 clock-names = "fck";
667 power-domains = <&k3_pds 216 TI_SCI_PD_EXCLUSIVE>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530668 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530669 };
670
671 main_i2c3: i2c@2030000 {
672 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
673 reg = <0x00 0x02030000 0x00 0x100>;
674 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
675 #address-cells = <1>;
676 #size-cells = <0>;
677 clocks = <&k3_clks 217 1>;
678 clock-names = "fck";
679 power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530680 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530681 };
682
683 main_i2c4: i2c@2040000 {
684 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
685 reg = <0x00 0x02040000 0x00 0x100>;
686 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
687 #address-cells = <1>;
688 #size-cells = <0>;
689 clocks = <&k3_clks 218 1>;
690 clock-names = "fck";
691 power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530692 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530693 };
694
695 main_i2c5: i2c@2050000 {
696 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
697 reg = <0x00 0x02050000 0x00 0x100>;
698 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
699 #address-cells = <1>;
700 #size-cells = <0>;
701 clocks = <&k3_clks 219 1>;
702 clock-names = "fck";
703 power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530704 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530705 };
706
707 main_i2c6: i2c@2060000 {
708 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
709 reg = <0x00 0x02060000 0x00 0x100>;
710 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
711 #address-cells = <1>;
712 #size-cells = <0>;
713 clocks = <&k3_clks 220 1>;
714 clock-names = "fck";
715 power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530716 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530717 };
718
719 main_sdhci0: mmc@4f80000 {
720 compatible = "ti,j721e-sdhci-8bit";
721 reg = <0x00 0x04f80000 0x00 0x1000>,
722 <0x00 0x04f88000 0x00 0x400>;
723 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
724 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
725 clocks = <&k3_clks 98 7>, <&k3_clks 98 1>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530726 clock-names = "clk_ahb", "clk_xin";
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530727 assigned-clocks = <&k3_clks 98 1>;
728 assigned-clock-parents = <&k3_clks 98 2>;
729 bus-width = <8>;
730 ti,otap-del-sel-legacy = <0x0>;
731 ti,otap-del-sel-mmc-hs = <0x0>;
732 ti,otap-del-sel-ddr52 = <0x6>;
733 ti,otap-del-sel-hs200 = <0x8>;
734 ti,otap-del-sel-hs400 = <0x5>;
735 ti,itap-del-sel-legacy = <0x10>;
736 ti,itap-del-sel-mmc-hs = <0xa>;
737 ti,strobe-sel = <0x77>;
738 ti,clkbuf-sel = <0x7>;
739 ti,trm-icp = <0x8>;
740 mmc-ddr-1_8v;
741 mmc-hs200-1_8v;
742 mmc-hs400-1_8v;
743 dma-coherent;
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530744 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530745 };
746
747 main_sdhci1: mmc@4fb0000 {
748 compatible = "ti,j721e-sdhci-4bit";
749 reg = <0x00 0x04fb0000 0x00 0x1000>,
750 <0x00 0x04fb8000 0x00 0x400>;
751 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
752 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>;
753 clocks = <&k3_clks 99 8>, <&k3_clks 99 1>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530754 clock-names = "clk_ahb", "clk_xin";
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530755 assigned-clocks = <&k3_clks 99 1>;
756 assigned-clock-parents = <&k3_clks 99 2>;
757 bus-width = <4>;
758 ti,otap-del-sel-legacy = <0x0>;
759 ti,otap-del-sel-sd-hs = <0x0>;
760 ti,otap-del-sel-sdr12 = <0xf>;
761 ti,otap-del-sel-sdr25 = <0xf>;
762 ti,otap-del-sel-sdr50 = <0xc>;
763 ti,otap-del-sel-sdr104 = <0x5>;
764 ti,otap-del-sel-ddr50 = <0xc>;
765 ti,itap-del-sel-legacy = <0x0>;
766 ti,itap-del-sel-sd-hs = <0x0>;
767 ti,itap-del-sel-sdr12 = <0x0>;
768 ti,itap-del-sel-sdr25 = <0x0>;
769 ti,clkbuf-sel = <0x7>;
770 ti,trm-icp = <0x8>;
771 dma-coherent;
772 /* Masking support for SDR104 capability */
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530773 sdhci-caps-mask = <0x00000003 0x00000000>;
774 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530775 };
776
777 main_navss: bus@30000000 {
778 compatible = "simple-mfd";
779 #address-cells = <2>;
780 #size-cells = <2>;
781 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
782 ti,sci-dev-id = <224>;
783 dma-coherent;
784 dma-ranges;
785
786 main_navss_intr: interrupt-controller@310e0000 {
787 compatible = "ti,sci-intr";
788 reg = <0x00 0x310e0000 0x00 0x4000>;
789 ti,intr-trigger-type = <4>;
790 interrupt-controller;
791 interrupt-parent = <&gic500>;
792 #interrupt-cells = <1>;
793 ti,sci = <&sms>;
794 ti,sci-dev-id = <227>;
795 ti,interrupt-ranges = <0 64 64>,
796 <64 448 64>,
797 <128 672 64>;
798 };
799
800 main_udmass_inta: msi-controller@33d00000 {
801 compatible = "ti,sci-inta";
802 reg = <0x00 0x33d00000 0x00 0x100000>;
803 interrupt-controller;
804 #interrupt-cells = <0>;
805 interrupt-parent = <&main_navss_intr>;
806 msi-controller;
807 ti,sci = <&sms>;
808 ti,sci-dev-id = <265>;
809 ti,interrupt-ranges = <0 0 256>;
810 };
811
812 secure_proxy_main: mailbox@32c00000 {
813 compatible = "ti,am654-secure-proxy";
814 #mbox-cells = <1>;
815 reg-names = "target_data", "rt", "scfg";
816 reg = <0x00 0x32c00000 0x00 0x100000>,
817 <0x00 0x32400000 0x00 0x100000>,
818 <0x00 0x32800000 0x00 0x100000>;
819 interrupt-names = "rx_011";
820 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
821 };
822
823 hwspinlock: spinlock@30e00000 {
824 compatible = "ti,am654-hwspinlock";
825 reg = <0x00 0x30e00000 0x00 0x1000>;
826 #hwlock-cells = <1>;
827 };
828
829 mailbox0_cluster0: mailbox@31f80000 {
830 compatible = "ti,am654-mailbox";
831 reg = <0x00 0x31f80000 0x00 0x200>;
832 #mbox-cells = <1>;
833 ti,mbox-num-users = <4>;
834 ti,mbox-num-fifos = <16>;
835 interrupt-parent = <&main_navss_intr>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530836 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530837 };
838
839 mailbox0_cluster1: mailbox@31f81000 {
840 compatible = "ti,am654-mailbox";
841 reg = <0x00 0x31f81000 0x00 0x200>;
842 #mbox-cells = <1>;
843 ti,mbox-num-users = <4>;
844 ti,mbox-num-fifos = <16>;
845 interrupt-parent = <&main_navss_intr>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530846 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530847 };
848
849 mailbox0_cluster2: mailbox@31f82000 {
850 compatible = "ti,am654-mailbox";
851 reg = <0x00 0x31f82000 0x00 0x200>;
852 #mbox-cells = <1>;
853 ti,mbox-num-users = <4>;
854 ti,mbox-num-fifos = <16>;
855 interrupt-parent = <&main_navss_intr>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530856 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530857 };
858
859 mailbox0_cluster3: mailbox@31f83000 {
860 compatible = "ti,am654-mailbox";
861 reg = <0x00 0x31f83000 0x00 0x200>;
862 #mbox-cells = <1>;
863 ti,mbox-num-users = <4>;
864 ti,mbox-num-fifos = <16>;
865 interrupt-parent = <&main_navss_intr>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530866 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530867 };
868
869 mailbox0_cluster4: mailbox@31f84000 {
870 compatible = "ti,am654-mailbox";
871 reg = <0x00 0x31f84000 0x00 0x200>;
872 #mbox-cells = <1>;
873 ti,mbox-num-users = <4>;
874 ti,mbox-num-fifos = <16>;
875 interrupt-parent = <&main_navss_intr>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530876 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530877 };
878
879 mailbox0_cluster5: mailbox@31f85000 {
880 compatible = "ti,am654-mailbox";
881 reg = <0x00 0x31f85000 0x00 0x200>;
882 #mbox-cells = <1>;
883 ti,mbox-num-users = <4>;
884 ti,mbox-num-fifos = <16>;
885 interrupt-parent = <&main_navss_intr>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530886 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530887 };
888
889 mailbox0_cluster6: mailbox@31f86000 {
890 compatible = "ti,am654-mailbox";
891 reg = <0x00 0x31f86000 0x00 0x200>;
892 #mbox-cells = <1>;
893 ti,mbox-num-users = <4>;
894 ti,mbox-num-fifos = <16>;
895 interrupt-parent = <&main_navss_intr>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530896 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530897 };
898
899 mailbox0_cluster7: mailbox@31f87000 {
900 compatible = "ti,am654-mailbox";
901 reg = <0x00 0x31f87000 0x00 0x200>;
902 #mbox-cells = <1>;
903 ti,mbox-num-users = <4>;
904 ti,mbox-num-fifos = <16>;
905 interrupt-parent = <&main_navss_intr>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530906 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530907 };
908
909 mailbox0_cluster8: mailbox@31f88000 {
910 compatible = "ti,am654-mailbox";
911 reg = <0x00 0x31f88000 0x00 0x200>;
912 #mbox-cells = <1>;
913 ti,mbox-num-users = <4>;
914 ti,mbox-num-fifos = <16>;
915 interrupt-parent = <&main_navss_intr>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530916 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530917 };
918
919 mailbox0_cluster9: mailbox@31f89000 {
920 compatible = "ti,am654-mailbox";
921 reg = <0x00 0x31f89000 0x00 0x200>;
922 #mbox-cells = <1>;
923 ti,mbox-num-users = <4>;
924 ti,mbox-num-fifos = <16>;
925 interrupt-parent = <&main_navss_intr>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530926 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530927 };
928
929 mailbox0_cluster10: mailbox@31f8a000 {
930 compatible = "ti,am654-mailbox";
931 reg = <0x00 0x31f8a000 0x00 0x200>;
932 #mbox-cells = <1>;
933 ti,mbox-num-users = <4>;
934 ti,mbox-num-fifos = <16>;
935 interrupt-parent = <&main_navss_intr>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530936 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530937 };
938
939 mailbox0_cluster11: mailbox@31f8b000 {
940 compatible = "ti,am654-mailbox";
941 reg = <0x00 0x31f8b000 0x00 0x200>;
942 #mbox-cells = <1>;
943 ti,mbox-num-users = <4>;
944 ti,mbox-num-fifos = <16>;
945 interrupt-parent = <&main_navss_intr>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530946 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530947 };
948
949 mailbox1_cluster0: mailbox@31f90000 {
950 compatible = "ti,am654-mailbox";
951 reg = <0x00 0x31f90000 0x00 0x200>;
952 #mbox-cells = <1>;
953 ti,mbox-num-users = <4>;
954 ti,mbox-num-fifos = <16>;
955 interrupt-parent = <&main_navss_intr>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530956 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530957 };
958
959 mailbox1_cluster1: mailbox@31f91000 {
960 compatible = "ti,am654-mailbox";
961 reg = <0x00 0x31f91000 0x00 0x200>;
962 #mbox-cells = <1>;
963 ti,mbox-num-users = <4>;
964 ti,mbox-num-fifos = <16>;
965 interrupt-parent = <&main_navss_intr>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530966 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530967 };
968
969 mailbox1_cluster2: mailbox@31f92000 {
970 compatible = "ti,am654-mailbox";
971 reg = <0x00 0x31f92000 0x00 0x200>;
972 #mbox-cells = <1>;
973 ti,mbox-num-users = <4>;
974 ti,mbox-num-fifos = <16>;
975 interrupt-parent = <&main_navss_intr>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530976 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530977 };
978
979 mailbox1_cluster3: mailbox@31f93000 {
980 compatible = "ti,am654-mailbox";
981 reg = <0x00 0x31f93000 0x00 0x200>;
982 #mbox-cells = <1>;
983 ti,mbox-num-users = <4>;
984 ti,mbox-num-fifos = <16>;
985 interrupt-parent = <&main_navss_intr>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530986 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530987 };
988
989 mailbox1_cluster4: mailbox@31f94000 {
990 compatible = "ti,am654-mailbox";
991 reg = <0x00 0x31f94000 0x00 0x200>;
992 #mbox-cells = <1>;
993 ti,mbox-num-users = <4>;
994 ti,mbox-num-fifos = <16>;
995 interrupt-parent = <&main_navss_intr>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +0530996 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +0530997 };
998
999 mailbox1_cluster5: mailbox@31f95000 {
1000 compatible = "ti,am654-mailbox";
1001 reg = <0x00 0x31f95000 0x00 0x200>;
1002 #mbox-cells = <1>;
1003 ti,mbox-num-users = <4>;
1004 ti,mbox-num-fifos = <16>;
1005 interrupt-parent = <&main_navss_intr>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +05301006 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +05301007 };
1008
1009 mailbox1_cluster6: mailbox@31f96000 {
1010 compatible = "ti,am654-mailbox";
1011 reg = <0x00 0x31f96000 0x00 0x200>;
1012 #mbox-cells = <1>;
1013 ti,mbox-num-users = <4>;
1014 ti,mbox-num-fifos = <16>;
1015 interrupt-parent = <&main_navss_intr>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +05301016 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +05301017 };
1018
1019 mailbox1_cluster7: mailbox@31f97000 {
1020 compatible = "ti,am654-mailbox";
1021 reg = <0x00 0x31f97000 0x00 0x200>;
1022 #mbox-cells = <1>;
1023 ti,mbox-num-users = <4>;
1024 ti,mbox-num-fifos = <16>;
1025 interrupt-parent = <&main_navss_intr>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +05301026 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +05301027 };
1028
1029 mailbox1_cluster8: mailbox@31f98000 {
1030 compatible = "ti,am654-mailbox";
1031 reg = <0x00 0x31f98000 0x00 0x200>;
1032 #mbox-cells = <1>;
1033 ti,mbox-num-users = <4>;
1034 ti,mbox-num-fifos = <16>;
1035 interrupt-parent = <&main_navss_intr>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +05301036 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +05301037 };
1038
1039 mailbox1_cluster9: mailbox@31f99000 {
1040 compatible = "ti,am654-mailbox";
1041 reg = <0x00 0x31f99000 0x00 0x200>;
1042 #mbox-cells = <1>;
1043 ti,mbox-num-users = <4>;
1044 ti,mbox-num-fifos = <16>;
1045 interrupt-parent = <&main_navss_intr>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +05301046 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +05301047 };
1048
1049 mailbox1_cluster10: mailbox@31f9a000 {
1050 compatible = "ti,am654-mailbox";
1051 reg = <0x00 0x31f9a000 0x00 0x200>;
1052 #mbox-cells = <1>;
1053 ti,mbox-num-users = <4>;
1054 ti,mbox-num-fifos = <16>;
1055 interrupt-parent = <&main_navss_intr>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +05301056 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +05301057 };
1058
1059 mailbox1_cluster11: mailbox@31f9b000 {
1060 compatible = "ti,am654-mailbox";
1061 reg = <0x00 0x31f9b000 0x00 0x200>;
1062 #mbox-cells = <1>;
1063 ti,mbox-num-users = <4>;
1064 ti,mbox-num-fifos = <16>;
1065 interrupt-parent = <&main_navss_intr>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +05301066 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +05301067 };
1068
1069 main_ringacc: ringacc@3c000000 {
1070 compatible = "ti,am654-navss-ringacc";
1071 reg = <0x0 0x3c000000 0x0 0x400000>,
1072 <0x0 0x38000000 0x0 0x400000>,
1073 <0x0 0x31120000 0x0 0x100>,
Manorit Chawdhry377cc642023-10-06 10:15:58 +05301074 <0x0 0x33000000 0x0 0x40000>,
1075 <0x0 0x31080000 0x0 0x40000>;
1076 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
Aswath Govindraju0e548f02022-01-25 20:56:40 +05301077 ti,num-rings = <1024>;
1078 ti,sci-rm-range-gp-rings = <0x1>;
1079 ti,sci = <&sms>;
1080 ti,sci-dev-id = <259>;
1081 msi-parent = <&main_udmass_inta>;
1082 };
1083
1084 main_udmap: dma-controller@31150000 {
1085 compatible = "ti,j721e-navss-main-udmap";
1086 reg = <0x0 0x31150000 0x0 0x100>,
1087 <0x0 0x34000000 0x0 0x80000>,
1088 <0x0 0x35000000 0x0 0x200000>;
1089 reg-names = "gcfg", "rchanrt", "tchanrt";
1090 msi-parent = <&main_udmass_inta>;
1091 #dma-cells = <1>;
1092
1093 ti,sci = <&sms>;
1094 ti,sci-dev-id = <263>;
1095 ti,ringacc = <&main_ringacc>;
1096
1097 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
1098 <0x0f>, /* TX_HCHAN */
1099 <0x10>; /* TX_UHCHAN */
1100 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
1101 <0x0b>, /* RX_HCHAN */
1102 <0x0c>; /* RX_UHCHAN */
1103 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
1104 };
1105
1106 cpts@310d0000 {
1107 compatible = "ti,j721e-cpts";
1108 reg = <0x0 0x310d0000 0x0 0x400>;
1109 reg-names = "cpts";
1110 clocks = <&k3_clks 226 5>;
1111 clock-names = "cpts";
Manorit Chawdhry377cc642023-10-06 10:15:58 +05301112 assigned-clocks = <&k3_clks 226 5>; /* NAVSS0_CPTS_0_RCLK */
1113 assigned-clock-parents = <&k3_clks 226 7>; /* MAIN_0_HSDIVOUT6_CLK */
Aswath Govindraju0e548f02022-01-25 20:56:40 +05301114 interrupts-extended = <&main_navss_intr 391>;
1115 interrupt-names = "cpts";
1116 ti,cpts-periodic-outputs = <6>;
1117 ti,cpts-ext-ts-inputs = <8>;
1118 };
1119 };
1120
Manorit Chawdhry377cc642023-10-06 10:15:58 +05301121 main_cpsw: ethernet@c200000 {
1122 compatible = "ti,j721e-cpsw-nuss";
1123 reg = <0x00 0xc200000 0x00 0x200000>;
1124 reg-names = "cpsw_nuss";
1125 ranges = <0x0 0x0 0x0 0xc200000 0x0 0x200000>;
1126 #address-cells = <2>;
1127 #size-cells = <2>;
1128 dma-coherent;
1129 clocks = <&k3_clks 28 28>;
1130 clock-names = "fck";
1131 power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>;
1132
1133 dmas = <&main_udmap 0xc640>,
1134 <&main_udmap 0xc641>,
1135 <&main_udmap 0xc642>,
1136 <&main_udmap 0xc643>,
1137 <&main_udmap 0xc644>,
1138 <&main_udmap 0xc645>,
1139 <&main_udmap 0xc646>,
1140 <&main_udmap 0xc647>,
1141 <&main_udmap 0x4640>;
1142 dma-names = "tx0", "tx1", "tx2", "tx3",
1143 "tx4", "tx5", "tx6", "tx7",
1144 "rx";
1145
1146 status = "disabled";
1147
1148 ethernet-ports {
1149 #address-cells = <1>;
1150 #size-cells = <0>;
1151
1152 main_cpsw_port1: port@1 {
1153 reg = <1>;
1154 ti,mac-only;
1155 label = "port1";
1156 phys = <&phy_gmii_sel_cpsw 1>;
1157 status = "disabled";
1158 };
1159 };
1160
1161 main_cpsw_mdio: mdio@f00 {
1162 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
1163 reg = <0x00 0xf00 0x00 0x100>;
1164 #address-cells = <1>;
1165 #size-cells = <0>;
1166 clocks = <&k3_clks 28 28>;
1167 clock-names = "fck";
1168 bus_freq = <1000000>;
1169 status = "disabled";
1170 };
1171
1172 cpts@3d000 {
1173 compatible = "ti,am65-cpts";
1174 reg = <0x00 0x3d000 0x00 0x400>;
1175 clocks = <&k3_clks 28 3>;
1176 clock-names = "cpts";
1177 interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1178 interrupt-names = "cpts";
1179 ti,cpts-ext-ts-inputs = <4>;
1180 ti,cpts-periodic-outputs = <2>;
1181 };
1182 };
1183
1184 usbss0: cdns-usb@4104000 {
1185 compatible = "ti,j721e-usb";
1186 reg = <0x00 0x04104000 0x00 0x100>;
1187 clocks = <&k3_clks 360 16>, <&k3_clks 360 15>;
1188 clock-names = "ref", "lpm";
1189 assigned-clocks = <&k3_clks 360 16>; /* USB2_REFCLK */
1190 assigned-clock-parents = <&k3_clks 360 17>;
1191 power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>;
1192 #address-cells = <2>;
1193 #size-cells = <2>;
1194 ranges;
1195 dma-coherent;
1196
1197 status = "disabled"; /* Needs pinmux */
1198
1199 usb0: usb@6000000 {
1200 compatible = "cdns,usb3";
1201 reg = <0x00 0x06000000 0x00 0x10000>,
1202 <0x00 0x06010000 0x00 0x10000>,
1203 <0x00 0x06020000 0x00 0x10000>;
1204 reg-names = "otg", "xhci", "dev";
1205 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1206 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1207 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1208 interrupt-names = "host", "peripheral", "otg";
1209 maximum-speed = "super-speed";
1210 dr_mode = "otg";
1211 };
1212 };
1213
1214 serdes_wiz0: wiz@5060000 {
1215 compatible = "ti,j721s2-wiz-10g";
1216 #address-cells = <1>;
1217 #size-cells = <1>;
1218 power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>;
1219 clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>;
1220 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
1221 num-lanes = <4>;
1222 #reset-cells = <1>;
1223 #clock-cells = <1>;
1224 ranges = <0x5060000 0x0 0x5060000 0x10000>;
1225
1226 assigned-clocks = <&k3_clks 365 3>;
1227 assigned-clock-parents = <&k3_clks 365 7>;
1228
1229 serdes0: serdes@5060000 {
1230 compatible = "ti,j721e-serdes-10g";
1231 reg = <0x05060000 0x00010000>;
1232 reg-names = "torrent_phy";
1233 resets = <&serdes_wiz0 0>;
1234 reset-names = "torrent_reset";
1235 clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
1236 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
1237 clock-names = "refclk", "phy_en_refclk";
1238 assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
1239 <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
1240 <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
1241 assigned-clock-parents = <&k3_clks 365 3>,
1242 <&k3_clks 365 3>,
1243 <&k3_clks 365 3>;
1244 #address-cells = <1>;
1245 #size-cells = <0>;
1246 #clock-cells = <1>;
1247
1248 status = "disabled"; /* Needs lane config */
1249 };
1250 };
1251
1252 pcie1_rc: pcie@2910000 {
1253 compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
1254 reg = <0x00 0x02910000 0x00 0x1000>,
1255 <0x00 0x02917000 0x00 0x400>,
1256 <0x00 0x0d800000 0x00 0x800000>,
1257 <0x00 0x18000000 0x00 0x1000>;
1258 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
1259 interrupt-names = "link_state";
1260 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
1261 device_type = "pci";
1262 ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
1263 max-link-speed = <3>;
1264 num-lanes = <4>;
1265 power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
1266 clocks = <&k3_clks 276 41>;
1267 clock-names = "fck";
1268 #address-cells = <3>;
1269 #size-cells = <2>;
1270 bus-range = <0x0 0xff>;
1271 vendor-id = <0x104c>;
1272 device-id = <0xb013>;
1273 msi-map = <0x0 &gic_its 0x0 0x10000>;
1274 dma-coherent;
1275 ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
1276 <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
1277 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
1278 #interrupt-cells = <1>;
1279 interrupt-map-mask = <0 0 0 7>;
1280 interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */
1281 <0 0 0 2 &pcie1_intc 0>, /* INT B */
1282 <0 0 0 3 &pcie1_intc 0>, /* INT C */
1283 <0 0 0 4 &pcie1_intc 0>; /* INT D */
1284
1285 status = "disabled"; /* Needs gpio and serdes info */
1286
1287 pcie1_intc: interrupt-controller {
1288 interrupt-controller;
1289 #interrupt-cells = <1>;
1290 interrupt-parent = <&gic500>;
1291 interrupts = <GIC_SPI 324 IRQ_TYPE_EDGE_RISING>;
1292 };
1293 };
1294
Aswath Govindraju0e548f02022-01-25 20:56:40 +05301295 main_mcan0: can@2701000 {
1296 compatible = "bosch,m_can";
1297 reg = <0x00 0x02701000 0x00 0x200>,
1298 <0x00 0x02708000 0x00 0x8000>;
1299 reg-names = "m_can", "message_ram";
1300 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
1301 clocks = <&k3_clks 182 0>, <&k3_clks 182 1>;
1302 clock-names = "hclk", "cclk";
1303 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1304 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
1305 interrupt-names = "int0", "int1";
1306 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +05301307 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +05301308 };
1309
1310 main_mcan1: can@2711000 {
1311 compatible = "bosch,m_can";
1312 reg = <0x00 0x02711000 0x00 0x200>,
1313 <0x00 0x02718000 0x00 0x8000>;
1314 reg-names = "m_can", "message_ram";
1315 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
1316 clocks = <&k3_clks 183 0>, <&k3_clks 183 1>;
1317 clock-names = "hclk", "cclk";
1318 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
1319 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
1320 interrupt-names = "int0", "int1";
1321 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +05301322 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +05301323 };
1324
1325 main_mcan2: can@2721000 {
1326 compatible = "bosch,m_can";
1327 reg = <0x00 0x02721000 0x00 0x200>,
1328 <0x00 0x02728000 0x00 0x8000>;
1329 reg-names = "m_can", "message_ram";
1330 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
1331 clocks = <&k3_clks 184 0>, <&k3_clks 184 1>;
1332 clock-names = "hclk", "cclk";
1333 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
1334 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
1335 interrupt-names = "int0", "int1";
1336 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +05301337 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +05301338 };
1339
1340 main_mcan3: can@2731000 {
1341 compatible = "bosch,m_can";
1342 reg = <0x00 0x02731000 0x00 0x200>,
1343 <0x00 0x02738000 0x00 0x8000>;
1344 reg-names = "m_can", "message_ram";
1345 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
1346 clocks = <&k3_clks 185 0>, <&k3_clks 185 1>;
1347 clock-names = "hclk", "cclk";
1348 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
1349 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
1350 interrupt-names = "int0", "int1";
1351 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +05301352 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +05301353 };
1354
1355 main_mcan4: can@2741000 {
1356 compatible = "bosch,m_can";
1357 reg = <0x00 0x02741000 0x00 0x200>,
1358 <0x00 0x02748000 0x00 0x8000>;
1359 reg-names = "m_can", "message_ram";
1360 power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
1361 clocks = <&k3_clks 186 0>, <&k3_clks 186 1>;
1362 clock-names = "hclk", "cclk";
1363 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
1364 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
1365 interrupt-names = "int0", "int1";
1366 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +05301367 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +05301368 };
1369
1370 main_mcan5: can@2751000 {
1371 compatible = "bosch,m_can";
1372 reg = <0x00 0x02751000 0x00 0x200>,
1373 <0x00 0x02758000 0x00 0x8000>;
1374 reg-names = "m_can", "message_ram";
1375 power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
1376 clocks = <&k3_clks 187 0>, <&k3_clks 187 1>;
1377 clock-names = "hclk", "cclk";
1378 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
1379 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
1380 interrupt-names = "int0", "int1";
1381 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +05301382 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +05301383 };
1384
1385 main_mcan6: can@2761000 {
1386 compatible = "bosch,m_can";
1387 reg = <0x00 0x02761000 0x00 0x200>,
1388 <0x00 0x02768000 0x00 0x8000>;
1389 reg-names = "m_can", "message_ram";
1390 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
1391 clocks = <&k3_clks 188 0>, <&k3_clks 188 1>;
1392 clock-names = "hclk", "cclk";
1393 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1394 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
1395 interrupt-names = "int0", "int1";
1396 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +05301397 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +05301398 };
1399
1400 main_mcan7: can@2771000 {
1401 compatible = "bosch,m_can";
1402 reg = <0x00 0x02771000 0x00 0x200>,
1403 <0x00 0x02778000 0x00 0x8000>;
1404 reg-names = "m_can", "message_ram";
1405 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
1406 clocks = <&k3_clks 189 0>, <&k3_clks 189 1>;
1407 clock-names = "hclk", "cclk";
1408 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1409 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1410 interrupt-names = "int0", "int1";
1411 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +05301412 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +05301413 };
1414
1415 main_mcan8: can@2781000 {
1416 compatible = "bosch,m_can";
1417 reg = <0x00 0x02781000 0x00 0x200>,
1418 <0x00 0x02788000 0x00 0x8000>;
1419 reg-names = "m_can", "message_ram";
1420 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
1421 clocks = <&k3_clks 190 0>, <&k3_clks 190 1>;
1422 clock-names = "hclk", "cclk";
1423 interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
1424 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>;
1425 interrupt-names = "int0", "int1";
1426 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +05301427 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +05301428 };
1429
1430 main_mcan9: can@2791000 {
1431 compatible = "bosch,m_can";
1432 reg = <0x00 0x02791000 0x00 0x200>,
1433 <0x00 0x02798000 0x00 0x8000>;
1434 reg-names = "m_can", "message_ram";
1435 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
1436 clocks = <&k3_clks 191 0>, <&k3_clks 191 1>;
1437 clock-names = "hclk", "cclk";
1438 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>,
1439 <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
1440 interrupt-names = "int0", "int1";
1441 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +05301442 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +05301443 };
1444
1445 main_mcan10: can@27a1000 {
1446 compatible = "bosch,m_can";
1447 reg = <0x00 0x027a1000 0x00 0x200>,
1448 <0x00 0x027a8000 0x00 0x8000>;
1449 reg-names = "m_can", "message_ram";
1450 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
1451 clocks = <&k3_clks 192 0>, <&k3_clks 192 1>;
1452 clock-names = "hclk", "cclk";
1453 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>,
1454 <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1455 interrupt-names = "int0", "int1";
1456 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +05301457 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +05301458 };
1459
1460 main_mcan11: can@27b1000 {
1461 compatible = "bosch,m_can";
1462 reg = <0x00 0x027b1000 0x00 0x200>,
1463 <0x00 0x027b8000 0x00 0x8000>;
1464 reg-names = "m_can", "message_ram";
1465 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
1466 clocks = <&k3_clks 193 0>, <&k3_clks 193 1>;
1467 clock-names = "hclk", "cclk";
1468 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
1469 <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1470 interrupt-names = "int0", "int1";
1471 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +05301472 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +05301473 };
1474
1475 main_mcan12: can@27c1000 {
1476 compatible = "bosch,m_can";
1477 reg = <0x00 0x027c1000 0x00 0x200>,
1478 <0x00 0x027c8000 0x00 0x8000>;
1479 reg-names = "m_can", "message_ram";
1480 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
1481 clocks = <&k3_clks 194 0>, <&k3_clks 194 1>;
1482 clock-names = "hclk", "cclk";
1483 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
1484 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
1485 interrupt-names = "int0", "int1";
1486 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +05301487 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +05301488 };
1489
1490 main_mcan13: can@27d1000 {
1491 compatible = "bosch,m_can";
1492 reg = <0x00 0x027d1000 0x00 0x200>,
1493 <0x00 0x027d8000 0x00 0x8000>;
1494 reg-names = "m_can", "message_ram";
1495 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
1496 clocks = <&k3_clks 195 0>, <&k3_clks 195 1>;
1497 clock-names = "hclk", "cclk";
1498 interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
1499 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
1500 interrupt-names = "int0", "int1";
1501 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +05301502 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +05301503 };
1504
1505 main_mcan14: can@2681000 {
1506 compatible = "bosch,m_can";
1507 reg = <0x00 0x02681000 0x00 0x200>,
1508 <0x00 0x02688000 0x00 0x8000>;
1509 reg-names = "m_can", "message_ram";
1510 power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>;
1511 clocks = <&k3_clks 197 0>, <&k3_clks 197 1>;
1512 clock-names = "hclk", "cclk";
1513 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
1514 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>;
1515 interrupt-names = "int0", "int1";
1516 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +05301517 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +05301518 };
1519
1520 main_mcan15: can@2691000 {
1521 compatible = "bosch,m_can";
1522 reg = <0x00 0x02691000 0x00 0x200>,
1523 <0x00 0x02698000 0x00 0x8000>;
1524 reg-names = "m_can", "message_ram";
1525 power-domains = <&k3_pds 199 TI_SCI_PD_EXCLUSIVE>;
1526 clocks = <&k3_clks 199 0>, <&k3_clks 199 1>;
1527 clock-names = "hclk", "cclk";
1528 interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
1529 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>;
1530 interrupt-names = "int0", "int1";
1531 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +05301532 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +05301533 };
1534
1535 main_mcan16: can@26a1000 {
1536 compatible = "bosch,m_can";
1537 reg = <0x00 0x026a1000 0x00 0x200>,
1538 <0x00 0x026a8000 0x00 0x8000>;
1539 reg-names = "m_can", "message_ram";
1540 power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>;
1541 clocks = <&k3_clks 201 0>, <&k3_clks 201 1>;
1542 clock-names = "hclk", "cclk";
1543 interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
1544 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>;
1545 interrupt-names = "int0", "int1";
1546 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +05301547 status = "disabled";
Aswath Govindraju0e548f02022-01-25 20:56:40 +05301548 };
1549
1550 main_mcan17: can@26b1000 {
1551 compatible = "bosch,m_can";
1552 reg = <0x00 0x026b1000 0x00 0x200>,
1553 <0x00 0x026b8000 0x00 0x8000>;
1554 reg-names = "m_can", "message_ram";
1555 power-domains = <&k3_pds 206 TI_SCI_PD_EXCLUSIVE>;
1556 clocks = <&k3_clks 206 0>, <&k3_clks 206 1>;
1557 clock-names = "hclk", "cclk";
1558 interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>,
1559 <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>;
1560 interrupt-names = "int0", "int1";
1561 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
Manorit Chawdhry377cc642023-10-06 10:15:58 +05301562 status = "disabled";
1563 };
1564
1565 main_spi0: spi@2100000 {
1566 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1567 reg = <0x00 0x02100000 0x00 0x400>;
1568 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
1569 #address-cells = <1>;
1570 #size-cells = <0>;
1571 power-domains = <&k3_pds 339 TI_SCI_PD_EXCLUSIVE>;
1572 clocks = <&k3_clks 339 1>;
1573 status = "disabled";
1574 };
1575
1576 main_spi1: spi@2110000 {
1577 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1578 reg = <0x00 0x02110000 0x00 0x400>;
1579 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
1580 #address-cells = <1>;
1581 #size-cells = <0>;
1582 power-domains = <&k3_pds 340 TI_SCI_PD_EXCLUSIVE>;
1583 clocks = <&k3_clks 340 1>;
1584 status = "disabled";
1585 };
1586
1587 main_spi2: spi@2120000 {
1588 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1589 reg = <0x00 0x02120000 0x00 0x400>;
1590 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1591 #address-cells = <1>;
1592 #size-cells = <0>;
1593 power-domains = <&k3_pds 341 TI_SCI_PD_EXCLUSIVE>;
1594 clocks = <&k3_clks 341 1>;
1595 status = "disabled";
1596 };
1597
1598 main_spi3: spi@2130000 {
1599 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1600 reg = <0x00 0x02130000 0x00 0x400>;
1601 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1602 #address-cells = <1>;
1603 #size-cells = <0>;
1604 power-domains = <&k3_pds 342 TI_SCI_PD_EXCLUSIVE>;
1605 clocks = <&k3_clks 342 1>;
1606 status = "disabled";
1607 };
1608
1609 main_spi4: spi@2140000 {
1610 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1611 reg = <0x00 0x02140000 0x00 0x400>;
1612 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1613 #address-cells = <1>;
1614 #size-cells = <0>;
1615 power-domains = <&k3_pds 343 TI_SCI_PD_EXCLUSIVE>;
1616 clocks = <&k3_clks 343 1>;
1617 status = "disabled";
1618 };
1619
1620 main_spi5: spi@2150000 {
1621 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1622 reg = <0x00 0x02150000 0x00 0x400>;
1623 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
1624 #address-cells = <1>;
1625 #size-cells = <0>;
1626 power-domains = <&k3_pds 344 TI_SCI_PD_EXCLUSIVE>;
1627 clocks = <&k3_clks 344 1>;
1628 status = "disabled";
1629 };
1630
1631 main_spi6: spi@2160000 {
1632 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1633 reg = <0x00 0x02160000 0x00 0x400>;
1634 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1635 #address-cells = <1>;
1636 #size-cells = <0>;
1637 power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>;
1638 clocks = <&k3_clks 345 1>;
1639 status = "disabled";
1640 };
1641
1642 main_spi7: spi@2170000 {
1643 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1644 reg = <0x00 0x02170000 0x00 0x400>;
1645 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
1646 #address-cells = <1>;
1647 #size-cells = <0>;
1648 power-domains = <&k3_pds 346 TI_SCI_PD_EXCLUSIVE>;
1649 clocks = <&k3_clks 346 1>;
1650 status = "disabled";
1651 };
1652
1653 dss: dss@4a00000 {
1654 compatible = "ti,j721e-dss";
1655 reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */
1656 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
1657 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
1658 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
1659 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
1660 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
1661 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */
1662 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */
1663 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
1664 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
1665 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
1666 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
1667 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */
1668 <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */
1669 <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */
1670 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
1671 <0x00 0x04af0000 0x00 0x10000>; /* wb */
1672 reg-names = "common_m", "common_s0",
1673 "common_s1", "common_s2",
1674 "vidl1", "vidl2","vid1","vid2",
1675 "ovr1", "ovr2", "ovr3", "ovr4",
1676 "vp1", "vp2", "vp3", "vp4",
1677 "wb";
1678 clocks = <&k3_clks 158 0>,
1679 <&k3_clks 158 2>,
1680 <&k3_clks 158 5>,
1681 <&k3_clks 158 14>,
1682 <&k3_clks 158 18>;
1683 clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
1684 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
1685 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
1686 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
1687 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
1688 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1689 interrupt-names = "common_m",
1690 "common_s0",
1691 "common_s1",
1692 "common_s2";
1693 status = "disabled";
1694
1695 dss_ports: ports {
1696 };
Aswath Govindraju0e548f02022-01-25 20:56:40 +05301697 };
1698};