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git01.mediatek.com / filogic / uboot / e4f41ae865323d12a241b2421d61e8f34dec2bac / . / arch / arm / dts / k3-j721e-sk-u-boot.dtsi
blob: 370fe5190b2d6819872d537b2d0f23e5b349ee47 [file] [log] [blame]
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
Neha Malcom Francis20a90042023-07-22 00:14:28 +0530[diff] [blame]6#include "k3-j721e-binman.dtsi"
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]7
Neha Malcom Franciscf5bc692023-09-27 18:39:56 +0530[diff] [blame]8&cbass_main {
Nishanth Menond16f3d72023-10-05 13:15:14 -0500[diff] [blame]9 bootph-all;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]10};
11
Neha Malcom Franciscf5bc692023-09-27 18:39:56 +0530[diff] [blame]12&main_navss {
Nishanth Menond16f3d72023-10-05 13:15:14 -0500[diff] [blame]13 bootph-all;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]14};
15
16&cbass_mcu_wakeup {
Nishanth Menond16f3d72023-10-05 13:15:14 -0500[diff] [blame]17 bootph-all;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]18
Neha Malcom Franciscf5bc692023-09-27 18:39:56 +0530[diff] [blame]19 chipid@43000014 {
Nishanth Menond16f3d72023-10-05 13:15:14 -0500[diff] [blame]20 bootph-all;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]21 };
Neha Malcom Franciscf5bc692023-09-27 18:39:56 +0530[diff] [blame]22};
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]23
Neha Malcom Franciscf5bc692023-09-27 18:39:56 +0530[diff] [blame]24&mcu_navss {
Nishanth Menond16f3d72023-10-05 13:15:14 -0500[diff] [blame]25 bootph-all;
Neha Malcom Franciscf5bc692023-09-27 18:39:56 +0530[diff] [blame]26};
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]27
Neha Malcom Franciscf5bc692023-09-27 18:39:56 +0530[diff] [blame]28&mcu_ringacc {
Nishanth Menond16f3d72023-10-05 13:15:14 -0500[diff] [blame]29 bootph-all;
Neha Malcom Franciscf5bc692023-09-27 18:39:56 +0530[diff] [blame]30};
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]31
Neha Malcom Franciscf5bc692023-09-27 18:39:56 +0530[diff] [blame]32&mcu_udmap {
33 reg = <0x0 0x285c0000 0x0 0x100>,
34 <0x0 0x284c0000 0x0 0x4000>,
35 <0x0 0x2a800000 0x0 0x40000>,
36 <0x0 0x284a0000 0x0 0x4000>,
37 <0x0 0x2aa00000 0x0 0x40000>,
38 <0x0 0x28400000 0x0 0x2000>;
39 reg-names = "gcfg", "rchan", "rchanrt", "tchan",
40 "tchanrt", "rflow";
Nishanth Menond16f3d72023-10-05 13:15:14 -0500[diff] [blame]41 bootph-all;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]42};
43
44&secure_proxy_main {
Nishanth Menond16f3d72023-10-05 13:15:14 -0500[diff] [blame]45 bootph-all;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]46};
47
48&dmsc {
Nishanth Menond16f3d72023-10-05 13:15:14 -0500[diff] [blame]49 bootph-all;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]50 k3_sysreset: sysreset-controller {
51 compatible = "ti,sci-sysreset";
Nishanth Menond16f3d72023-10-05 13:15:14 -0500[diff] [blame]52 bootph-all;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]53 };
54};
55
56&k3_pds {
Nishanth Menond16f3d72023-10-05 13:15:14 -0500[diff] [blame]57 bootph-all;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]58};
59
60&k3_clks {
Nishanth Menond16f3d72023-10-05 13:15:14 -0500[diff] [blame]61 bootph-all;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]62};
63
64&k3_reset {
Nishanth Menond16f3d72023-10-05 13:15:14 -0500[diff] [blame]65 bootph-all;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]66};
67
68&wkup_pmx0 {
Nishanth Menond16f3d72023-10-05 13:15:14 -0500[diff] [blame]69 bootph-all;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]70};
71
72&main_pmx0 {
Nishanth Menond16f3d72023-10-05 13:15:14 -0500[diff] [blame]73 bootph-all;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]74};
75
76&main_uart0 {
Nishanth Menond16f3d72023-10-05 13:15:14 -0500[diff] [blame]77 bootph-all;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]78};
79
80&mcu_uart0 {
Nishanth Menond16f3d72023-10-05 13:15:14 -0500[diff] [blame]81 bootph-all;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]82};
83
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]84&main_sdhci1 {
Nishanth Menond16f3d72023-10-05 13:15:14 -0500[diff] [blame]85 bootph-all;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]86};
87
Neha Malcom Franciscf5bc692023-09-27 18:39:56 +0530[diff] [blame]88&main_uart0_pins_default {
Nishanth Menond16f3d72023-10-05 13:15:14 -0500[diff] [blame]89 bootph-all;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]90};
91
92&main_usbss0_pins_default {
Nishanth Menond16f3d72023-10-05 13:15:14 -0500[diff] [blame]93 bootph-all;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]94};
95
96&usbss0 {
Nishanth Menond16f3d72023-10-05 13:15:14 -0500[diff] [blame]97 bootph-all;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]98};
99
100&usb0 {
101 dr_mode = "host";
Nishanth Menond16f3d72023-10-05 13:15:14 -0500[diff] [blame]102 bootph-all;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]103};
104
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]105&main_usbss1_pins_default {
Nishanth Menond16f3d72023-10-05 13:15:14 -0500[diff] [blame]106 bootph-all;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]107};
108
109&usbss1 {
Nishanth Menond16f3d72023-10-05 13:15:14 -0500[diff] [blame]110 bootph-all;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]111};
112
113&usb1 {
114 dr_mode = "host";
Nishanth Menond16f3d72023-10-05 13:15:14 -0500[diff] [blame]115 bootph-all;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]116};
117
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]118&main_mmc1_pins_default {
Nishanth Menond16f3d72023-10-05 13:15:14 -0500[diff] [blame]119 bootph-all;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]120};
121
122&wkup_i2c0_pins_default {
Nishanth Menond16f3d72023-10-05 13:15:14 -0500[diff] [blame]123 bootph-all;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]124};
125
126&wkup_i2c0 {
Nishanth Menond16f3d72023-10-05 13:15:14 -0500[diff] [blame]127 bootph-all;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]128};
129
Neha Malcom Franciscf5bc692023-09-27 18:39:56 +0530[diff] [blame]130&wkup_uart0 {
Nishanth Menond16f3d72023-10-05 13:15:14 -0500[diff] [blame]131 bootph-all;
Neha Malcom Franciscf5bc692023-09-27 18:39:56 +0530[diff] [blame]132 status = "okay";
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]133};
134
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]135&mcu_fss0_ospi0_pins_default {
Nishanth Menond16f3d72023-10-05 13:15:14 -0500[diff] [blame]136 bootph-all;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]137};
138
139&fss {
Nishanth Menond16f3d72023-10-05 13:15:14 -0500[diff] [blame]140 bootph-all;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]141};
142
Neha Malcom Franciscf5bc692023-09-27 18:39:56 +0530[diff] [blame]143&main_esm {
Nishanth Menond16f3d72023-10-05 13:15:14 -0500[diff] [blame]144 bootph-all;
Sinthu Raja490d7162023-04-03 12:03:12 -0500[diff] [blame]145};
146
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]147&ospi0 {
Nishanth Menond16f3d72023-10-05 13:15:14 -0500[diff] [blame]148 bootph-all;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]149
150 flash@0 {
Nishanth Menond16f3d72023-10-05 13:15:14 -0500[diff] [blame]151 bootph-all;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]152
153 partition@3fc0000 {
Nishanth Menond16f3d72023-10-05 13:15:14 -0500[diff] [blame]154 bootph-all;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]155 };
156 };
157};