Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / e4e9bb61c1b18a8288c13839a28dd986993fc24e / . / include / configs / tegra20-common.h
blob: 617bfb2197cf9683d0fc7fb1e8f193f50e465f37 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Tom Warrena3e280b2011-01-27 10:58:07 +0000[diff] [blame]2/*
Tom Warrenc570d7a2012-05-22 12:19:25 +0000[diff] [blame]3 * (C) Copyright 2010-2012
Tom Warrena3e280b2011-01-27 10:58:07 +0000[diff] [blame]4 * NVIDIA Corporation <www.nvidia.com>
Tom Warrena3e280b2011-01-27 10:58:07 +0000[diff] [blame]5 */
6
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]7#ifndef _TEGRA20_COMMON_H_
8#define _TEGRA20_COMMON_H_
9#include "tegra-common.h"
Tom Warrena3e280b2011-01-27 10:58:07 +0000[diff] [blame]10
11/*
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]12 * NS16550 Configuration
13 */
14#define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */
15
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]16/*
17 * Miscellaneous configurable options
18 */
Jonathan Hunter80239362019-02-12 16:03:14 +0000[diff] [blame]19#define CONFIG_STACKBASE 0x03800000 /* 56MB */
Tom Warrena3e280b2011-01-27 10:58:07 +0000[diff] [blame]20
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]21/*-----------------------------------------------------------------------
22 * Physical Memory Map
23 */
Simon Glassa1dccff2012-10-17 13:24:56 +0000[diff] [blame]24
Tom Warrena3e280b2011-01-27 10:58:07 +0000[diff] [blame]25/*
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]26 * Memory layout for where various images get loaded by boot scripts:
27 *
28 * scriptaddr can be pretty much anywhere that doesn't conflict with something
29 * else. Put it above BOOTMAPSZ to eliminate conflicts.
30 *
Stephen Warren7434dfe2014-02-05 09:24:59 -0700[diff] [blame]31 * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
32 * something else. Put it above BOOTMAPSZ to eliminate conflicts.
33 *
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]34 * kernel_addr_r must be within the first 128M of RAM in order for the
35 * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
36 * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
37 * should not overlap that area, or the kernel will have to copy itself
38 * somewhere else before decompression. Similarly, the address of any other
39 * data passed to the kernel shouldn't overlap the start of RAM. Pushing
Jonathan Hunter80239362019-02-12 16:03:14 +0000[diff] [blame]40 * this up to 32M allows for a sizable kernel to be decompressed below the
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]41 * compressed load address.
42 *
Jonathan Hunter80239362019-02-12 16:03:14 +0000[diff] [blame]43 * fdt_addr_r simply shouldn't overlap anything else. Choosing 48M allows for
44 * the compressed kernel to be up to 32M too.
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]45 *
Jonathan Hunter80239362019-02-12 16:03:14 +0000[diff] [blame]46 * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]47 * for the FDT/DTB to be up to 1M, which is hopefully plenty.
Tom Warrena3e280b2011-01-27 10:58:07 +0000[diff] [blame]48 */
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]49#define MEM_LAYOUT_ENV_SETTINGS \
50 "scriptaddr=0x10000000\0" \
Stephen Warren7434dfe2014-02-05 09:24:59 -0700[diff] [blame]51 "pxefile_addr_r=0x10100000\0" \
Tom Rini9004ee02021-08-23 10:25:30 -0400[diff] [blame]52 "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
Peter Robinson637ac012020-04-02 00:28:54 +0100[diff] [blame]53 "fdtfile=" FDTFILE "\0" \
Jonathan Hunter80239362019-02-12 16:03:14 +0000[diff] [blame]54 "fdt_addr_r=0x03000000\0" \
55 "ramdisk_addr_r=0x03100000\0"
Tom Warrena3e280b2011-01-27 10:58:07 +0000[diff] [blame]56
Tom Warren22562a42012-09-04 17:00:24 -0700[diff] [blame]57#ifdef CONFIG_TEGRA_LP0
Simon Glassef2fb1a2012-04-02 13:19:03 +0000[diff] [blame]58#define TEGRA_LP0_ADDR 0x1C406000
59#define TEGRA_LP0_SIZE 0x2000
60#define TEGRA_LP0_VEC \
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]61 "lp0_vec=" __stringify(TEGRA_LP0_SIZE) \
Marek Vasut1b476f92012-09-23 17:41:25 +0200[diff] [blame]62 "@" __stringify(TEGRA_LP0_ADDR) " "
Simon Glassef2fb1a2012-04-02 13:19:03 +0000[diff] [blame]63#else
64#define TEGRA_LP0_VEC
65#endif
66
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]67#endif /* _TEGRA20_COMMON_H_ */