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Paweł Anikiel5ee903d2022-06-17 12:47:20 +02001/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright 2022 Google LLC
4 */
5#ifndef __SOCFGPA_CHAMELEONV3_H__
6#define __SOCFGPA_CHAMELEONV3_H__
7
8#include <asm/arch/base_addr_a10.h>
9
Paweł Anikiel5ee903d2022-06-17 12:47:20 +020010/*
11 * U-Boot general configurations
12 */
13
14/* Memory configurations */
15#define PHYS_SDRAM_1_SIZE 0x40000000
16
17/*
18 * Serial / UART configurations
19 */
Tom Rini6a5dccc2022-11-16 13:10:41 -050020#define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
Paweł Anikiel5ee903d2022-06-17 12:47:20 +020021
22#define CONFIG_EXTRA_ENV_SETTINGS \
23 "autoload=no\0" \
24 "bootargs=cma=256M console=ttyS1,115200 root=/dev/mmcblk0p3 rw rootwait\0" \
25 "distro_bootcmd=bridge enable; run bootcmd_mmc\0" \
26 "bootcmd_mmc=load mmc 0:1 ${loadaddr} kernel.itb; bootm\0" \
27 "bootcmd_net=dhcp; tftpboot ${loadaddr} kernel.itb; bootm\0"
28
29/*
30 * L4 OSC1 Timer 0
31 */
32/* reload value when timer count to zero */
33#define TIMER_LOAD_VAL 0xFFFFFFFF
34
Paweł Anikiel5ee903d2022-06-17 12:47:20 +020035/* The rest of the configuration is shared */
36#include <configs/socfpga_common.h>
37
38#endif /* __SOCFGPA_CHAMELEONV3_H__ */