blob: a5b7364435dd35d4a5f7a361e0b675eff98547c9 [file] [log] [blame]
Jianchao Wange5332ba2019-07-19 00:30:01 +03001/* SPDX-License-Identifier: GPL-2.0
Vladimir Oltean5041e422021-09-17 14:27:13 +03002 * Copyright 2016-2019 NXP
Jianchao Wange5332ba2019-07-19 00:30:01 +03003 * Copyright 2019 Vladimir Oltean <olteanv@gmail.com>
4 */
5
6#ifndef __CONFIG_H
7#define __CONFIG_H
8
Tom Rini6a5dccc2022-11-16 13:10:41 -05009#define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
10#define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE
Jianchao Wange5332ba2019-07-19 00:30:01 +030011
12/* XHCI Support - enabled by default */
Jianchao Wange5332ba2019-07-19 00:30:01 +030013
Jianchao Wange5332ba2019-07-19 00:30:01 +030014#define DDR_SDRAM_CFG 0x470c0008
15#define DDR_CS0_BNDS 0x008000bf
16#define DDR_CS0_CONFIG 0x80014302
17#define DDR_TIMING_CFG_0 0x50550004
18#define DDR_TIMING_CFG_1 0xbcb38c56
19#define DDR_TIMING_CFG_2 0x0040d120
20#define DDR_TIMING_CFG_3 0x010e1000
21#define DDR_TIMING_CFG_4 0x00000001
22#define DDR_TIMING_CFG_5 0x03401400
23#define DDR_SDRAM_CFG_2 0x00401010
24#define DDR_SDRAM_MODE 0x00061c60
25#define DDR_SDRAM_MODE_2 0x00180000
26#define DDR_SDRAM_INTERVAL 0x18600618
27#define DDR_DDR_WRLVL_CNTL 0x8655f605
28#define DDR_DDR_WRLVL_CNTL_2 0x05060607
29#define DDR_DDR_WRLVL_CNTL_3 0x05050505
30#define DDR_DDR_CDR1 0x80040000
31#define DDR_DDR_CDR2 0x00000001
32#define DDR_SDRAM_CLK_CNTL 0x02000000
33#define DDR_DDR_ZQ_CNTL 0x89080600
34#define DDR_CS0_CONFIG_2 0
35#define DDR_SDRAM_CFG_MEM_EN 0x80000000
36#define SDRAM_CFG2_D_INIT 0x00000010
37#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
38#define SDRAM_CFG2_FRC_SR 0x80000000
39#define SDRAM_CFG_BI 0x00000001
40
Jianchao Wange5332ba2019-07-19 00:30:01 +030041#ifdef CONFIG_SD_BOOT
Tom Rini7cf9ab72020-06-16 19:06:25 -040042#ifdef CONFIG_NXP_ESBC
Jianchao Wange5332ba2019-07-19 00:30:01 +030043#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
Tom Rini7cf9ab72020-06-16 19:06:25 -040044#endif /* ifdef CONFIG_NXP_ESBC */
Jianchao Wange5332ba2019-07-19 00:30:01 +030045
Jianchao Wange5332ba2019-07-19 00:30:01 +030046#ifdef CONFIG_U_BOOT_HDR_SIZE
47/*
48 * HDR would be appended at end of image and copied to DDR along
49 * with U-Boot image. Here u-boot max. size is 512K. So if binary
50 * size increases then increase this size in case of secure boot as
51 * it uses raw U-Boot image instead of FIT image.
52 */
Jianchao Wange5332ba2019-07-19 00:30:01 +030053#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
54#endif
55
Jianchao Wange5332ba2019-07-19 00:30:01 +030056#define PHYS_SDRAM 0x80000000
57#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
58
Tom Rini6a5dccc2022-11-16 13:10:41 -050059#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
60#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
Jianchao Wange5332ba2019-07-19 00:30:01 +030061
Jianchao Wange5332ba2019-07-19 00:30:01 +030062/* Serial Port */
Tom Rinidf6a2152022-11-16 13:10:28 -050063#define CFG_SYS_NS16550_CLK get_serial_clock()
Jianchao Wange5332ba2019-07-19 00:30:01 +030064
Jianchao Wange5332ba2019-07-19 00:30:01 +030065/* I2C */
Jianchao Wange5332ba2019-07-19 00:30:01 +030066
Jianchao Wange5332ba2019-07-19 00:30:01 +030067/* PCIe */
Jianchao Wange5332ba2019-07-19 00:30:01 +030068#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
Jianchao Wange5332ba2019-07-19 00:30:01 +030069
Jianchao Wange5332ba2019-07-19 00:30:01 +030070#define HWCONFIG_BUFFER_SIZE 256
71
Jianchao Wange5332ba2019-07-19 00:30:01 +030072#define BOOT_TARGET_DEVICES(func) \
73 func(MMC, mmc, 0) \
74 func(USB, usb, 0) \
75 func(DHCP, dhcp, na)
76#include <config_distro_bootcmd.h>
77
78#define CONFIG_EXTRA_ENV_SETTINGS \
79 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
80 "initrd_high=0xffffffff\0" \
Jianchao Wange5332ba2019-07-19 00:30:01 +030081 "kernel_addr=0x61000000\0" \
82 "kernelheader_addr=0x60800000\0" \
83 "scriptaddr=0x80000000\0" \
84 "scripthdraddr=0x80080000\0" \
85 "fdtheader_addr_r=0x80100000\0" \
86 "kernelheader_addr_r=0x80200000\0" \
87 "kernel_addr_r=0x80008000\0" \
88 "kernelheader_size=0x40000\0" \
89 "fdt_addr_r=0x8f000000\0" \
90 "ramdisk_addr_r=0xa0000000\0" \
91 "load_addr=0x80008000\0" \
92 "kernel_size=0x2800000\0" \
93 "kernel_addr_sd=0x8000\0" \
94 "kernel_size_sd=0x14000\0" \
95 "kernelhdr_addr_sd=0x4000\0" \
96 "kernelhdr_size_sd=0x10\0" \
97 BOOTENV \
98 "boot_scripts=ls1021atsn_boot.scr\0" \
99 "boot_script_hdr=hdr_ls1021atsn_bs.out\0" \
100 "scan_dev_for_boot_part=" \
101 "part list ${devtype} ${devnum} devplist; " \
102 "env exists devplist || setenv devplist 1; " \
103 "for distro_bootpart in ${devplist}; do " \
104 "if fstype ${devtype} " \
105 "${devnum}:${distro_bootpart} " \
106 "bootfstype; then " \
107 "run scan_dev_for_boot; " \
108 "fi; " \
109 "done\0" \
110 "scan_dev_for_boot=" \
111 "echo Scanning ${devtype} " \
112 "${devnum}:${distro_bootpart}...; " \
113 "for prefix in ${boot_prefixes}; do " \
114 "run scan_dev_for_scripts; " \
115 "run scan_dev_for_extlinux; " \
116 "done;" \
117 "\0" \
118 "boot_a_script=" \
119 "load ${devtype} ${devnum}:${distro_bootpart} " \
120 "${scriptaddr} ${prefix}${script}; " \
121 "env exists secureboot && load ${devtype} " \
122 "${devnum}:${distro_bootpart} " \
123 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
124 "&& esbc_validate ${scripthdraddr};" \
125 "source ${scriptaddr}\0" \
126 "qspi_bootcmd=echo Trying load from qspi..;" \
127 "sf probe && sf read $load_addr " \
128 "$kernel_addr $kernel_size; env exists secureboot " \
129 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
130 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
131 "bootm $load_addr#$board\0" \
132 "sd_bootcmd=echo Trying load from SD ..;" \
133 "mmcinfo && mmc read $load_addr " \
134 "$kernel_addr_sd $kernel_size_sd && " \
135 "env exists secureboot && mmc read $kernelheader_addr_r " \
136 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
137 " && esbc_validate ${kernelheader_addr_r};" \
138 "bootm $load_addr#$board\0"
139
140/* Miscellaneous configurable options */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500141#define CFG_SYS_BOOTMAPSZ (256 << 20)
Alison Wang71477062020-02-03 15:25:19 +0800142
Jianchao Wange5332ba2019-07-19 00:30:01 +0300143#define CONFIG_LS102XA_STREAM_ID
144
Jianchao Wange5332ba2019-07-19 00:30:01 +0300145/* Environment */
Jianchao Wange5332ba2019-07-19 00:30:01 +0300146
Jianchao Wange5332ba2019-07-19 00:30:01 +0300147#endif