| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Stelian Pop | 61e69d7 | 2008-05-08 20:52:22 +0200 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2007-2008 |
| Stelian Pop | 5ee0c7f | 2011-11-01 00:00:39 +0100 | [diff] [blame] | 4 | * Stelian Pop <stelian@popies.net> |
| Stelian Pop | 61e69d7 | 2008-05-08 20:52:22 +0200 | [diff] [blame] | 5 | * Lead Tech Design <www.leadtechdesign.com> |
| 6 | * |
| 7 | * Configuation settings for the AT91SAM9261EK board. |
| Stelian Pop | 61e69d7 | 2008-05-08 20:52:22 +0200 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #ifndef __CONFIG_H |
| 11 | #define __CONFIG_H |
| 12 | |
| 13 | /* ARM asynchronous clock */ |
| Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 14 | #define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ |
| 15 | #define CFG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ |
| Stelian Pop | 61e69d7 | 2008-05-08 20:52:22 +0200 | [diff] [blame] | 16 | |
| Xu, Hong | 0a61494 | 2011-07-31 22:49:00 +0000 | [diff] [blame] | 17 | #include <asm/hardware.h> |
| 18 | |
| Stelian Pop | 61e69d7 | 2008-05-08 20:52:22 +0200 | [diff] [blame] | 19 | /* SDRAM */ |
| Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 20 | #define CFG_SYS_SDRAM_BASE 0x20000000 |
| 21 | #define CFG_SYS_SDRAM_SIZE 0x04000000 |
| Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 22 | #define CFG_SYS_INIT_RAM_SIZE (16 * 1024) |
| 23 | #define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM |
| Stelian Pop | 61e69d7 | 2008-05-08 20:52:22 +0200 | [diff] [blame] | 24 | |
| 25 | /* NAND flash */ |
| Jean-Christophe PLAGNIOL-VILLARD | c9539ba | 2009-03-22 10:22:34 +0100 | [diff] [blame] | 26 | #ifdef CONFIG_CMD_NAND |
| Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 27 | #define CFG_SYS_NAND_BASE 0x40000000 |
| Jean-Christophe PLAGNIOL-VILLARD | c9539ba | 2009-03-22 10:22:34 +0100 | [diff] [blame] | 28 | /* our ALE is AD22 */ |
| Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 29 | #define CFG_SYS_NAND_MASK_ALE (1 << 22) |
| Jean-Christophe PLAGNIOL-VILLARD | c9539ba | 2009-03-22 10:22:34 +0100 | [diff] [blame] | 30 | /* our CLE is AD21 */ |
| Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 31 | #define CFG_SYS_NAND_MASK_CLE (1 << 21) |
| 32 | #define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 |
| 33 | #define CFG_SYS_NAND_READY_PIN AT91_PIN_PC15 |
| Wolfgang Denk | 1f79774 | 2009-07-18 21:52:24 +0200 | [diff] [blame] | 34 | |
| Jean-Christophe PLAGNIOL-VILLARD | c9539ba | 2009-03-22 10:22:34 +0100 | [diff] [blame] | 35 | #endif |
| Stelian Pop | 61e69d7 | 2008-05-08 20:52:22 +0200 | [diff] [blame] | 36 | |
| Stelian Pop | 61e69d7 | 2008-05-08 20:52:22 +0200 | [diff] [blame] | 37 | /* Ethernet */ |
| Stelian Pop | 61e69d7 | 2008-05-08 20:52:22 +0200 | [diff] [blame] | 38 | #define CONFIG_DM9000_BASE 0x30000000 |
| 39 | #define DM9000_IO CONFIG_DM9000_BASE |
| 40 | #define DM9000_DATA (CONFIG_DM9000_BASE + 4) |
| Xu, Hong | 0a61494 | 2011-07-31 22:49:00 +0000 | [diff] [blame] | 41 | #define CONFIG_DM9000_USE_16BIT |
| 42 | #define CONFIG_DM9000_NO_SROM |
| Stelian Pop | 61e69d7 | 2008-05-08 20:52:22 +0200 | [diff] [blame] | 43 | |
| 44 | /* USB */ |
| Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 45 | #define CFG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */ |
| Stelian Pop | 61e69d7 | 2008-05-08 20:52:22 +0200 | [diff] [blame] | 46 | |
| Stelian Pop | 61e69d7 | 2008-05-08 20:52:22 +0200 | [diff] [blame] | 47 | #endif |