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wdenke3a06802004-06-06 23:13:55 +00001/*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
6 * (C) Copyright 2002
7 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
8 *
9 * (C) Copyright 2003
10 * Texas Instruments, <www.ti.com>
11 * Kshitij Gupta <Kshitij@ti.com>
12 *
13 * See file CREDITS for list of people who contributed to this
14 * project.
15 *
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenk914be132004-06-08 00:22:43 +000023 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenke3a06802004-06-06 23:13:55 +000024 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * MA 02111-1307 USA
30 */
31
32#include <common.h>
Ben Warrenf0e37d12009-12-14 16:30:39 -080033#include <netdev.h>
wdenke3a06802004-06-06 23:13:55 +000034#if defined(CONFIG_OMAP730)
35#include <./configs/omap730.h>
36#endif
37
Wolfgang Denk6405a152006-03-31 18:32:53 +020038DECLARE_GLOBAL_DATA_PTR;
39
wdenke3a06802004-06-06 23:13:55 +000040int test_boot_mode(void);
41void spin_up_leds(void);
42void flash__init (void);
43void ether__init (void);
44void set_muxconf_regs (void);
45void peripheral_power_enable (void);
46
wdenk914be132004-06-08 00:22:43 +000047#define FLASH_ON_CS0 1
48#define FLASH_ON_CS3 0
wdenke3a06802004-06-06 23:13:55 +000049
50static inline void delay (unsigned long loops)
51{
wdenk914be132004-06-08 00:22:43 +000052 __asm__ volatile ("1:\n"
wdenke3a06802004-06-06 23:13:55 +000053 "subs %0, %1, #1\n"
54 "bne 1b":"=r" (loops):"0" (loops));
55}
56
57int test_boot_mode(void)
58{
59 /* Check for CS0 and CS3 address decode swapping */
60 if (*((volatile int *)EMIFS_CONFIG) & 0x00000002)
61 return(FLASH_ON_CS3);
62 else
63 return(FLASH_ON_CS0);
64}
65
66/* Toggle backup LED indication */
67void toggle_backup_led(void)
68{
wdenk914be132004-06-08 00:22:43 +000069 static int backupLEDState = 0; /* Init variable so that the LED will be ON the first time */
wdenke3a06802004-06-06 23:13:55 +000070 volatile unsigned int *IOConfReg;
71
72
73 IOConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_5 + GPIO_DATA_OUTPUT);
74
75 if (backupLEDState != 0) {
76 *IOConfReg &= (0xFFFFEFFF);
77 backupLEDState = 0;
78 } else {
79 *IOConfReg |= (0x00001000);
80 backupLEDState = 1;
81 }
82}
83
84/*
85 * Miscellaneous platform dependent initialisations
86 */
87
88int board_init (void)
89{
wdenke3a06802004-06-06 23:13:55 +000090 /* arch number of OMAP 730 P2 Board - Same as the Innovator! */
wdenk767fbd42004-10-10 18:41:04 +000091 gd->bd->bi_arch_number = MACH_TYPE_OMAP_PERSEUS2;
wdenke3a06802004-06-06 23:13:55 +000092
93 /* adress of boot parameters */
94 gd->bd->bi_boot_params = 0x10000100;
95
96 /* Configure MUX settings */
97 set_muxconf_regs ();
98
99 peripheral_power_enable ();
100
wdenke3a06802004-06-06 23:13:55 +0000101 /* Backup LED indication via GPIO_140 -> Red led if MUX correctly setup */
102 toggle_backup_led();
103
104 /* Hold GSM in reset until needed */
105 *((volatile unsigned short *)M_CTL) &= ~1;
106
wdenke3a06802004-06-06 23:13:55 +0000107 /*
108 * CSx timings, GPIO Mux ... setup
109 */
110
111 /* Flash: CS0 timings setup */
112 *((volatile unsigned int *) FLASH_CFG_0) = 0x0000fff3;
113 *((volatile unsigned int *) FLASH_ACFG_0_1) = 0x00000088;
114
115 /* Ethernet support trough the debug board */
116 /* CS1 timings setup */
117 *((volatile unsigned int *) FLASH_CFG_1) = 0x0000fff3;
118 *((volatile unsigned int *) FLASH_ACFG_0_1) = 0x00000000;
119
120 /* this speeds up your boot a quite a bit. However to make it
121 * work, you need make sure your kernel startup flush bug is fixed.
122 * ... rkw ...
123 */
124 icache_enable ();
125
126 flash__init ();
127 ether__init ();
128
129 return 0;
130}
131
132int misc_init_r (void)
133{
134 /* currently empty */
135 return (0);
136}
137
138/******************************
139 Routine:
140 Description:
141******************************/
142void flash__init (void)
143{
wdenk914be132004-06-08 00:22:43 +0000144 unsigned int regval;
wdenke3a06802004-06-06 23:13:55 +0000145
wdenk914be132004-06-08 00:22:43 +0000146 regval = *((volatile unsigned int *) EMIFS_CONFIG);
147 /* Turn off write protection for flash devices. */
148 regval = regval | 0x0001;
149 *((volatile unsigned int *) EMIFS_CONFIG) = regval;
wdenke3a06802004-06-06 23:13:55 +0000150}
151
152/*************************************************************
153 Routine:ether__init
154 Description: take the Ethernet controller out of reset and wait
wdenk914be132004-06-08 00:22:43 +0000155 for the EEPROM load to complete.
wdenke3a06802004-06-06 23:13:55 +0000156*************************************************************/
157void ether__init (void)
158{
159#define LAN_RESET_REGISTER 0x0400001c
160
161 *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000;
162 do {
163 *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0001;
164 udelay (100);
165 } while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0001);
166
167 do {
168 *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000;
169 udelay (100);
170 } while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0000);
171
172#define ETH_CONTROL_REG 0x0400030b
173
174 *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
175 udelay (100);
176}
177
178/******************************
179 Routine:
180 Description:
181******************************/
182int dram_init (void)
183{
wdenke3a06802004-06-06 23:13:55 +0000184 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
185 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
186
187 return 0;
188}
189
190/******************************************************
191 Routine: set_muxconf_regs
192 Description: Setting up the configuration Mux registers
wdenk914be132004-06-08 00:22:43 +0000193 specific to the hardware
wdenke3a06802004-06-06 23:13:55 +0000194*******************************************************/
195void set_muxconf_regs (void)
196{
197 volatile unsigned int *MuxConfReg;
198 /* set each registers to its reset value; */
199
200 /*
201 * Backup LED Indication
202 */
203
204 /* Configure MUXed pin. Mode 6: GPIO_140 */
205 MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF10);
wdenk914be132004-06-08 00:22:43 +0000206 *MuxConfReg &= (0xFFFFFF1F); /* Clear D_MPU_LPG1 */
207 *MuxConfReg |= 0x000000C0; /* Set D_MPU_LPG1 to 0x6 */
wdenke3a06802004-06-06 23:13:55 +0000208
209 /* Configure GPIO_140 as output */
210 MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_5 + GPIO_DIRECTION_CONTROL);
wdenk914be132004-06-08 00:22:43 +0000211 *MuxConfReg &= (0xFFFFEFFF); /* Clear direction (output) for GPIO 140 */
wdenke3a06802004-06-06 23:13:55 +0000212
213 /*
214 * Configure GPIOs for battery charge & feedback
215 */
216
217 /* Configure MUXed pin. Mode 6: GPIO_35 */
218 MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF3);
wdenk914be132004-06-08 00:22:43 +0000219 *MuxConfReg &= 0xFFFFFFF1; /* Clear M_CLK_OUT */
220 *MuxConfReg |= 0x0000000C; /* Set M_CLK_OUT = 0x6 (GPIOs) */
wdenke3a06802004-06-06 23:13:55 +0000221
222 /* Configure MUXed pin. Mode 6: GPIO_72,73,74 */
223 MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF5);
wdenk914be132004-06-08 00:22:43 +0000224 *MuxConfReg &= 0xFFFF1FFF; /* Clear D_DDR */
225 *MuxConfReg |= 0x0000C000; /* Set D_DDR = 0x6 (GPIOs) */
wdenke3a06802004-06-06 23:13:55 +0000226
227 MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_3 + GPIO_DIRECTION_CONTROL);
wdenk914be132004-06-08 00:22:43 +0000228 *MuxConfReg |= 0x00000100; /* Configure GPIO_72 as input */
229 *MuxConfReg &= 0xFFFFFDFF; /* Configure GPIO_73 as output */
wdenke3a06802004-06-06 23:13:55 +0000230
231 /*
232 * Allow battery charge
233 */
234
235 MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_3 + GPIO_DATA_OUTPUT);
wdenk914be132004-06-08 00:22:43 +0000236 *MuxConfReg &= (0xFFFFFDFF); /* Clear GPIO_73 pin */
wdenke3a06802004-06-06 23:13:55 +0000237
238 /*
239 * Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
240 * It is used as the Ethernet controller interrupt
241 */
242 MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF9);
243 *MuxConfReg &= 0x1FFFFFFF;
244}
245
246/******************************************************
247 Routine: peripheral_power_enable
248 Description: Enable the power for UART1
249*******************************************************/
250void peripheral_power_enable (void)
251{
252 volatile unsigned int *MuxConfReg;
253
254
255 /* Set up pins used by UART */
256
257 /* Start UART clock (48MHz) */
258 MuxConfReg = (volatile unsigned int *) (PERSEUS_PCC_CONF_REG);
259 *MuxConfReg &= (0xFFFFFFF7);
260 *MuxConfReg |= (0x00000008);
261
262 /* Get the UART pin in mode0 */
263 MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF3);
264 *MuxConfReg &= (0xFF1FFFFF);
265 *MuxConfReg &= (0xF1FFFFFF);
266}
Ben Warrenf0e37d12009-12-14 16:30:39 -0800267
268#ifdef CONFIG_CMD_NET
269int board_eth_init(bd_t *bis)
270{
271 int rc = 0;
272#ifdef CONFIG_LAN91C96
273 rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
274#endif
275 return rc;
276}
277#endif