| Thomas Chou | 7ffbbf5 | 2010-04-21 08:40:59 +0800 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw> |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | * |
| 8 | * This file is generated by sopc-create-config-files. |
| 9 | */ |
| 10 | #ifndef _CUSTOM_FPGA_H_ |
| 11 | #define _CUSTOM_FPGA_H_ |
| 12 | |
| 13 | /* generated from std_1c20.sopc */ |
| 14 | |
| 15 | /* cpu.data_master is a altera_nios2 */ |
| 16 | #define CONFIG_SYS_CLK_FREQ 50000000 |
| 17 | #define CONFIG_SYS_RESET_ADDR 0x00000000 |
| 18 | #define CONFIG_SYS_EXCEPTION_ADDR 0x01000020 |
| 19 | #define CONFIG_SYS_ICACHE_SIZE 4096 |
| 20 | #define CONFIG_SYS_ICACHELINE_SIZE 32 |
| 21 | #define CONFIG_SYS_DCACHE_SIZE 2048 |
| 22 | #define CONFIG_SYS_DCACHELINE_SIZE 4 |
| 23 | |
| 24 | /* sdram.s1 is a altera_avalon_new_sdram_controller */ |
| 25 | #define CONFIG_SYS_SDRAM_BASE 0x01000000 |
| 26 | #define CONFIG_SYS_SDRAM_SIZE 0x01000000 |
| 27 | |
| 28 | /* uart1.s1 is a altera_avalon_uart */ |
| 29 | #define CONFIG_SYS_UART_BASE 0x82120840 |
| 30 | #define CONFIG_SYS_UART_FREQ 50000000 |
| 31 | #define CONFIG_SYS_UART_BAUD 115200 |
| 32 | |
| 33 | /* lan91c111.s1 is a altera_avalon_lan91c111 */ |
| 34 | #define CONFIG_SMC91111_BASE 0x82110300 |
| 35 | #define CONFIG_SMC91111 |
| 36 | #define CONFIG_SMC_USE_32_BIT |
| 37 | |
| Thomas Chou | 199ce71 | 2010-04-30 11:34:18 +0800 | [diff] [blame] | 38 | /* epcs_controller.epcs_control_port is a altera_avalon_epcs_flash_controller */ |
| 39 | #define EPCS_CONTROLLER_REG_BASE 0x82100200 |
| 40 | #define CONFIG_SYS_ALTERA_SPI_LIST { EPCS_CONTROLLER_REG_BASE } |
| 41 | #define CONFIG_ALTERA_SPI |
| 42 | #define CONFIG_CMD_SPI |
| 43 | #define CONFIG_CMD_SF |
| 44 | #define CONFIG_SF_DEFAULT_SPEED 30000000 |
| 45 | #define CONFIG_SPI_FLASH |
| 46 | #define CONFIG_SPI_FLASH_STMICRO |
| 47 | |
| Thomas Chou | 7ffbbf5 | 2010-04-21 08:40:59 +0800 | [diff] [blame] | 48 | /* jtag_uart.avalon_jtag_slave is a altera_avalon_jtag_uart */ |
| 49 | #define CONFIG_SYS_JTAG_UART_BASE 0x821208b0 |
| 50 | |
| 51 | /* led_pio.s1 is a altera_avalon_pio */ |
| 52 | #define LED_PIO_BASE 0x82120870 |
| Thomas Chou | 5dbb29f | 2010-12-27 10:46:01 +0800 | [diff] [blame] | 53 | #define LED_PIO_WIDTH 8 |
| Joachim Foerster | c932eed | 2011-10-21 15:48:50 +0200 | [diff] [blame] | 54 | #define LED_PIO_RSTVAL 0x0 |
| Thomas Chou | 7ffbbf5 | 2010-04-21 08:40:59 +0800 | [diff] [blame] | 55 | |
| 56 | /* high_res_timer.s1 is a altera_avalon_timer */ |
| 57 | #define CONFIG_SYS_TIMER_BASE 0x82120820 |
| 58 | #define CONFIG_SYS_TIMER_IRQ 3 |
| 59 | #define CONFIG_SYS_TIMER_FREQ 50000000 |
| 60 | |
| 61 | /* ext_flash.s1 is a altera_avalon_cfi_flash */ |
| 62 | #define CONFIG_SYS_FLASH_BASE 0x80000000 |
| 63 | #define CONFIG_FLASH_CFI_DRIVER |
| 64 | #define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */ |
| 65 | #define CONFIG_SYS_FLASH_CFI |
| 66 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
| 67 | #define CONFIG_SYS_FLASH_PROTECTION |
| 68 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
| 69 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 |
| 70 | |
| 71 | /* ext_ram.s1 is a altera_nios_dev_kit_stratix_edition_sram2 */ |
| 72 | #define CONFIG_SYS_SRAM_BASE 0x02000000 |
| 73 | #define CONFIG_SYS_SRAM_SIZE 0x00100000 |
| 74 | |
| 75 | /* sysid.control_slave is a altera_avalon_sysid */ |
| 76 | #define CONFIG_SYS_SYSID_BASE 0x821208b8 |
| 77 | |
| 78 | #endif /* _CUSTOM_FPGA_H_ */ |