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git01.mediatek.com / filogic / uboot / e4c1bbf0a76d2f06d91d160c9727b08b046b5e2b / . / arch / arm / dts / k3-am65.dtsi
blob: 3d4bf369d0304a3afb8bcb43e18ca1eeb2648413 [file] [log] [blame]
Lokesh Vutla8bfaf012018-08-27 15:59:08 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for AM6 SoC Family
4 *
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/interrupt-controller/irq.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11
12/ {
13 model = "Texas Instruments K3 AM654 SoC";
14 compatible = "ti,am654";
15 interrupt-parent = <&gic500>;
16 #address-cells = <2>;
17 #size-cells = <2>;
18
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]19 aliases {
20 serial0 = &wkup_uart0;
21 serial1 = &mcu_uart0;
22 serial2 = &main_uart0;
23 serial3 = &main_uart1;
24 serial4 = &main_uart2;
25 };
26
Lokesh Vutla8bfaf012018-08-27 15:59:08 +0530[diff] [blame]27 chosen { };
28
29 firmware {
30 optee {
31 compatible = "linaro,optee-tz";
32 method = "smc";
33 };
34
35 psci: psci {
36 compatible = "arm,psci-1.0";
37 method = "smc";
38 };
39 };
40
41 a53_timer0: timer-cl0-cpu0 {
42 compatible = "arm,armv8-timer";
43 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
44 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
45 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
46 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
47 };
48
49 pmu: pmu {
50 compatible = "arm,armv8-pmuv3";
51 /* Recommendation from GIC500 TRM Table A.3 */
52 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
53 };
54
55 cbass_main: interconnect@100000 {
56 compatible = "simple-bus";
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]57 #address-cells = <2>;
58 #size-cells = <2>;
59 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
60 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
61 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
62 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
63 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
Lokesh Vutla8bfaf012018-08-27 15:59:08 +0530[diff] [blame]64 /* MCUSS Range */
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]65 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
66 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
67 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
68 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
69 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
70 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>;
Lokesh Vutla8bfaf012018-08-27 15:59:08 +0530[diff] [blame]71
72 cbass_mcu: interconnect@28380000 {
73 compatible = "simple-bus";
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]74 #address-cells = <2>;
75 #size-cells = <2>;
76 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
77 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */
78 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */
79 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
80 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
81 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>; /* OSPI space 1 */
Lokesh Vutla8bfaf012018-08-27 15:59:08 +0530[diff] [blame]82
83 cbass_wakeup: interconnect@42040000 {
84 compatible = "simple-bus";
85 #address-cells = <1>;
86 #size-cells = <1>;
87 /* WKUP Basic peripherals */
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]88 ranges = <0x42040000 0x00 0x42040000 0x03ac2400>;
Lokesh Vutla8bfaf012018-08-27 15:59:08 +0530[diff] [blame]89 };
90 };
91 };
92};
93
94/* Now include the peripherals for each bus segments */
95#include "k3-am65-main.dtsi"
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]96#include "k3-am65-mcu.dtsi"
97#include "k3-am65-wakeup.dtsi"