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git01.mediatek.com / filogic / uboot / e4c1bbf0a76d2f06d91d160c9727b08b046b5e2b / . / arch / arm / dts / imx6-logicpd-som.dtsi
blob: 3fc50babf09979816c67c17fbe3248b13d29a6a8 [file] [log] [blame]
Adam Ford158e9192018-12-28 08:55:41 -0600[diff] [blame]1/*
2 * Copyright 2018 Logic PD
3 * This file is adapted from imx6qdl-sabresd.dtsi.
4 * Copyright 2012 Freescale Semiconductor, Inc.
5 * Copyright 2011 Linaro Ltd.
6 *
7 * The code contained herein is licensed under the GNU General Public
8 * License. You may obtain a copy of the GNU General Public License
9 * Version 2 or later at the following locations:
10 *
11 * http://www.opensource.org/licenses/gpl-license.html
12 * http://www.gnu.org/copyleft/gpl.html
13 */
14
15#include <dt-bindings/gpio/gpio.h>
16#include <dt-bindings/input/input.h>
17
18/ {
19 chosen {
20 stdout-path = &uart1;
21 };
22
23 memory {
24 reg = <0x10000000 0x80000000>;
25 };
26
27 reg_wl18xx_vmmc: regulator-wl18xx {
28 compatible = "regulator-fixed";
29 regulator-name = "vwl1837";
30 regulator-min-microvolt = <3300000>;
31 regulator-max-microvolt = <3300000>;
32 gpio = <&gpio7 0 GPIO_ACTIVE_HIGH>;
33 startup-delay-us = <70000>;
34 enable-active-high;
35 };
36};
37
38/* Reroute power feeding the CPU to come from the external PMIC */
39&reg_arm
40{
41 vin-supply = <&sw1a_reg>;
42};
43
44&reg_soc
45{
46 vin-supply = <&sw1c_reg>;
47};
48
49&clks {
50 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
51 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
52 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
53 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
54};
55
56&gpmi {
57 pinctrl-names = "default";
58 pinctrl-0 = <&pinctrl_gpmi_nand>;
59 status = "okay";
60 nand-on-flash-bbt;
61};
62
63&i2c3 {
64 clock-frequency = <100000>;
65 pinctrl-names = "default";
66 pinctrl-0 = <&pinctrl_i2c3>;
67 status = "okay";
68
69 pmic: pfuze100@08 {
70 compatible = "fsl,pfuze100";
71 reg = <0x08>;
72
73 regulators {
74 sw1a_reg: sw1ab {
75 regulator-min-microvolt = <725000>;
76 regulator-max-microvolt = <1450000>;
77 regulator-name = "vddcore";
78 regulator-boot-on;
79 regulator-always-on;
80 regulator-ramp-delay = <6250>;
81 };
82
83 sw1c_reg: sw1c {
84 regulator-min-microvolt = <725000>;
85 regulator-max-microvolt = <1450000>;
86 regulator-name = "vddsoc";
87 regulator-boot-on;
88 regulator-always-on;
89 regulator-ramp-delay = <6250>;
90 };
91
92 sw2_reg: sw2 {
93 regulator-min-microvolt = <3300000>;
94 regulator-max-microvolt = <3300000>;
95 regulator-name = "gen_3v3";
96 regulator-boot-on;
97 /* regulator-always-on; */
98 };
99
100 sw3a_reg: sw3a {
101 regulator-min-microvolt = <400000>;
102 regulator-max-microvolt = <1975000>;
103 regulator-name = "sw3a_vddr";
104 regulator-boot-on;
105 regulator-always-on;
106 };
107
108 sw3b_reg: sw3b {
109 regulator-min-microvolt = <400000>;
110 regulator-max-microvolt = <1975000>;
111 regulator-name = "sw3b_vddr";
112 regulator-boot-on;
113 regulator-always-on;
114 };
115
116 sw4_reg: sw4 {
117 regulator-min-microvolt = <1800000>;
118 regulator-max-microvolt = <3300000>;
119 regulator-name = "gen_rgmii";
120 };
121
122 swbst_reg: swbst {
123 regulator-min-microvolt = <5000000>;
124 regulator-max-microvolt = <5150000>;
125 regulator-name = "gen_5v0";
126 };
127
128 snvs_reg: vsnvs {
129 regulator-min-microvolt = <1000000>;
130 regulator-max-microvolt = <3000000>;
131 regulator-name = "gen_vsns";
132 regulator-boot-on;
133 regulator-always-on;
134 };
135
136 vref_reg: vrefddr {
137 regulator-boot-on;
138 regulator-always-on;
139 };
140
141 vgen1_reg: vgen1 {
142 regulator-min-microvolt = <1500000>;
143 regulator-max-microvolt = <1500000>;
144 regulator-name = "gen_1v5";
145 };
146
147 vgen2_reg: vgen2 {
148 regulator-name = "vgen2";
149 regulator-min-microvolt = <800000>;
150 regulator-max-microvolt = <1550000>;
151 };
152
153 vgen3_reg: vgen3 {
154 regulator-name = "gen_vadj_0";
155 regulator-min-microvolt = <3000000>;
156 regulator-max-microvolt = <3000000>;
157 };
158
159 vgen4_reg: vgen4 {
160 regulator-name = "gen_1v8";
161 regulator-min-microvolt = <1800000>;
162 regulator-max-microvolt = <1800000>;
163 regulator-always-on;
164 };
165
166 vgen5_reg: vgen5 {
167 regulator-name = "gen_adj_1";
168 regulator-min-microvolt = <3300000>;
169 regulator-max-microvolt = <3300000>;
170 regulator-always-on;
171 };
172
173 vgen6_reg: vgen6 {
174 regulator-name = "gen_2v5";
175 regulator-min-microvolt = <2500000>;
176 regulator-max-microvolt = <2500000>;
177 regulator-always-on;
178 };
179
180 coin_reg: coin {
181 regulator-min-microvolt = <2500000>;
182 regulator-max-microvolt = <3000000>;
183 regulator-always-on;
184 };
185 };
186 };
187
188 temp_sense0: tmp102@4a {
189 compatible = "ti,tmp102";
190 reg = <0x4a>;
191 pinctrl-names = "default";
192 pinctrl-0 = <&pinctrl_tempsense>;
193 interrupt-parent = <&gpio6>;
194 interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
195 #thermal-sensor-cells = <1>;
196 };
197
198 temp_sense1: tmp102@49 {
199 compatible = "ti,tmp102";
200 reg = <0x49>;
201 interrupt-parent = <&gpio6>;
202 interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
203 #thermal-sensor-cells = <1>;
204 };
205
206 mfg_eeprom: at24@51 {
207 compatible = "atmel,24c64";
208 pagesize = <32>;
209 read-only;
210 reg = <0x51>;
211 };
212
213 user_eeprom: at24@52 {
214 compatible = "atmel,24c64";
215 pagesize = <32>;
216 reg = <0x52>;
217 };
218};
219
220&iomuxc {
221 pinctrl-names = "default";
222 pinctrl-0 = <&pinctrl_hog>;
223
224 pinctrl_hog: hoggrp {
225 fsl,pins = <
226 MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x1b0b0
227 MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x1b0b0
228 MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x1b0b0
229 MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x1b0b0
230 MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 0x1b0b0
231 MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 0x1b0b0
232 MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 0x1b0b0
233 MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 0x1b0b0
234 MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 0x1b0b0
235 MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 0x1b0b0
236 MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x1b0b0
237 MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 0x1b0b0
238 MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 0x1b0b0
239 MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 0x1b0b0
240 MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 0x1b0b0
241 MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 0x1b0b0
242 MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 0x1b0b0
243 MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 0x1b0b0
244 MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 0x1b0b0
245 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
246 >;
247 };
248
249 pinctrl_gpmi_nand: gpminandgrp {
250 fsl,pins = <
251 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1
252 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1
253 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1
254 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000
255 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1
256 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1
257 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1
258 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1
259 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1
260 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1
261 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1
262 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1
263 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1
264 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1
265 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1
266 >;
267 };
268
269 pinctrl_i2c3: i2c3grp {
270 fsl,pins = <
271 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
272 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
273 >;
274 };
275
276 pinctrl_uart1: uart1grp {
277 fsl,pins = <
278 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
279 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
280 >;
281 };
282
283 pinctrl_uart2: uart2grp {
284 fsl,pins = <
285 MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x13059 /* BT_EN */
286 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
287 MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
288 MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
289 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
290 >;
291 };
292
293 pinctrl_usdhc1: usdhc1grp {
294 fsl,pins = <
295 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170B9
296 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100B9
297 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170B9
298 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170B9
299 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170B9
300 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170B9
301 >;
302 };
303
304 pinctrl_usdhc3: usdhc3grp {
305 fsl,pins = <
306 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17049
307 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10049
308 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17049
309 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17049
310 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17049
311 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17049
312 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x130b0 /* WL_IRQ */
313 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* WLAN_EN */
314 >;
315 };
316
317 pinctrl_tempsense: tempsensegrp {
318 fsl,pins = <
319 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Temp Sense Alert */
320 >;
321 };
322};
323
324&snvs_poweroff {
325 status = "okay";
326};
327
328&uart1 {
329 pinctrl-names = "default";
330 pinctrl-0 = <&pinctrl_uart1>;
331 status = "okay";
332};
333
334&uart2 {
335 pinctrl-names = "default";
336 pinctrl-0 = <&pinctrl_uart2>;
337 status = "okay";
338 uart-has-rtscts;
339 bluetooth {
340 compatible = "ti,wl1837-st";
341 enable-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
342 };
343};
344
345&usdhc1 {
346 pinctrl-names = "default", "state_100mhz", "state_200mhz";
347 pinctrl-0 = <&pinctrl_usdhc1>;
348 non-removable;
349 keep-power-in-suspend;
350 enable-sdio-wakeup;
351 status = "okay";
352 vmmc-supply = <&sw2_reg>;
353};
354
355&usdhc3 {
356 pinctrl-names = "default";
357 pinctrl-0 = <&pinctrl_usdhc3>;
358 non-removable;
359 cap-power-off-card;
360 keep-power-in-suspend;
361 wakeup-source;
362 vmmc-supply = <&reg_wl18xx_vmmc>;
363 status = "okay";
364 #address-cells = <1>;
365 #size-cells = <0>;
366 wlcore: wlcore@2 {
367 compatible = "ti,wl1837";
368 reg = <2>;
369 interrupt-parent = <&gpio7>;
370 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
371 tcxo-clock-frequency = <26000000>;
372 };
373};