blob: f966b9083fc2ea1da32a4695faecdd6907506713 [file] [log] [blame]
Simon Glassdc796912019-12-08 17:32:10 -07001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2017 Intel Corporation.
4 * Take from coreboot project file of the same name
5 */
6
Simon Glassdc796912019-12-08 17:32:10 -07007#include <asm/intel_regs.h>
8#include <asm/io.h>
9#include <asm/arch/systemagent.h>
10
11void enable_bios_reset_cpl(void)
12{
13 /*
14 * Set bits 0+1 of BIOS_RESET_CPL to indicate to the CPU
15 * that BIOS has initialised memory and power management
16 *
17 * The FSP-S does not do this. If we leave this as zero then I believe
18 * the power-aware interrupts don't work in Linux, and CPU 0 always gets
19 * the interrupt.
20 */
21 setbits_8(MCHBAR_REG(BIOS_RESET_CPL), 3);
22}