blob: 9c29c31393ccfa3c9f77e9cbafc6c121fd4b72d4 [file] [log] [blame]
Suneel Garapatiaddfabc2019-10-19 18:37:55 -07001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2018 Marvell International Ltd.
4 *
5 * https://spdx.org/licenses
6 */
7
8#include <common.h>
9#include <asm/armv8/mmu.h>
10#include <asm/io.h>
11#include <asm/arch/board.h>
12
13DECLARE_GLOBAL_DATA_PTR;
14
15#define OTX_MEM_MAP_USED 3
16
17/* 1 for 83xx, +1 is end of list which needs to be empty */
18#define OTX_MEM_MAP_MAX (OTX_MEM_MAP_USED + 1 + CONFIG_NR_DRAM_BANKS + 1)
19
20static struct mm_region otx_mem_map[OTX_MEM_MAP_MAX] = {
21 {
22 .virt = 0x800000000000UL,
23 .phys = 0x800000000000UL,
24 .size = 0x40000000000UL,
25 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
26 PTE_BLOCK_NON_SHARE
27 }, {
28 .virt = 0x840000000000UL,
29 .phys = 0x840000000000UL,
30 .size = 0x40000000000UL,
31 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
32 PTE_BLOCK_NON_SHARE
33 }, {
34 .virt = 0x880000000000UL,
35 .phys = 0x880000000000UL,
36 .size = 0x40000000000UL,
37 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
38 PTE_BLOCK_NON_SHARE
39 }
40
41};
42
43struct mm_region *mem_map = otx_mem_map;
44
45void mem_map_fill(void)
46{
47 int banks = OTX_MEM_MAP_USED;
48 u32 dram_start = CONFIG_SYS_TEXT_BASE;
49
50 if (otx_is_soc(CN83XX)) {
51 otx_mem_map[banks].virt = 0x8c0000000000UL;
52 otx_mem_map[banks].phys = 0x8c0000000000UL;
53 otx_mem_map[banks].size = 0x40000000000UL;
54 otx_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
55 PTE_BLOCK_NON_SHARE;
56 banks = banks + 1;
57 }
58
59 for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
60 otx_mem_map[banks].virt = dram_start;
61 otx_mem_map[banks].phys = dram_start;
62 otx_mem_map[banks].size = gd->ram_size;
63 otx_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
64 PTE_BLOCK_NON_SHARE;
65 banks = banks + 1;
66 }
67}
68
69u64 get_page_table_size(void)
70{
71 return 0x80000;
72}
73
74void reset_cpu(ulong addr)
75{
76}