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git01.mediatek.com / filogic / uboot / e4638a065fc1e89c66ebf7c5f8933bf7e1f96515 / . / arch / arm / dts / imx6qdl-gw5912.dtsi
blob: f51ec3d62ce00d7a452d6a57aabc1b9fc4ecd186 [file] [log] [blame]
Tim Harvey295c8f92021-03-01 14:33:30 -0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright 2019 Gateworks Corporation
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/input/linux-event-codes.h>
8#include <dt-bindings/interrupt-controller/irq.h>
9
10/ {
11 /* these are used by bootloader for disabling nodes */
12 aliases {
13 led0 = &led0;
14 led1 = &led1;
15 led2 = &led2;
Tim Harveycf08d1b2021-03-01 14:33:35 -0800[diff] [blame]16 mmc0 = &usdhc3;
Tim Harvey295c8f92021-03-01 14:33:30 -0800[diff] [blame]17 nand = &gpmi;
Tim Harvey69a53212021-07-24 10:40:36 -0700[diff] [blame]18 usb0 = &usbotg;
19 usb1 = &usbh1;
Tim Harvey295c8f92021-03-01 14:33:30 -0800[diff] [blame]20 };
21
22 chosen {
23 stdout-path = &uart2;
24 };
25
26 gpio-keys {
27 compatible = "gpio-keys";
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 user-pb {
32 label = "user_pb";
33 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
34 linux,code = <BTN_0>;
35 };
36
37 user-pb1x {
38 label = "user_pb1x";
39 linux,code = <BTN_1>;
40 interrupt-parent = <&gsc>;
41 interrupts = <0>;
42 };
43
44 key-erased {
45 label = "key-erased";
46 linux,code = <BTN_2>;
47 interrupt-parent = <&gsc>;
48 interrupts = <1>;
49 };
50
51 eeprom-wp {
52 label = "eeprom_wp";
53 linux,code = <BTN_3>;
54 interrupt-parent = <&gsc>;
55 interrupts = <2>;
56 };
57
58 tamper {
59 label = "tamper";
60 linux,code = <BTN_4>;
61 interrupt-parent = <&gsc>;
62 interrupts = <5>;
63 };
64
65 switch-hold {
66 label = "switch_hold";
67 linux,code = <BTN_5>;
68 interrupt-parent = <&gsc>;
69 interrupts = <7>;
70 };
71 };
72
73 leds {
74 compatible = "gpio-leds";
75 pinctrl-names = "default";
76 pinctrl-0 = <&pinctrl_gpio_leds>;
77
78 led0: user1 {
79 label = "user1";
80 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
81 default-state = "on";
82 linux,default-trigger = "heartbeat";
83 };
84
85 led1: user2 {
86 label = "user2";
87 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
88 default-state = "off";
89 };
90
91 led2: user3 {
92 label = "user3";
93 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
94 default-state = "off";
95 };
96 };
97
98 memory@10000000 {
99 device_type = "memory";
100 reg = <0x10000000 0x40000000>;
101 };
102
103 pps {
104 compatible = "pps-gpio";
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_pps>;
107 gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
108 };
109
110 reg_3p3v: regulator-3p3v {
111 compatible = "regulator-fixed";
112 regulator-name = "3P3V";
113 regulator-min-microvolt = <3300000>;
114 regulator-max-microvolt = <3300000>;
115 regulator-always-on;
116 };
117
118 reg_usb_vbus: regulator-5p0v {
119 compatible = "regulator-fixed";
120 regulator-name = "usb_vbus";
121 regulator-min-microvolt = <5000000>;
122 regulator-max-microvolt = <5000000>;
Tim Harvey469611e2021-09-29 15:04:22 -0700[diff] [blame]123 gpio = <&gpio4 5 GPIO_ACTIVE_HIGH>;
124 enable-active-high;
Tim Harvey295c8f92021-03-01 14:33:30 -0800[diff] [blame]125 };
126};
127
128&can1 {
129 pinctrl-names = "default";
130 pinctrl-0 = <&pinctrl_flexcan1>;
131 status = "okay";
132};
133
134&ecspi2 {
135 cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
136 pinctrl-names = "default";
137 pinctrl-0 = <&pinctrl_ecspi2>;
138 status = "okay";
139};
140
141&fec {
142 pinctrl-names = "default";
143 pinctrl-0 = <&pinctrl_enet>;
144 phy-mode = "rgmii-id";
Tim Harvey6ce10d52021-05-03 11:21:27 -0700[diff] [blame]145 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
146 phy-reset-duration = <10>;
Tim Harveyb9d23522022-04-29 13:51:02 -0700[diff] [blame]147 phy-reset-post-delay = <300>;
Tim Harvey295c8f92021-03-01 14:33:30 -0800[diff] [blame]148 status = "okay";
149};
150
151&gpmi {
152 pinctrl-names = "default";
153 pinctrl-0 = <&pinctrl_gpmi_nand>;
154 status = "okay";
155};
156
157&i2c1 {
158 clock-frequency = <100000>;
159 pinctrl-names = "default";
160 pinctrl-0 = <&pinctrl_i2c1>;
161 status = "okay";
162
163 gsc: gsc@20 {
164 compatible = "gw,gsc";
165 reg = <0x20>;
166 interrupt-parent = <&gpio1>;
167 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
168 interrupt-controller;
169 #interrupt-cells = <1>;
170 #address-cells = <1>;
171 #size-cells = <0>;
172
173 adc {
174 compatible = "gw,gsc-adc";
175 #address-cells = <1>;
176 #size-cells = <0>;
177
178 channel@0 {
179 gw,mode = <0>;
180 reg = <0x00>;
181 label = "temp";
182 };
183
184 channel@2 {
185 gw,mode = <1>;
186 reg = <0x02>;
187 label = "vdd_vin";
188 };
189
190 channel@5 {
191 gw,mode = <1>;
192 reg = <0x05>;
193 label = "vdd_3p3";
194 };
195
196 channel@8 {
197 gw,mode = <1>;
198 reg = <0x08>;
199 label = "vdd_bat";
200 };
201
202 channel@b {
203 gw,mode = <1>;
204 reg = <0x0b>;
205 label = "vdd_5p0";
206 };
207
208 channel@e {
209 gw,mode = <1>;
210 reg = <0xe>;
211 label = "vdd_arm";
212 };
213
214 channel@11 {
215 gw,mode = <1>;
216 reg = <0x11>;
217 label = "vdd_soc";
218 };
219
220 channel@14 {
221 gw,mode = <1>;
222 reg = <0x14>;
223 label = "vdd_3p0";
224 };
225
226 channel@17 {
227 gw,mode = <1>;
228 reg = <0x17>;
229 label = "vdd_1p5";
230 };
231
232 channel@1d {
233 gw,mode = <1>;
234 reg = <0x1d>;
235 label = "vdd_1p8";
236 };
237
238 channel@20 {
239 gw,mode = <1>;
240 reg = <0x20>;
241 label = "vdd_1p0";
242 };
243
244 channel@23 {
245 gw,mode = <1>;
246 reg = <0x23>;
247 label = "vdd_2p5";
248 };
249 };
250
251 fan-controller@a {
252 compatible = "gw,gsc-fan";
253 #address-cells = <1>;
254 #size-cells = <0>;
255 reg = <0x0a>;
256 };
257 };
258
259 gsc_gpio: gpio@23 {
260 compatible = "nxp,pca9555";
261 reg = <0x23>;
262 gpio-controller;
263 #gpio-cells = <2>;
264 interrupt-parent = <&gsc>;
265 interrupts = <4>;
266 };
267
268 eeprom@50 {
269 compatible = "atmel,24c02";
270 reg = <0x50>;
271 pagesize = <16>;
272 };
273
274 eeprom@51 {
275 compatible = "atmel,24c02";
276 reg = <0x51>;
277 pagesize = <16>;
278 };
279
280 eeprom@52 {
281 compatible = "atmel,24c02";
282 reg = <0x52>;
283 pagesize = <16>;
284 };
285
286 eeprom@53 {
287 compatible = "atmel,24c02";
288 reg = <0x53>;
289 pagesize = <16>;
290 };
291
292 rtc@68 {
293 compatible = "dallas,ds1672";
294 reg = <0x68>;
295 };
296};
297
298&i2c2 {
299 clock-frequency = <100000>;
300 pinctrl-names = "default";
301 pinctrl-0 = <&pinctrl_i2c2>;
302 status = "okay";
303};
304
305&i2c3 {
306 clock-frequency = <100000>;
307 pinctrl-names = "default";
308 pinctrl-0 = <&pinctrl_i2c3>;
309 status = "okay";
310
311 accel@19 {
312 pinctrl-names = "default";
313 pinctrl-0 = <&pinctrl_accel>;
314 compatible = "st,lis2de12";
315 reg = <0x19>;
316 st,drdy-int-pin = <1>;
317 interrupt-parent = <&gpio7>;
318 interrupts = <13 0>;
319 interrupt-names = "INT1";
320 };
321};
322
323&pcie {
324 pinctrl-names = "default";
325 pinctrl-0 = <&pinctrl_pcie>;
326 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
327 status = "okay";
328};
329
330&pwm1 {
331 pinctrl-names = "default";
332 pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */
333 status = "disabled";
334};
335
336&pwm2 {
337 pinctrl-names = "default";
338 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
339 status = "disabled";
340};
341
342&pwm3 {
343 pinctrl-names = "default";
344 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
345 status = "disabled";
346};
347
348&pwm4 {
349 pinctrl-names = "default";
350 pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
351 status = "disabled";
352};
353
354&uart1 {
355 pinctrl-names = "default";
356 pinctrl-0 = <&pinctrl_uart1>;
357 rts-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>;
358 status = "okay";
359};
360
361&uart2 {
362 pinctrl-names = "default";
363 pinctrl-0 = <&pinctrl_uart2>;
364 status = "okay";
365};
366
367&uart5 {
368 pinctrl-names = "default";
369 pinctrl-0 = <&pinctrl_uart5>;
370 status = "okay";
371};
372
373&usbotg {
374 vbus-supply = <&reg_usb_vbus>;
375 pinctrl-names = "default";
376 pinctrl-0 = <&pinctrl_usbotg>;
377 disable-over-current;
378 dr_mode = "host";
379 status = "okay";
380};
381
382&usbh1 {
383 vbus-supply = <&reg_usb_vbus>;
Tim Harvey469611e2021-09-29 15:04:22 -0700[diff] [blame]384 pinctrl-names = "default";
385 pinctrl-0 = <&pinctrl_usbh1>;
Tim Harvey295c8f92021-03-01 14:33:30 -0800[diff] [blame]386 status = "okay";
387};
388
389&usdhc3 {
390 pinctrl-names = "default", "state_100mhz", "state_200mhz";
391 pinctrl-0 = <&pinctrl_usdhc3>;
392 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
393 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
394 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
395 vmmc-supply = <&reg_3p3v>;
396 no-1-8-v; /* firmware will remove if board revision supports */
397 status = "okay";
398};
399
400&wdog1 {
401 status = "disabled";
402};
403
404&wdog2 {
405 pinctrl-names = "default";
406 pinctrl-0 = <&pinctrl_wdog>;
407 fsl,ext-reset-output;
408 status = "okay";
409};
410
411&iomuxc {
412 pinctrl_accel: accelmuxgrp {
413 fsl,pins = <
414 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1
415 >;
416 };
417
418 pinctrl_enet: enetgrp {
419 fsl,pins = <
420 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
421 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
422 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
423 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
424 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
425 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
426 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
427 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
428 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
429 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
430 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
431 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
432 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
433 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
434 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
Tim Harvey6ce10d52021-05-03 11:21:27 -0700[diff] [blame]435 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
Tim Harvey295c8f92021-03-01 14:33:30 -0800[diff] [blame]436 >;
437 };
438
439 pinctrl_ecspi2: escpi2grp {
440 fsl,pins = <
441 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
442 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
443 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
444 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1
445 >;
446 };
447
448 pinctrl_flexcan1: flexcan1grp {
449 fsl,pins = <
450 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
451 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
452 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0
453 >;
454 };
455
456 pinctrl_gpio_leds: gpioledsgrp {
457 fsl,pins = <
458 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
459 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
460 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
461 >;
462 };
463
464 pinctrl_gpmi_nand: gpminandgrp {
465 fsl,pins = <
466 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
467 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
468 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
469 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
470 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
471 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
472 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
473 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
474 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
475 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
476 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
477 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
478 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
479 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
480 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
481 >;
482 };
483
484 pinctrl_i2c1: i2c1grp {
485 fsl,pins = <
486 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
487 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
488 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0
489 >;
490 };
491
492 pinctrl_i2c2: i2c2grp {
493 fsl,pins = <
494 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
495 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
496 >;
497 };
498
499 pinctrl_i2c3: i2c3grp {
500 fsl,pins = <
501 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
502 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
503 >;
504 };
505
506 pinctrl_pcie: pciegrp {
507 fsl,pins = <
508 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
509 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
510 >;
511 };
512
513 pinctrl_pps: ppsgrp {
514 fsl,pins = <
515 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1
516 >;
517 };
518
519 pinctrl_pwm1: pwm1grp {
520 fsl,pins = <
521 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
522 >;
523 };
524
525 pinctrl_pwm2: pwm2grp {
526 fsl,pins = <
527 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
528 >;
529 };
530
531 pinctrl_pwm3: pwm3grp {
532 fsl,pins = <
533 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
534 >;
535 };
536
537 pinctrl_pwm4: pwm4grp {
538 fsl,pins = <
539 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
540 >;
541 };
542
543 pinctrl_uart1: uart1grp {
544 fsl,pins = <
545 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
546 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
547 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b1
548 >;
549 };
550
551 pinctrl_uart2: uart2grp {
552 fsl,pins = <
553 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
554 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
555 MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b1
556 >;
557 };
558
559 pinctrl_uart5: uart5grp {
560 fsl,pins = <
561 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
562 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
563 >;
564 };
565
Tim Harvey469611e2021-09-29 15:04:22 -0700[diff] [blame]566 pinctrl_usbh1: usbh1grp {
567 fsl,pins = <
568 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
569 >;
570 };
571
Tim Harvey295c8f92021-03-01 14:33:30 -0800[diff] [blame]572 pinctrl_usbotg: usbotggrp {
573 fsl,pins = <
574 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059
575 >;
576 };
577
578 pinctrl_usdhc3: usdhc3grp {
579 fsl,pins = <
580 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
581 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
582 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
583 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
584 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
585 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
586 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
587 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
588 >;
589 };
590
591 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
592 fsl,pins = <
593 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
594 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
595 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
596 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
597 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
598 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
599 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
600 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
601 >;
602 };
603
604 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
605 fsl,pins = <
606 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
607 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
608 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
609 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
610 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
611 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
612 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
613 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
614 >;
615 };
616
617 pinctrl_wdog: wdoggrp {
618 fsl,pins = <
619 MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0
620 >;
621 };
622};