Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Prafulla Wadaskar | e565fda | 2009-06-20 11:01:52 +0200 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2009 |
| 4 | * Marvell Semiconductor <www.marvell.com> |
| 5 | * Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
Prafulla Wadaskar | e565fda | 2009-06-20 11:01:52 +0200 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef _ASM_CACHE_H |
| 9 | #define _ASM_CACHE_H |
| 10 | |
| 11 | #include <asm/system.h> |
| 12 | |
David Feng | 85fd5f1 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 13 | #ifndef CONFIG_ARM64 |
| 14 | |
Prafulla Wadaskar | e565fda | 2009-06-20 11:01:52 +0200 | [diff] [blame] | 15 | /* |
| 16 | * Invalidate L2 Cache using co-proc instruction |
| 17 | */ |
Tom Rini | 1c640a6 | 2017-03-18 09:01:44 -0400 | [diff] [blame] | 18 | #if CONFIG_IS_ENABLED(SYS_THUMB_BUILD) |
Albert ARIBAUD | a382322 | 2015-10-23 18:06:40 +0200 | [diff] [blame] | 19 | void invalidate_l2_cache(void); |
| 20 | #else |
Prafulla Wadaskar | e565fda | 2009-06-20 11:01:52 +0200 | [diff] [blame] | 21 | static inline void invalidate_l2_cache(void) |
| 22 | { |
| 23 | unsigned int val=0; |
| 24 | |
| 25 | asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache" |
| 26 | : : "r" (val) : "cc"); |
| 27 | isb(); |
| 28 | } |
Albert ARIBAUD | a382322 | 2015-10-23 18:06:40 +0200 | [diff] [blame] | 29 | #endif |
Kim, Heung Jun | 3b5ac95 | 2009-06-20 11:02:17 +0200 | [diff] [blame] | 30 | |
Simon Glass | 8540658 | 2016-06-19 19:43:01 -0600 | [diff] [blame] | 31 | int check_cache_range(unsigned long start, unsigned long stop); |
| 32 | |
Kim, Heung Jun | 3b5ac95 | 2009-06-20 11:02:17 +0200 | [diff] [blame] | 33 | void l2_cache_enable(void); |
| 34 | void l2_cache_disable(void); |
Vincent Stehlé | 313fe56 | 2013-03-04 20:04:43 +0000 | [diff] [blame] | 35 | void set_section_dcache(int section, enum dcache_option option); |
Kim, Heung Jun | 3b5ac95 | 2009-06-20 11:02:17 +0200 | [diff] [blame] | 36 | |
Jeroen Hofstee | d746077 | 2014-06-23 22:07:04 +0200 | [diff] [blame] | 37 | void arm_init_before_mmu(void); |
| 38 | void arm_init_domains(void); |
| 39 | void cpu_cache_initialization(void); |
R Sricharan | 0871607 | 2013-03-04 20:04:44 +0000 | [diff] [blame] | 40 | void dram_bank_mmu_setup(int bank); |
David Feng | 85fd5f1 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 41 | |
| 42 | #endif |
| 43 | |
Anton Staaf | 13b6b59 | 2011-10-17 16:46:03 -0700 | [diff] [blame] | 44 | /* |
Tom Rini | 84f9b61 | 2016-08-22 08:22:17 -0400 | [diff] [blame] | 45 | * The value of the largest data cache relevant to DMA operations shall be set |
| 46 | * for us in CONFIG_SYS_CACHELINE_SIZE. In some cases this may be a larger |
| 47 | * value than found in the L1 cache but this is OK to use in terms of |
| 48 | * alignment. |
Anton Staaf | 13b6b59 | 2011-10-17 16:46:03 -0700 | [diff] [blame] | 49 | */ |
Anton Staaf | 13b6b59 | 2011-10-17 16:46:03 -0700 | [diff] [blame] | 50 | #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE |
Anton Staaf | 13b6b59 | 2011-10-17 16:46:03 -0700 | [diff] [blame] | 51 | |
Prafulla Wadaskar | e565fda | 2009-06-20 11:01:52 +0200 | [diff] [blame] | 52 | #endif /* _ASM_CACHE_H */ |