blob: fa87cb4e34518456fcd1c307a0775bcadacaa99b [file] [log] [blame]
Aaron Williamsb2ea8182020-06-30 12:08:56 +02001/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2020 Stefan Roese <sr@denx.de>
4 */
5
6#include <config.h>
7#include <asm-offsets.h>
8#include <asm/cacheops.h>
9#include <asm/regdef.h>
10#include <asm/mipsregs.h>
11#include <asm/addrspace.h>
12#include <asm/asm.h>
13
14 .set noreorder
15
16LEAF(lowlevel_init)
17 jr ra
18 nop
19 END(lowlevel_init)
Stefan Roese15ba8022020-06-30 12:33:17 +020020
21LEAF(mips_mach_early_init)
22
23 move s0, ra
24
25 bal __dummy
26 nop
27
28__dummy:
29 /* Get the actual address that we are running at */
30 PTR_LA a7, __dummy
31 dsubu t3, ra, a7 /* t3 now has reloc offset */
32
33 PTR_LA t1, _start
34 daddu t0, t1, t3 /* t0 now has actual address of _start */
35
36 /* Calculate end address of copy loop */
37 PTR_LA t2, _end
38 daddiu t2, t2, 0x4000 /* Increase size to include appended DTB */
39 daddiu t2, t2, 127
40 ins t2, zero, 0, 7 /* Round up to cache line for memcpy */
41
42 /* Copy ourself to the L2 cache from flash, 32 bytes at a time */
431:
44 ld a0, 0(t0)
45 ld a1, 8(t0)
46 ld a2, 16(t0)
47 ld a3, 24(t0)
48 sd a0, 0(t1)
49 sd a1, 8(t1)
50 sd a2, 16(t1)
51 sd a3, 24(t1)
52 addiu t0, 32
53 addiu t1, 32
54 bne t1, t2, 1b
55 nop
56
57 sync
58
59 /*
60 * Return to start.S now running from TEXT_BASE, which points
61 * to DRAM address space, which effectively is L2 cache now.
62 * This speeds up the init process extremely, especially the
63 * DDR init code.
64 */
65 dsubu s0, s0, t3 /* Fixup return address with reloc offset */
66 jr.hb s0 /* Jump back with hazard barrier */
67 nop
68
69 END(mips_mach_early_init)