| Simon Glass | dc79691 | 2019-12-08 17:32:10 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright (C) 2017 Intel Corporation. |
| 4 | * Take from coreboot project file of the same name |
| 5 | */ |
| 6 | |
| 7 | #ifndef _ASM_ARCH_SYSTEMAGENT_H |
| 8 | #define _ASM_ARCH_SYSTEMAGENT_H |
| 9 | |
| 10 | /* Device 0:0.0 PCI configuration space */ |
| Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 11 | #include <linux/bitops.h> |
| Simon Glass | dc79691 | 2019-12-08 17:32:10 -0700 | [diff] [blame] | 12 | #define MCHBAR 0x48 |
| 13 | |
| 14 | /* RAPL Package Power Limit register under MCHBAR */ |
| 15 | #define PUNIT_THERMAL_DEVICE_IRQ 0x700C |
| 16 | #define PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER 0x18 |
| 17 | #define PUINT_THERMAL_DEVICE_IRQ_LOCK 0x80000000 |
| 18 | #define BIOS_RESET_CPL 0x7078 |
| 19 | #define PCODE_INIT_DONE BIT(8) |
| 20 | #define MCHBAR_RAPL_PPL 0x70A8 |
| 21 | #define CORE_DISABLE_MASK 0x7168 |
| 22 | #define CAPID0_A 0xE4 |
| 23 | #define VTD_DISABLE BIT(23) |
| 24 | #define DEFVTBAR 0x6c80 |
| 25 | #define GFXVTBAR 0x6c88 |
| 26 | #define VTBAR_ENABLED 0x01 |
| 27 | #define VTBAR_MASK GENMASK_ULL(39, 12) |
| 28 | #define VTBAR_SIZE 0x1000 |
| 29 | |
| 30 | /** |
| 31 | * enable_bios_reset_cpl() - Tell the system agent that memory/power are ready |
| 32 | * |
| 33 | * This should be called when U-Boot has set up the memory and power |
| 34 | * management. |
| 35 | */ |
| 36 | void enable_bios_reset_cpl(void); |
| 37 | |
| 38 | #endif |