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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Tom Warren112a1882011-04-14 12:18:06 +00002/*
Tom Warrenab0cc6b2015-03-04 16:36:00 -07003 * (C) Copyright 2010-2015
Tom Warren112a1882011-04-14 12:18:06 +00004 * NVIDIA Corporation <www.nvidia.com>
Tom Warren112a1882011-04-14 12:18:06 +00005 */
6#include <asm/types.h>
7
8/* Stabilization delays, in usec */
Tom Warren61c6d0e2012-12-11 13:34:15 +00009#define PLL_STABILIZATION_DELAY (300)
Tom Warren112a1882011-04-14 12:18:06 +000010#define IO_STABILIZATION_DELAY (1000)
11
Tom Warren112a1882011-04-14 12:18:06 +000012#define PLLX_ENABLED (1 << 30)
13#define CCLK_BURST_POLICY 0x20008888
14#define SUPER_CCLK_DIVIDER 0x80000000
15
16/* Calculate clock fractional divider value from ref and target frequencies */
Tom Warren61c6d0e2012-12-11 13:34:15 +000017#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2)
Tom Warren112a1882011-04-14 12:18:06 +000018
19/* Calculate clock frequency value from reference and clock divider value */
Tom Warren61c6d0e2012-12-11 13:34:15 +000020#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2))
Tom Warren112a1882011-04-14 12:18:06 +000021
22/* AVP/CPU ID */
23#define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */
Tom Warren61c6d0e2012-12-11 13:34:15 +000024#define PG_UP_TAG_0 0x0
Tom Warren112a1882011-04-14 12:18:06 +000025
Tom Warren61c6d0e2012-12-11 13:34:15 +000026/* AP base physical address of internal SRAM */
27#define NV_PA_BASE_SRAM 0x40000000
Tom Warren112a1882011-04-14 12:18:06 +000028
29#define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100)
30#define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0)
31#define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0)
32
33#define FLOW_CTLR_HALT_COP_EVENTS (NV_PA_FLOW_BASE + 4)
34#define FLOW_MODE_STOP 2
35#define HALT_COP_EVENT_JTAG (1 << 28)
36#define HALT_COP_EVENT_IRQ_1 (1 << 11)
37#define HALT_COP_EVENT_FIQ_1 (1 << 9)
38
Simon Glassec8dab42011-11-05 03:56:50 +000039/* This is the main entry into U-Boot, used by the Cortex-A9 */
40extern void _start(void);
Simon Glass1fed82a2012-04-02 13:18:50 +000041
42/**
Tom Warren8b817112013-04-10 10:32:32 -070043 * Works out the SOC/SKU type used for clocks settings
Simon Glass1fed82a2012-04-02 13:18:50 +000044 *
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +010045 * Return: SOC type - see TEGRA_SOC...
Simon Glass1fed82a2012-04-02 13:18:50 +000046 */
Tom Warren8b817112013-04-10 10:32:32 -070047int tegra_get_chip_sku(void);
48
49/**
50 * Returns the pure SOC (chip ID) from the HIDREV register
51 *
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +010052 * Return: SOC ID - see CHIPID_TEGRAxx...
Tom Warren8b817112013-04-10 10:32:32 -070053 */
54int tegra_get_chip(void);
55
56/**
57 * Returns the SKU ID from the sku_info register
58 *
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +010059 * Return: SKU ID - see SKU_ID_Txx...
Tom Warren8b817112013-04-10 10:32:32 -070060 */
61int tegra_get_sku_info(void);
62
63/* Do any chip-specific cache config */
Tom Warren82b51342013-03-25 16:22:26 -070064void config_cache(void);
Bryan Wu97adb222014-06-24 11:45:29 +090065
Stephen Warren8d1fb312015-01-19 16:25:52 -070066#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
67bool tegra_cpu_is_non_secure(void);
68#endif