Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / e42015b3e9ee7916e9003c70ca1eda62c1f0fb40 / . / arch / arm / include / asm / arch-imx8ulp / pcc.h
blob: d9b2d7c2998501cb992b522aac476daf3f5850cf [file] [log] [blame]
Peng Fan690eea12021-08-07 16:00:45 +0800[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright 2021 NXP
4 */
5
6#ifndef _ASM_ARCH_IMX8ULP_PCC_H
7#define _ASM_ARCH_IMX8ULP_PCC_H
8
9#include <asm/arch/cgc.h>
10
Alice Guo23ee0e12021-10-29 09:46:29 +0800[diff] [blame]11enum pcc1_entry {
12 ADC1_PCC1_SLOT = 34,
13};
14
Peng Fan690eea12021-08-07 16:00:45 +0800[diff] [blame]15enum pcc3_entry {
16 DMA1_MP_PCC3_SLOT = 1,
17 DMA1_CH0_PCC3_SLOT = 2,
18 DMA1_CH1_PCC3_SLOT = 3,
19 DMA1_CH2_PCC3_SLOT = 4,
20 DMA1_CH3_PCC3_SLOT = 5,
21 DMA1_CH4_PCC3_SLOT = 6,
22 DMA1_CH5_PCC3_SLOT = 7,
23 DMA1_CH6_PCC3_SLOT = 8,
24 DMA1_CH7_PCC3_SLOT = 9,
25 DMA1_CH8_PCC3_SLOT = 10,
26 DMA1_CH9_PCC3_SLOT = 11,
27 DMA1_CH10_PCC3_SLOT = 12,
28 DMA1_CH11_PCC3_SLOT = 13,
29 DMA1_CH12_PCC3_SLOT = 14,
30 DMA1_CH13_PCC3_SLOT = 15,
31 DMA1_CH14_PCC3_SLOT = 16,
32 DMA1_CH15_PCC3_SLOT = 17,
33 DMA1_CH16_PCC3_SLOT = 18,
34 DMA1_CH17_PCC3_SLOT = 19,
35 DMA1_CH18_PCC3_SLOT = 20,
36 DMA1_CH19_PCC3_SLOT = 21,
37 DMA1_CH20_PCC3_SLOT = 22,
38 DMA1_CH21_PCC3_SLOT = 23,
39 DMA1_CH22_PCC3_SLOT = 24,
40 DMA1_CH23_PCC3_SLOT = 25,
41 DMA1_CH24_PCC3_SLOT = 26,
42 DMA1_CH25_PCC3_SLOT = 27,
43 DMA1_CH26_PCC3_SLOT = 28,
44 DMA1_CH27_PCC3_SLOT = 29,
45 DMA1_CH28_PCC3_SLOT = 30,
46 DMA1_CH29_PCC3_SLOT = 31,
47 DMA1_CH30_PCC3_SLOT = 32,
48 DMA1_CH31_PCC3_SLOT = 33,
49 MU0_B_PCC3_SLOT = 34,
50 MU3_A_PCC3_SLOT = 35,
51 LLWU1_PCC3_SLOT = 38,
52 UPOWER_PCC3_SLOT = 40,
53 WDOG3_PCC3_SLOT = 42,
54 WDOG4_PCC3_SLOT = 43,
Peng Fane6129042022-04-06 14:30:10 +0800[diff] [blame]55 CAAM_PCC3_SLOT = 46,
Peng Fan690eea12021-08-07 16:00:45 +0800[diff] [blame]56 XRDC_MGR_PCC3_SLOT = 47,
57 SEMA42_1_PCC3_SLOT = 48,
58 ROMCP1_PCC3_SLOT = 49,
59 LPIT1_PCC3_SLOT = 50,
60 TPM4_PCC3_SLOT = 51,
61 TPM5_PCC3_SLOT = 52,
62 FLEXIO1_PCC3_SLOT = 53,
63 I3C2_PCC3_SLOT = 54,
64 LPI2C4_PCC3_SLOT = 55,
65 LPI2C5_PCC3_SLOT = 56,
66 LPUART4_PCC3_SLOT = 57,
67 LPUART5_PCC3_SLOT = 58,
68 LPSPI4_PCC3_SLOT = 59,
69 LPSPI5_PCC3_SLOT = 60,
70};
71
72enum pcc4_entry {
73 FLEXSPI2_PCC4_SLOT = 1,
74 TPM6_PCC4_SLOT = 2,
75 TPM7_PCC4_SLOT = 3,
76 LPI2C6_PCC4_SLOT = 4,
77 LPI2C7_PCC4_SLOT = 5,
78 LPUART6_PCC4_SLOT = 6,
79 LPUART7_PCC4_SLOT = 7,
80 SAI4_PCC4_SLOT = 8,
81 SAI5_PCC4_SLOT = 9,
82 PCTLE_PCC4_SLOT = 10,
83 PCTLF_PCC4_SLOT = 11,
84 SDHC0_PCC4_SLOT = 13,
85 SDHC1_PCC4_SLOT = 14,
86 SDHC2_PCC4_SLOT = 15,
87 USB0_PCC4_SLOT = 16,
88 USBPHY_PCC4_SLOT = 17,
89 USB1_PCC4_SLOT = 18,
90 USB1PHY_PCC4_SLOT = 19,
91 USB_XBAR_PCC4_SLOT = 20,
92 ENET_PCC4_SLOT = 21,
93 SFA1_PCC4_SLOT = 22,
94 RGPIOE_PCC4_SLOT = 30,
95 RGPIOF_PCC4_SLOT = 31,
96};
97
Ye Lida0469d2021-10-29 09:46:18 +0800[diff] [blame]98enum pcc5_entry {
99 DMA2_MP_PCC5_SLOT = 0,
100 DMA2_CH0_PCC5_SLOT = 1,
101 DMA2_CH1_PCC5_SLOT = 2,
102 DMA2_CH2_PCC5_SLOT = 3,
103 DMA2_CH3_PCC5_SLOT = 4,
104 DMA2_CH4_PCC5_SLOT = 5,
105 DMA2_CH5_PCC5_SLOT = 6,
106 DMA2_CH6_PCC5_SLOT = 7,
107 DMA2_CH7_PCC5_SLOT = 8,
108 DMA2_CH8_PCC5_SLOT = 9,
109 DMA2_CH9_PCC5_SLOT = 10,
110 DMA2_CH10_PCC5_SLOT = 11,
111 DMA2_CH11_PCC5_SLOT = 12,
112 DMA2_CH12_PCC5_SLOT = 13,
113 DMA2_CH13_PCC5_SLOT = 14,
114 DMA2_CH14_PCC5_SLOT = 15,
115 DMA2_CH15_PCC5_SLOT = 16,
116 DMA2_CH16_PCC5_SLOT = 17,
117 DMA2_CH17_PCC5_SLOT = 18,
118 DMA2_CH18_PCC5_SLOT = 19,
119 DMA2_CH19_PCC5_SLOT = 20,
120 DMA2_CH20_PCC5_SLOT = 21,
121 DMA2_CH21_PCC5_SLOT = 22,
122 DMA2_CH22_PCC5_SLOT = 23,
123 DMA2_CH23_PCC5_SLOT = 24,
124 DMA2_CH24_PCC5_SLOT = 25,
125 DMA2_CH25_PCC5_SLOT = 26,
126 DMA2_CH26_PCC5_SLOT = 27,
127 DMA2_CH27_PCC5_SLOT = 28,
128 DMA2_CH28_PCC5_SLOT = 29,
129 DMA2_CH29_PCC5_SLOT = 30,
130 DMA2_CH30_PCC5_SLOT = 31,
131 DMA2_CH31_PCC5_SLOT = 32,
132 MU2_B_PCC5_SLOT = 33,
133 MU3_B_PCC5_SLOT = 34,
134 SEMA42_2_PCC5_SLOT = 35,
135 CMC2_PCC5_SLOT = 36,
136 AVD_SIM_PCC5_SLOT = 37,
137 LPAV_CGC_PCC5_SLOT = 38,
138 PCC5_PCC5_SLOT = 39,
139 TPM8_PCC5_SLOT = 40,
140 SAI6_PCC5_SLOT = 41,
141 SAI7_PCC5_SLOT = 42,
142 SPDIF_PCC5_SLOT = 43,
143 ISI_PCC5_SLOT = 44,
144 CSI_REGS_PCC5_SLOT = 45,
145 CSI_PCC5_SLOT = 47,
146 DSI_PCC5_SLOT = 48,
147 WDOG5_PCC5_SLOT = 50,
148 EPDC_PCC5_SLOT = 51,
149 PXP_PCC5_SLOT = 52,
150 SFA2_PCC5_SLOT = 53,
151 GPU2D_PCC5_SLOT = 60,
152 GPU3D_PCC5_SLOT = 61,
153 DCNANO_PCC5_SLOT = 62,
154 LPDDR4_PCC5_SLOT = 66,
155 CSI_CLK_UI_PCC5_SLOT = 67,
156 CSI_CLK_ESC_PCC5_SLOT = 68,
157 RGPIOD_PCC5_SLOT = 69,
158};
159
Peng Fan690eea12021-08-07 16:00:45 +0800[diff] [blame]160/* PCC registers */
161#define PCC_PR_OFFSET 31
162#define PCC_PR_MASK (0x1 << PCC_PR_OFFSET)
163#define PCC_CGC_OFFSET 30
164#define PCC_CGC_MASK (0x1 << PCC_CGC_OFFSET)
165#define PCC_INUSE_OFFSET 29
166#define PCC_INUSE_MASK (0x1 << PCC_INUSE_OFFSET)
167#define PCC_PCS_OFFSET 24
168#define PCC_PCS_MASK (0x7 << PCC_PCS_OFFSET)
169#define PCC_FRAC_OFFSET 3
170#define PCC_FRAC_MASK (0x1 << PCC_FRAC_OFFSET)
171#define PCC_PCD_OFFSET 0
172#define PCC_PCD_MASK (0x7 << PCC_PCD_OFFSET)
173
174enum pcc_clksrc_type {
175 CLKSRC_PER_PLAT = 0,
176 CLKSRC_PER_BUS = 1,
177 CLKSRC_NO_PCS = 2,
178};
179
180enum pcc_div_type {
181 PCC_HAS_DIV,
182 PCC_NO_DIV,
183};
184
185enum pcc_rst_b {
186 PCC_HAS_RST_B,
187 PCC_NO_RST_B,
188};
189
190/* This structure keeps info for each pcc slot */
191struct pcc_entry {
192 u32 pcc_base;
193 u32 pcc_slot;
194 enum pcc_clksrc_type clksrc;
195 enum pcc_div_type div;
196 enum pcc_rst_b rst_b;
197};
198
199int pcc_clock_enable(int pcc_controller, int pcc_clk_slot, bool enable);
Ye Lida0469d2021-10-29 09:46:18 +0800[diff] [blame]200int pcc_clock_sel(int pcc_controller, int pcc_clk_slot, enum cgc_clk src);
Peng Fan690eea12021-08-07 16:00:45 +0800[diff] [blame]201int pcc_clock_div_config(int pcc_controller, int pcc_clk_slot, bool frac, u8 div);
202bool pcc_clock_is_enable(int pcc_controller, int pcc_clk_slot);
Ye Lida0469d2021-10-29 09:46:18 +0800[diff] [blame]203int pcc_clock_get_clksrc(int pcc_controller, int pcc_clk_slot, enum cgc_clk *src);
Peng Fan690eea12021-08-07 16:00:45 +0800[diff] [blame]204int pcc_reset_peripheral(int pcc_controller, int pcc_clk_slot, bool reset);
205u32 pcc_clock_get_rate(int pcc_controller, int pcc_clk_slot);
206#endif