Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 1 | /* |
Jerry Huang | ed41367 | 2011-01-06 23:42:19 -0600 | [diff] [blame] | 2 | * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 3 | * Andy Fleming |
| 4 | * |
| 5 | * Based vaguely on the pxa mmc code: |
| 6 | * (C) Copyright 2003 |
| 7 | * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net |
| 8 | * |
| 9 | * See file CREDITS for list of people who contributed to this |
| 10 | * project. |
| 11 | * |
| 12 | * This program is free software; you can redistribute it and/or |
| 13 | * modify it under the terms of the GNU General Public License as |
| 14 | * published by the Free Software Foundation; either version 2 of |
| 15 | * the License, or (at your option) any later version. |
| 16 | * |
| 17 | * This program is distributed in the hope that it will be useful, |
| 18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 20 | * GNU General Public License for more details. |
| 21 | * |
| 22 | * You should have received a copy of the GNU General Public License |
| 23 | * along with this program; if not, write to the Free Software |
| 24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 25 | * MA 02111-1307 USA |
| 26 | */ |
| 27 | |
| 28 | #include <config.h> |
| 29 | #include <common.h> |
| 30 | #include <command.h> |
Anton Vorontsov | f751a3c | 2009-06-10 00:25:29 +0400 | [diff] [blame] | 31 | #include <hwconfig.h> |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 32 | #include <mmc.h> |
| 33 | #include <part.h> |
| 34 | #include <malloc.h> |
| 35 | #include <mmc.h> |
| 36 | #include <fsl_esdhc.h> |
Anton Vorontsov | f751a3c | 2009-06-10 00:25:29 +0400 | [diff] [blame] | 37 | #include <fdt_support.h> |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 38 | #include <asm/io.h> |
| 39 | |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 40 | DECLARE_GLOBAL_DATA_PTR; |
| 41 | |
| 42 | struct fsl_esdhc { |
| 43 | uint dsaddr; |
| 44 | uint blkattr; |
| 45 | uint cmdarg; |
| 46 | uint xfertyp; |
| 47 | uint cmdrsp0; |
| 48 | uint cmdrsp1; |
| 49 | uint cmdrsp2; |
| 50 | uint cmdrsp3; |
| 51 | uint datport; |
| 52 | uint prsstat; |
| 53 | uint proctl; |
| 54 | uint sysctl; |
| 55 | uint irqstat; |
| 56 | uint irqstaten; |
| 57 | uint irqsigen; |
| 58 | uint autoc12err; |
| 59 | uint hostcapblt; |
| 60 | uint wml; |
Jason Liu | 9919d64 | 2011-11-25 00:18:04 +0000 | [diff] [blame] | 61 | uint mixctrl; |
| 62 | char reserved1[4]; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 63 | uint fevt; |
| 64 | char reserved2[168]; |
| 65 | uint hostver; |
| 66 | char reserved3[780]; |
| 67 | uint scr; |
| 68 | }; |
| 69 | |
| 70 | /* Return the XFERTYP flags for a given command and data packet */ |
| 71 | uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) |
| 72 | { |
| 73 | uint xfertyp = 0; |
| 74 | |
| 75 | if (data) { |
Dipen Dudhat | 5c72f35 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 76 | xfertyp |= XFERTYP_DPSEL; |
| 77 | #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO |
| 78 | xfertyp |= XFERTYP_DMAEN; |
| 79 | #endif |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 80 | if (data->blocks > 1) { |
| 81 | xfertyp |= XFERTYP_MSBSEL; |
| 82 | xfertyp |= XFERTYP_BCEN; |
Jerry Huang | ed41367 | 2011-01-06 23:42:19 -0600 | [diff] [blame] | 83 | #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
| 84 | xfertyp |= XFERTYP_AC12EN; |
| 85 | #endif |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 86 | } |
| 87 | |
| 88 | if (data->flags & MMC_DATA_READ) |
| 89 | xfertyp |= XFERTYP_DTDSEL; |
| 90 | } |
| 91 | |
| 92 | if (cmd->resp_type & MMC_RSP_CRC) |
| 93 | xfertyp |= XFERTYP_CCCEN; |
| 94 | if (cmd->resp_type & MMC_RSP_OPCODE) |
| 95 | xfertyp |= XFERTYP_CICEN; |
| 96 | if (cmd->resp_type & MMC_RSP_136) |
| 97 | xfertyp |= XFERTYP_RSPTYP_136; |
| 98 | else if (cmd->resp_type & MMC_RSP_BUSY) |
| 99 | xfertyp |= XFERTYP_RSPTYP_48_BUSY; |
| 100 | else if (cmd->resp_type & MMC_RSP_PRESENT) |
| 101 | xfertyp |= XFERTYP_RSPTYP_48; |
| 102 | |
Jason Liu | bef0ff0 | 2011-03-22 01:32:31 +0000 | [diff] [blame] | 103 | #ifdef CONFIG_MX53 |
| 104 | if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) |
| 105 | xfertyp |= XFERTYP_CMDTYP_ABORT; |
| 106 | #endif |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 107 | return XFERTYP_CMD(cmd->cmdidx) | xfertyp; |
| 108 | } |
| 109 | |
Dipen Dudhat | 5c72f35 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 110 | #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO |
| 111 | /* |
| 112 | * PIO Read/Write Mode reduce the performace as DMA is not used in this mode. |
| 113 | */ |
Wolfgang Denk | a40545c | 2010-05-09 23:52:59 +0200 | [diff] [blame] | 114 | static void |
Dipen Dudhat | 5c72f35 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 115 | esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data) |
| 116 | { |
Ira Snyder | 66a722e | 2011-12-23 08:30:40 +0000 | [diff] [blame] | 117 | struct fsl_esdhc_cfg *cfg = mmc->priv; |
| 118 | struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; |
Dipen Dudhat | 5c72f35 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 119 | uint blocks; |
| 120 | char *buffer; |
| 121 | uint databuf; |
| 122 | uint size; |
| 123 | uint irqstat; |
| 124 | uint timeout; |
| 125 | |
| 126 | if (data->flags & MMC_DATA_READ) { |
| 127 | blocks = data->blocks; |
| 128 | buffer = data->dest; |
| 129 | while (blocks) { |
| 130 | timeout = PIO_TIMEOUT; |
| 131 | size = data->blocksize; |
| 132 | irqstat = esdhc_read32(®s->irqstat); |
| 133 | while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN) |
| 134 | && --timeout); |
| 135 | if (timeout <= 0) { |
| 136 | printf("\nData Read Failed in PIO Mode."); |
Wolfgang Denk | a40545c | 2010-05-09 23:52:59 +0200 | [diff] [blame] | 137 | return; |
Dipen Dudhat | 5c72f35 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 138 | } |
| 139 | while (size && (!(irqstat & IRQSTAT_TC))) { |
| 140 | udelay(100); /* Wait before last byte transfer complete */ |
| 141 | irqstat = esdhc_read32(®s->irqstat); |
| 142 | databuf = in_le32(®s->datport); |
| 143 | *((uint *)buffer) = databuf; |
| 144 | buffer += 4; |
| 145 | size -= 4; |
| 146 | } |
| 147 | blocks--; |
| 148 | } |
| 149 | } else { |
| 150 | blocks = data->blocks; |
Wolfgang Denk | a40545c | 2010-05-09 23:52:59 +0200 | [diff] [blame] | 151 | buffer = (char *)data->src; |
Dipen Dudhat | 5c72f35 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 152 | while (blocks) { |
| 153 | timeout = PIO_TIMEOUT; |
| 154 | size = data->blocksize; |
| 155 | irqstat = esdhc_read32(®s->irqstat); |
| 156 | while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN) |
| 157 | && --timeout); |
| 158 | if (timeout <= 0) { |
| 159 | printf("\nData Write Failed in PIO Mode."); |
Wolfgang Denk | a40545c | 2010-05-09 23:52:59 +0200 | [diff] [blame] | 160 | return; |
Dipen Dudhat | 5c72f35 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 161 | } |
| 162 | while (size && (!(irqstat & IRQSTAT_TC))) { |
| 163 | udelay(100); /* Wait before last byte transfer complete */ |
| 164 | databuf = *((uint *)buffer); |
| 165 | buffer += 4; |
| 166 | size -= 4; |
| 167 | irqstat = esdhc_read32(®s->irqstat); |
| 168 | out_le32(®s->datport, databuf); |
| 169 | } |
| 170 | blocks--; |
| 171 | } |
| 172 | } |
| 173 | } |
| 174 | #endif |
| 175 | |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 176 | static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) |
| 177 | { |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 178 | int timeout; |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 179 | struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; |
| 180 | struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; |
Wolfgang Denk | a40545c | 2010-05-09 23:52:59 +0200 | [diff] [blame] | 181 | #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO |
| 182 | uint wml_value; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 183 | |
| 184 | wml_value = data->blocksize/4; |
| 185 | |
| 186 | if (data->flags & MMC_DATA_READ) { |
Priyanka Jain | 0244963 | 2011-02-09 09:24:10 +0530 | [diff] [blame] | 187 | if (wml_value > WML_RD_WML_MAX) |
| 188 | wml_value = WML_RD_WML_MAX_VAL; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 189 | |
Roy Zang | e5853af | 2010-02-09 18:23:33 +0800 | [diff] [blame] | 190 | esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 191 | esdhc_write32(®s->dsaddr, (u32)data->dest); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 192 | } else { |
Eric Nelson | 30e9cad | 2012-04-25 14:28:48 +0000 | [diff] [blame] | 193 | flush_dcache_range((ulong)data->src, |
| 194 | (ulong)data->src+data->blocks |
| 195 | *data->blocksize); |
| 196 | |
Priyanka Jain | 0244963 | 2011-02-09 09:24:10 +0530 | [diff] [blame] | 197 | if (wml_value > WML_WR_WML_MAX) |
| 198 | wml_value = WML_WR_WML_MAX_VAL; |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 199 | if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 200 | printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); |
| 201 | return TIMEOUT; |
| 202 | } |
Roy Zang | e5853af | 2010-02-09 18:23:33 +0800 | [diff] [blame] | 203 | |
| 204 | esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, |
| 205 | wml_value << 16); |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 206 | esdhc_write32(®s->dsaddr, (u32)data->src); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 207 | } |
Wolfgang Denk | a40545c | 2010-05-09 23:52:59 +0200 | [diff] [blame] | 208 | #else /* CONFIG_SYS_FSL_ESDHC_USE_PIO */ |
| 209 | if (!(data->flags & MMC_DATA_READ)) { |
| 210 | if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { |
| 211 | printf("\nThe SD card is locked. " |
| 212 | "Can not write to a locked card.\n\n"); |
| 213 | return TIMEOUT; |
| 214 | } |
| 215 | esdhc_write32(®s->dsaddr, (u32)data->src); |
| 216 | } else |
| 217 | esdhc_write32(®s->dsaddr, (u32)data->dest); |
| 218 | #endif /* CONFIG_SYS_FSL_ESDHC_USE_PIO */ |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 219 | |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 220 | esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 221 | |
| 222 | /* Calculate the timeout period for data transactions */ |
Priyanka Jain | c51b40d | 2011-03-03 09:18:56 +0530 | [diff] [blame] | 223 | /* |
| 224 | * 1)Timeout period = (2^(timeout+13)) SD Clock cycles |
| 225 | * 2)Timeout period should be minimum 0.250sec as per SD Card spec |
| 226 | * So, Number of SD Clock cycles for 0.25sec should be minimum |
| 227 | * (SD Clock/sec * 0.25 sec) SD Clock cycles |
| 228 | * = (mmc->tran_speed * 1/4) SD Clock cycles |
| 229 | * As 1) >= 2) |
| 230 | * => (2^(timeout+13)) >= mmc->tran_speed * 1/4 |
| 231 | * Taking log2 both the sides |
| 232 | * => timeout + 13 >= log2(mmc->tran_speed/4) |
| 233 | * Rounding up to next power of 2 |
| 234 | * => timeout + 13 = log2(mmc->tran_speed/4) + 1 |
| 235 | * => timeout + 13 = fls(mmc->tran_speed/4) |
| 236 | */ |
| 237 | timeout = fls(mmc->tran_speed/4); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 238 | timeout -= 13; |
| 239 | |
| 240 | if (timeout > 14) |
| 241 | timeout = 14; |
| 242 | |
| 243 | if (timeout < 0) |
| 244 | timeout = 0; |
| 245 | |
Kumar Gala | 9a878d5 | 2011-01-29 15:36:10 -0600 | [diff] [blame] | 246 | #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 |
| 247 | if ((timeout == 4) || (timeout == 8) || (timeout == 12)) |
| 248 | timeout++; |
| 249 | #endif |
| 250 | |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 251 | esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 252 | |
| 253 | return 0; |
| 254 | } |
| 255 | |
Eric Nelson | 30e9cad | 2012-04-25 14:28:48 +0000 | [diff] [blame] | 256 | static void check_and_invalidate_dcache_range |
| 257 | (struct mmc_cmd *cmd, |
| 258 | struct mmc_data *data) { |
| 259 | unsigned start = (unsigned)data->dest ; |
| 260 | unsigned size = roundup(ARCH_DMA_MINALIGN, |
| 261 | data->blocks*data->blocksize); |
| 262 | unsigned end = start+size ; |
| 263 | invalidate_dcache_range(start, end); |
| 264 | } |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 265 | /* |
| 266 | * Sends a command out on the bus. Takes the mmc pointer, |
| 267 | * a command pointer, and an optional data pointer. |
| 268 | */ |
| 269 | static int |
| 270 | esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) |
| 271 | { |
| 272 | uint xfertyp; |
| 273 | uint irqstat; |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 274 | struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; |
| 275 | volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 276 | |
Jerry Huang | ed41367 | 2011-01-06 23:42:19 -0600 | [diff] [blame] | 277 | #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
| 278 | if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) |
| 279 | return 0; |
| 280 | #endif |
| 281 | |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 282 | esdhc_write32(®s->irqstat, -1); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 283 | |
| 284 | sync(); |
| 285 | |
| 286 | /* Wait for the bus to be idle */ |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 287 | while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) || |
| 288 | (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB)) |
| 289 | ; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 290 | |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 291 | while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA) |
| 292 | ; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 293 | |
| 294 | /* Wait at least 8 SD clock cycles before the next command */ |
| 295 | /* |
| 296 | * Note: This is way more than 8 cycles, but 1ms seems to |
| 297 | * resolve timing issues with some cards |
| 298 | */ |
| 299 | udelay(1000); |
| 300 | |
| 301 | /* Set up for a data transfer if we have one */ |
| 302 | if (data) { |
| 303 | int err; |
| 304 | |
| 305 | err = esdhc_setup_data(mmc, data); |
| 306 | if(err) |
| 307 | return err; |
| 308 | } |
| 309 | |
| 310 | /* Figure out the transfer arguments */ |
| 311 | xfertyp = esdhc_xfertyp(cmd, data); |
| 312 | |
| 313 | /* Send the command */ |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 314 | esdhc_write32(®s->cmdarg, cmd->cmdarg); |
Jason Liu | 9919d64 | 2011-11-25 00:18:04 +0000 | [diff] [blame] | 315 | #if defined(CONFIG_FSL_USDHC) |
| 316 | esdhc_write32(®s->mixctrl, |
| 317 | (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)); |
| 318 | esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000); |
| 319 | #else |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 320 | esdhc_write32(®s->xfertyp, xfertyp); |
Jason Liu | 9919d64 | 2011-11-25 00:18:04 +0000 | [diff] [blame] | 321 | #endif |
Dirk Behme | d8552d6 | 2012-03-26 03:13:05 +0000 | [diff] [blame] | 322 | |
| 323 | /* Mask all irqs */ |
| 324 | esdhc_write32(®s->irqsigen, 0); |
| 325 | |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 326 | /* Wait for the command to complete */ |
Dirk Behme | d8552d6 | 2012-03-26 03:13:05 +0000 | [diff] [blame] | 327 | while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE))) |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 328 | ; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 329 | |
Eric Nelson | 30e9cad | 2012-04-25 14:28:48 +0000 | [diff] [blame] | 330 | if (data && (data->flags & MMC_DATA_READ)) |
| 331 | check_and_invalidate_dcache_range(cmd, data); |
| 332 | |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 333 | irqstat = esdhc_read32(®s->irqstat); |
| 334 | esdhc_write32(®s->irqstat, irqstat); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 335 | |
Dirk Behme | d8552d6 | 2012-03-26 03:13:05 +0000 | [diff] [blame] | 336 | /* Reset CMD and DATA portions on error */ |
| 337 | if (irqstat & (CMD_ERR | IRQSTAT_CTOE)) { |
| 338 | esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) | |
| 339 | SYSCTL_RSTC); |
| 340 | while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC) |
| 341 | ; |
| 342 | |
| 343 | if (data) { |
| 344 | esdhc_write32(®s->sysctl, |
| 345 | esdhc_read32(®s->sysctl) | |
| 346 | SYSCTL_RSTD); |
| 347 | while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD)) |
| 348 | ; |
| 349 | } |
| 350 | } |
| 351 | |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 352 | if (irqstat & CMD_ERR) |
| 353 | return COMM_ERR; |
| 354 | |
| 355 | if (irqstat & IRQSTAT_CTOE) |
| 356 | return TIMEOUT; |
| 357 | |
Dirk Behme | d8552d6 | 2012-03-26 03:13:05 +0000 | [diff] [blame] | 358 | /* Workaround for ESDHC errata ENGcm03648 */ |
| 359 | if (!data && (cmd->resp_type & MMC_RSP_BUSY)) { |
| 360 | int timeout = 2500; |
| 361 | |
| 362 | /* Poll on DATA0 line for cmd with busy signal for 250 ms */ |
| 363 | while (timeout > 0 && !(esdhc_read32(®s->prsstat) & |
| 364 | PRSSTAT_DAT0)) { |
| 365 | udelay(100); |
| 366 | timeout--; |
| 367 | } |
| 368 | |
| 369 | if (timeout <= 0) { |
| 370 | printf("Timeout waiting for DAT0 to go high!\n"); |
| 371 | return TIMEOUT; |
| 372 | } |
| 373 | } |
| 374 | |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 375 | /* Copy the response to the response buffer */ |
| 376 | if (cmd->resp_type & MMC_RSP_136) { |
| 377 | u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0; |
| 378 | |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 379 | cmdrsp3 = esdhc_read32(®s->cmdrsp3); |
| 380 | cmdrsp2 = esdhc_read32(®s->cmdrsp2); |
| 381 | cmdrsp1 = esdhc_read32(®s->cmdrsp1); |
| 382 | cmdrsp0 = esdhc_read32(®s->cmdrsp0); |
Rabin Vincent | b6eed94 | 2009-04-05 13:30:56 +0530 | [diff] [blame] | 383 | cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24); |
| 384 | cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24); |
| 385 | cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24); |
| 386 | cmd->response[3] = (cmdrsp0 << 8); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 387 | } else |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 388 | cmd->response[0] = esdhc_read32(®s->cmdrsp0); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 389 | |
| 390 | /* Wait until all of the blocks are transferred */ |
| 391 | if (data) { |
Dipen Dudhat | 5c72f35 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 392 | #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO |
| 393 | esdhc_pio_read_write(mmc, data); |
| 394 | #else |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 395 | do { |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 396 | irqstat = esdhc_read32(®s->irqstat); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 397 | |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 398 | if (irqstat & IRQSTAT_DTOE) |
| 399 | return TIMEOUT; |
Frans Meulenbroeks | 010ba98 | 2010-07-31 04:45:18 +0000 | [diff] [blame] | 400 | |
| 401 | if (irqstat & DATA_ERR) |
| 402 | return COMM_ERR; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 403 | } while (!(irqstat & IRQSTAT_TC) && |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 404 | (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)); |
Dipen Dudhat | 5c72f35 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 405 | #endif |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 406 | } |
| 407 | |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 408 | esdhc_write32(®s->irqstat, -1); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 409 | |
| 410 | return 0; |
| 411 | } |
| 412 | |
| 413 | void set_sysctl(struct mmc *mmc, uint clock) |
| 414 | { |
| 415 | int sdhc_clk = gd->sdhc_clk; |
| 416 | int div, pre_div; |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 417 | struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; |
| 418 | volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 419 | uint clk; |
| 420 | |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 421 | if (clock < mmc->f_min) |
| 422 | clock = mmc->f_min; |
| 423 | |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 424 | if (sdhc_clk / 16 > clock) { |
| 425 | for (pre_div = 2; pre_div < 256; pre_div *= 2) |
| 426 | if ((sdhc_clk / pre_div) <= (clock * 16)) |
| 427 | break; |
| 428 | } else |
| 429 | pre_div = 2; |
| 430 | |
| 431 | for (div = 1; div <= 16; div++) |
| 432 | if ((sdhc_clk / (div * pre_div)) <= clock) |
| 433 | break; |
| 434 | |
| 435 | pre_div >>= 1; |
| 436 | div -= 1; |
| 437 | |
| 438 | clk = (pre_div << 8) | (div << 4); |
| 439 | |
Kumar Gala | 09876a3 | 2010-03-18 15:51:05 -0500 | [diff] [blame] | 440 | esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 441 | |
| 442 | esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 443 | |
| 444 | udelay(10000); |
| 445 | |
Kumar Gala | 09876a3 | 2010-03-18 15:51:05 -0500 | [diff] [blame] | 446 | clk = SYSCTL_PEREN | SYSCTL_CKEN; |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 447 | |
| 448 | esdhc_setbits32(®s->sysctl, clk); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 449 | } |
| 450 | |
| 451 | static void esdhc_set_ios(struct mmc *mmc) |
| 452 | { |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 453 | struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; |
| 454 | struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 455 | |
| 456 | /* Set the clock speed */ |
| 457 | set_sysctl(mmc, mmc->clock); |
| 458 | |
| 459 | /* Set the bus width */ |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 460 | esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 461 | |
| 462 | if (mmc->bus_width == 4) |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 463 | esdhc_setbits32(®s->proctl, PROCTL_DTW_4); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 464 | else if (mmc->bus_width == 8) |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 465 | esdhc_setbits32(®s->proctl, PROCTL_DTW_8); |
| 466 | |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 467 | } |
| 468 | |
| 469 | static int esdhc_init(struct mmc *mmc) |
| 470 | { |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 471 | struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; |
| 472 | struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 473 | int timeout = 1000; |
| 474 | |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 475 | /* Reset the entire host controller */ |
| 476 | esdhc_write32(®s->sysctl, SYSCTL_RSTA); |
| 477 | |
| 478 | /* Wait until the controller is available */ |
| 479 | while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) |
| 480 | udelay(1000); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 481 | |
Benoît Thébaudeau | c08d11c | 2012-08-13 07:28:16 +0000 | [diff] [blame] | 482 | #ifndef ARCH_MXC |
P.V.Suresh | 7b1868b | 2010-12-04 10:37:23 +0530 | [diff] [blame] | 483 | /* Enable cache snooping */ |
Benoît Thébaudeau | c08d11c | 2012-08-13 07:28:16 +0000 | [diff] [blame] | 484 | esdhc_write32(®s->scr, 0x00000040); |
| 485 | #endif |
P.V.Suresh | 7b1868b | 2010-12-04 10:37:23 +0530 | [diff] [blame] | 486 | |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 487 | esdhc_write32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 488 | |
| 489 | /* Set the initial clock speed */ |
Jerry Huang | 0caea1a | 2010-11-25 17:06:07 +0000 | [diff] [blame] | 490 | mmc_set_clock(mmc, 400000); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 491 | |
| 492 | /* Disable the BRR and BWR bits in IRQSTAT */ |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 493 | esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 494 | |
| 495 | /* Put the PROCTL reg back to the default */ |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 496 | esdhc_write32(®s->proctl, PROCTL_INIT); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 497 | |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 498 | /* Set timout to the maximum value */ |
| 499 | esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 500 | |
Thierry Reding | 8cee4c98 | 2012-01-02 01:15:38 +0000 | [diff] [blame] | 501 | return 0; |
| 502 | } |
| 503 | |
| 504 | static int esdhc_getcd(struct mmc *mmc) |
| 505 | { |
| 506 | struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; |
| 507 | struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; |
| 508 | int timeout = 1000; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 509 | |
Thierry Reding | 8cee4c98 | 2012-01-02 01:15:38 +0000 | [diff] [blame] | 510 | while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout) |
| 511 | udelay(1000); |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 512 | |
Thierry Reding | 8cee4c98 | 2012-01-02 01:15:38 +0000 | [diff] [blame] | 513 | return timeout > 0; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 514 | } |
| 515 | |
Jerry Huang | b7ef756 | 2010-03-18 15:57:06 -0500 | [diff] [blame] | 516 | static void esdhc_reset(struct fsl_esdhc *regs) |
| 517 | { |
| 518 | unsigned long timeout = 100; /* wait max 100 ms */ |
| 519 | |
| 520 | /* reset the controller */ |
| 521 | esdhc_write32(®s->sysctl, SYSCTL_RSTA); |
| 522 | |
| 523 | /* hardware clears the bit when it is done */ |
| 524 | while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) |
| 525 | udelay(1000); |
| 526 | if (!timeout) |
| 527 | printf("MMC/SD: Reset never completed.\n"); |
| 528 | } |
| 529 | |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 530 | int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 531 | { |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 532 | struct fsl_esdhc *regs; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 533 | struct mmc *mmc; |
Li Yang | d4933f2 | 2010-11-25 17:06:09 +0000 | [diff] [blame] | 534 | u32 caps, voltage_caps; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 535 | |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 536 | if (!cfg) |
| 537 | return -1; |
| 538 | |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 539 | mmc = malloc(sizeof(struct mmc)); |
| 540 | |
Jason Liu | 9919d64 | 2011-11-25 00:18:04 +0000 | [diff] [blame] | 541 | sprintf(mmc->name, "FSL_SDHC"); |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 542 | regs = (struct fsl_esdhc *)cfg->esdhc_base; |
| 543 | |
Jerry Huang | b7ef756 | 2010-03-18 15:57:06 -0500 | [diff] [blame] | 544 | /* First reset the eSDHC controller */ |
| 545 | esdhc_reset(regs); |
| 546 | |
Jerry Huang | 4e3bfa0 | 2012-05-17 23:57:02 +0000 | [diff] [blame] | 547 | esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN |
| 548 | | SYSCTL_IPGEN | SYSCTL_CKEN); |
| 549 | |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 550 | mmc->priv = cfg; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 551 | mmc->send_cmd = esdhc_send_cmd; |
| 552 | mmc->set_ios = esdhc_set_ios; |
| 553 | mmc->init = esdhc_init; |
Thierry Reding | 8cee4c98 | 2012-01-02 01:15:38 +0000 | [diff] [blame] | 554 | mmc->getcd = esdhc_getcd; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 555 | |
Li Yang | d4933f2 | 2010-11-25 17:06:09 +0000 | [diff] [blame] | 556 | voltage_caps = 0; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 557 | caps = regs->hostcapblt; |
Roy Zang | 3935661 | 2011-01-07 00:06:47 -0600 | [diff] [blame] | 558 | |
| 559 | #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135 |
| 560 | caps = caps & ~(ESDHC_HOSTCAPBLT_SRS | |
| 561 | ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30); |
| 562 | #endif |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 563 | if (caps & ESDHC_HOSTCAPBLT_VS18) |
Li Yang | d4933f2 | 2010-11-25 17:06:09 +0000 | [diff] [blame] | 564 | voltage_caps |= MMC_VDD_165_195; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 565 | if (caps & ESDHC_HOSTCAPBLT_VS30) |
Li Yang | d4933f2 | 2010-11-25 17:06:09 +0000 | [diff] [blame] | 566 | voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 567 | if (caps & ESDHC_HOSTCAPBLT_VS33) |
Li Yang | d4933f2 | 2010-11-25 17:06:09 +0000 | [diff] [blame] | 568 | voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34; |
| 569 | |
| 570 | #ifdef CONFIG_SYS_SD_VOLTAGE |
| 571 | mmc->voltages = CONFIG_SYS_SD_VOLTAGE; |
| 572 | #else |
| 573 | mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; |
| 574 | #endif |
| 575 | if ((mmc->voltages & voltage_caps) == 0) { |
| 576 | printf("voltage not supported by controller\n"); |
| 577 | return -1; |
| 578 | } |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 579 | |
| 580 | mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; |
| 581 | |
| 582 | if (caps & ESDHC_HOSTCAPBLT_HSS) |
| 583 | mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; |
| 584 | |
| 585 | mmc->f_min = 400000; |
Jerry Huang | 9a95095 | 2010-11-25 17:06:10 +0000 | [diff] [blame] | 586 | mmc->f_max = MIN(gd->sdhc_clk, 52000000); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 587 | |
Fabio Estevam | 1be94b7 | 2011-05-12 09:33:27 +0000 | [diff] [blame] | 588 | mmc->b_max = 0; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 589 | mmc_register(mmc); |
| 590 | |
| 591 | return 0; |
| 592 | } |
| 593 | |
| 594 | int fsl_esdhc_mmc_init(bd_t *bis) |
| 595 | { |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 596 | struct fsl_esdhc_cfg *cfg; |
| 597 | |
| 598 | cfg = malloc(sizeof(struct fsl_esdhc_cfg)); |
| 599 | memset(cfg, 0, sizeof(struct fsl_esdhc_cfg)); |
| 600 | cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; |
| 601 | return fsl_esdhc_initialize(bis, cfg); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 602 | } |
Anton Vorontsov | f751a3c | 2009-06-10 00:25:29 +0400 | [diff] [blame] | 603 | |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 604 | #ifdef CONFIG_OF_LIBFDT |
Anton Vorontsov | f751a3c | 2009-06-10 00:25:29 +0400 | [diff] [blame] | 605 | void fdt_fixup_esdhc(void *blob, bd_t *bd) |
| 606 | { |
| 607 | const char *compat = "fsl,esdhc"; |
Anton Vorontsov | f751a3c | 2009-06-10 00:25:29 +0400 | [diff] [blame] | 608 | |
Chenhui Zhao | 025eab0 | 2011-01-04 17:23:05 +0800 | [diff] [blame] | 609 | #ifdef CONFIG_FSL_ESDHC_PIN_MUX |
Anton Vorontsov | f751a3c | 2009-06-10 00:25:29 +0400 | [diff] [blame] | 610 | if (!hwconfig("esdhc")) { |
Chenhui Zhao | 025eab0 | 2011-01-04 17:23:05 +0800 | [diff] [blame] | 611 | do_fixup_by_compat(blob, compat, "status", "disabled", |
| 612 | 8 + 1, 1); |
| 613 | return; |
Anton Vorontsov | f751a3c | 2009-06-10 00:25:29 +0400 | [diff] [blame] | 614 | } |
Chenhui Zhao | 025eab0 | 2011-01-04 17:23:05 +0800 | [diff] [blame] | 615 | #endif |
Anton Vorontsov | f751a3c | 2009-06-10 00:25:29 +0400 | [diff] [blame] | 616 | |
| 617 | do_fixup_by_compat_u32(blob, compat, "clock-frequency", |
| 618 | gd->sdhc_clk, 1); |
Chenhui Zhao | 025eab0 | 2011-01-04 17:23:05 +0800 | [diff] [blame] | 619 | |
| 620 | do_fixup_by_compat(blob, compat, "status", "okay", |
| 621 | 4 + 1, 1); |
Anton Vorontsov | f751a3c | 2009-06-10 00:25:29 +0400 | [diff] [blame] | 622 | } |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 623 | #endif |