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wdenk1fe2c702003-03-06 21:55:29 +00001/*
2 * (C) Copyright 2002
3 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/* This code should work for both the S3C2400 and the S3C2410
25 * as they seem to have the same I2C controller inside.
26 * The different address mapping is handled by the s3c24xx.h files below.
27 */
28
29#include <common.h>
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +000030#ifdef CONFIG_EXYNOS5
31#include <asm/arch/clk.h>
32#include <asm/arch/cpu.h>
33#else
kevin.morfitt@fearnside-systems.co.uke0d81312009-11-17 18:30:34 +090034#include <asm/arch/s3c24x0_cpu.h>
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +000035#endif
kevin.morfitt@fearnside-systems.co.uk1464f4d2009-10-10 13:33:11 +090036#include <asm/io.h>
wdenk1fe2c702003-03-06 21:55:29 +000037#include <i2c.h>
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +000038#include "s3c24x0_i2c.h"
wdenk1fe2c702003-03-06 21:55:29 +000039
40#ifdef CONFIG_HARD_I2C
41
wdenk7539dea2003-06-19 23:01:32 +000042#define I2C_WRITE 0
43#define I2C_READ 1
wdenk1fe2c702003-03-06 21:55:29 +000044
wdenk7539dea2003-06-19 23:01:32 +000045#define I2C_OK 0
46#define I2C_NOK 1
47#define I2C_NACK 2
kevin.morfitt@fearnside-systems.co.uk1464f4d2009-10-10 13:33:11 +090048#define I2C_NOK_LA 3 /* Lost arbitration */
49#define I2C_NOK_TOUT 4 /* time out */
wdenk1fe2c702003-03-06 21:55:29 +000050
kevin.morfitt@fearnside-systems.co.uk1464f4d2009-10-10 13:33:11 +090051#define I2CSTAT_BSY 0x20 /* Busy bit */
52#define I2CSTAT_NACK 0x01 /* Nack bit */
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +000053#define I2CCON_ACKGEN 0x80 /* Acknowledge generation */
kevin.morfitt@fearnside-systems.co.uk1464f4d2009-10-10 13:33:11 +090054#define I2CCON_IRPND 0x10 /* Interrupt pending bit */
55#define I2C_MODE_MT 0xC0 /* Master Transmit Mode */
56#define I2C_MODE_MR 0x80 /* Master Receive Mode */
57#define I2C_START_STOP 0x20 /* START / STOP */
58#define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */
wdenk1fe2c702003-03-06 21:55:29 +000059
kevin.morfitt@fearnside-systems.co.uk1464f4d2009-10-10 13:33:11 +090060#define I2C_TIMEOUT 1 /* 1 second */
wdenk1fe2c702003-03-06 21:55:29 +000061
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +000062
63static unsigned int g_current_bus; /* Stores Current I2C Bus */
64
65#ifndef CONFIG_EXYNOS5
wdenk7539dea2003-06-19 23:01:32 +000066static int GetI2CSDA(void)
wdenk1fe2c702003-03-06 21:55:29 +000067{
kevin.morfitt@fearnside-systems.co.uk1464f4d2009-10-10 13:33:11 +090068 struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
wdenk7539dea2003-06-19 23:01:32 +000069
wdenkca9bc762003-07-15 07:45:49 +000070#ifdef CONFIG_S3C2410
C Nauman383c43e2010-10-26 23:04:31 +090071 return (readl(&gpio->gpedat) & 0x8000) >> 15;
wdenkca9bc762003-07-15 07:45:49 +000072#endif
73#ifdef CONFIG_S3C2400
C Nauman383c43e2010-10-26 23:04:31 +090074 return (readl(&gpio->pgdat) & 0x0020) >> 5;
wdenkca9bc762003-07-15 07:45:49 +000075#endif
wdenk1fe2c702003-03-06 21:55:29 +000076}
77
wdenk6b58f332003-03-14 20:47:52 +000078#if 0
wdenk7539dea2003-06-19 23:01:32 +000079static void SetI2CSDA(int x)
wdenk1fe2c702003-03-06 21:55:29 +000080{
kevin.morfitt@fearnside-systems.co.uk1464f4d2009-10-10 13:33:11 +090081 rGPEDAT = (rGPEDAT & ~0x8000) | (x & 1) << 15;
wdenk1fe2c702003-03-06 21:55:29 +000082}
wdenk6b58f332003-03-14 20:47:52 +000083#endif
wdenk1fe2c702003-03-06 21:55:29 +000084
wdenk7539dea2003-06-19 23:01:32 +000085static void SetI2CSCL(int x)
wdenk1fe2c702003-03-06 21:55:29 +000086{
kevin.morfitt@fearnside-systems.co.uk1464f4d2009-10-10 13:33:11 +090087 struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
wdenk7539dea2003-06-19 23:01:32 +000088
wdenkca9bc762003-07-15 07:45:49 +000089#ifdef CONFIG_S3C2410
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +000090 writel((readl(&gpio->gpedat) & ~0x4000) |
91 (x & 1) << 14, &gpio->gpedat);
wdenkca9bc762003-07-15 07:45:49 +000092#endif
93#ifdef CONFIG_S3C2400
C Nauman383c43e2010-10-26 23:04:31 +090094 writel((readl(&gpio->pgdat) & ~0x0040) | (x & 1) << 6, &gpio->pgdat);
wdenkca9bc762003-07-15 07:45:49 +000095#endif
wdenk1fe2c702003-03-06 21:55:29 +000096}
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +000097#endif
wdenk1fe2c702003-03-06 21:55:29 +000098
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +000099static int WaitForXfer(struct s3c24x0_i2c *i2c)
wdenk1fe2c702003-03-06 21:55:29 +0000100{
kevin.morfitt@fearnside-systems.co.uk1464f4d2009-10-10 13:33:11 +0900101 int i;
wdenk1fe2c702003-03-06 21:55:29 +0000102
wdenk49c3f672003-10-08 22:33:00 +0000103 i = I2C_TIMEOUT * 10000;
C Nauman383c43e2010-10-26 23:04:31 +0900104 while (!(readl(&i2c->iiccon) & I2CCON_IRPND) && (i > 0)) {
kevin.morfitt@fearnside-systems.co.uk1464f4d2009-10-10 13:33:11 +0900105 udelay(100);
wdenk49c3f672003-10-08 22:33:00 +0000106 i--;
107 }
wdenk1fe2c702003-03-06 21:55:29 +0000108
C Nauman383c43e2010-10-26 23:04:31 +0900109 return (readl(&i2c->iiccon) & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT;
wdenk1fe2c702003-03-06 21:55:29 +0000110}
111
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000112static int IsACK(struct s3c24x0_i2c *i2c)
wdenk1fe2c702003-03-06 21:55:29 +0000113{
C Nauman383c43e2010-10-26 23:04:31 +0900114 return !(readl(&i2c->iicstat) & I2CSTAT_NACK);
wdenk1fe2c702003-03-06 21:55:29 +0000115}
116
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000117static void ReadWriteByte(struct s3c24x0_i2c *i2c)
wdenk1fe2c702003-03-06 21:55:29 +0000118{
C Nauman383c43e2010-10-26 23:04:31 +0900119 writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon);
wdenk1fe2c702003-03-06 21:55:29 +0000120}
121
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000122static struct s3c24x0_i2c *get_base_i2c(void)
123{
124#ifdef CONFIG_EXYNOS5
125 struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c()
126 + (EXYNOS5_I2C_SPACING
127 * g_current_bus));
128 return i2c;
129#else
130 return s3c24x0_get_base_i2c();
131#endif
132}
133
134static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
135{
136 ulong freq, pres = 16, div;
137#ifdef CONFIG_EXYNOS5
138 freq = get_i2c_clk();
139#else
140 freq = get_PCLK();
141#endif
142 /* calculate prescaler and divisor values */
143 if ((freq / pres / (16 + 1)) > speed)
144 /* set prescaler to 512 */
145 pres = 512;
146
147 div = 0;
148 while ((freq / pres / (div + 1)) > speed)
149 div++;
150
151 /* set prescaler, divisor according to freq, also set ACKGEN, IRQ */
152 writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon);
153
154 /* init to SLAVE REVEIVE and set slaveaddr */
155 writel(0, &i2c->iicstat);
156 writel(slaveadd, &i2c->iicadd);
157 /* program Master Transmit (and implicit STOP) */
158 writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
159}
160
Rajeshwari Shindec07c11d2012-07-23 21:23:54 +0000161/*
162 * MULTI BUS I2C support
163 */
164
165#ifdef CONFIG_I2C_MULTI_BUS
166int i2c_set_bus_num(unsigned int bus)
167{
168 struct s3c24x0_i2c *i2c;
169
170 if ((bus < 0) || (bus >= CONFIG_MAX_I2C_NUM)) {
171 debug("Bad bus: %d\n", bus);
172 return -1;
173 }
174
175 g_current_bus = bus;
176 i2c = get_base_i2c();
177 i2c_ch_init(i2c, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
178
179 return 0;
180}
181
182unsigned int i2c_get_bus_num(void)
183{
184 return g_current_bus;
185}
186#endif
187
kevin.morfitt@fearnside-systems.co.uk1464f4d2009-10-10 13:33:11 +0900188void i2c_init(int speed, int slaveadd)
wdenk1fe2c702003-03-06 21:55:29 +0000189{
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000190 struct s3c24x0_i2c *i2c;
191#ifndef CONFIG_EXYNOS5
kevin.morfitt@fearnside-systems.co.uk1464f4d2009-10-10 13:33:11 +0900192 struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000193#endif
kevin.morfitt@fearnside-systems.co.uk1464f4d2009-10-10 13:33:11 +0900194 int i;
wdenk1fe2c702003-03-06 21:55:29 +0000195
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000196 /* By default i2c channel 0 is the current bus */
197 g_current_bus = 0;
198 i2c = get_base_i2c();
wdenk1fe2c702003-03-06 21:55:29 +0000199
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000200 /* wait for some time to give previous transfer a chance to finish */
wdenk49c3f672003-10-08 22:33:00 +0000201 i = I2C_TIMEOUT * 1000;
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000202 while ((readl(&i2c->iicstat) & I2CSTAT_BSY) && (i > 0)) {
kevin.morfitt@fearnside-systems.co.uk1464f4d2009-10-10 13:33:11 +0900203 udelay(1000);
wdenk49c3f672003-10-08 22:33:00 +0000204 i--;
205 }
wdenk1fe2c702003-03-06 21:55:29 +0000206
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000207#ifndef CONFIG_EXYNOS5
C Nauman383c43e2010-10-26 23:04:31 +0900208 if ((readl(&i2c->iicstat) & I2CSTAT_BSY) || GetI2CSDA() == 0) {
wdenkca9bc762003-07-15 07:45:49 +0000209#ifdef CONFIG_S3C2410
C Nauman383c43e2010-10-26 23:04:31 +0900210 ulong old_gpecon = readl(&gpio->gpecon);
wdenkca9bc762003-07-15 07:45:49 +0000211#endif
212#ifdef CONFIG_S3C2400
C Nauman383c43e2010-10-26 23:04:31 +0900213 ulong old_gpecon = readl(&gpio->pgcon);
wdenkca9bc762003-07-15 07:45:49 +0000214#endif
kevin.morfitt@fearnside-systems.co.uk1464f4d2009-10-10 13:33:11 +0900215 /* bus still busy probably by (most) previously interrupted
216 transfer */
wdenk1fe2c702003-03-06 21:55:29 +0000217
wdenkca9bc762003-07-15 07:45:49 +0000218#ifdef CONFIG_S3C2410
wdenk49c3f672003-10-08 22:33:00 +0000219 /* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */
C Nauman383c43e2010-10-26 23:04:31 +0900220 writel((readl(&gpio->gpecon) & ~0xF0000000) | 0x10000000,
221 &gpio->gpecon);
wdenkca9bc762003-07-15 07:45:49 +0000222#endif
223#ifdef CONFIG_S3C2400
wdenk49c3f672003-10-08 22:33:00 +0000224 /* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */
C Nauman383c43e2010-10-26 23:04:31 +0900225 writel((readl(&gpio->pgcon) & ~0x00003c00) | 0x00001000,
226 &gpio->pgcon);
wdenkca9bc762003-07-15 07:45:49 +0000227#endif
wdenk1fe2c702003-03-06 21:55:29 +0000228
wdenk49c3f672003-10-08 22:33:00 +0000229 /* toggle I2CSCL until bus idle */
kevin.morfitt@fearnside-systems.co.uk1464f4d2009-10-10 13:33:11 +0900230 SetI2CSCL(0);
231 udelay(1000);
wdenk49c3f672003-10-08 22:33:00 +0000232 i = 10;
kevin.morfitt@fearnside-systems.co.uk1464f4d2009-10-10 13:33:11 +0900233 while ((i > 0) && (GetI2CSDA() != 1)) {
234 SetI2CSCL(1);
235 udelay(1000);
236 SetI2CSCL(0);
237 udelay(1000);
wdenk49c3f672003-10-08 22:33:00 +0000238 i--;
239 }
kevin.morfitt@fearnside-systems.co.uk1464f4d2009-10-10 13:33:11 +0900240 SetI2CSCL(1);
241 udelay(1000);
wdenk1fe2c702003-03-06 21:55:29 +0000242
wdenk49c3f672003-10-08 22:33:00 +0000243 /* restore pin functions */
wdenkca9bc762003-07-15 07:45:49 +0000244#ifdef CONFIG_S3C2410
C Nauman383c43e2010-10-26 23:04:31 +0900245 writel(old_gpecon, &gpio->gpecon);
wdenkca9bc762003-07-15 07:45:49 +0000246#endif
247#ifdef CONFIG_S3C2400
C Nauman383c43e2010-10-26 23:04:31 +0900248 writel(old_gpecon, &gpio->pgcon);
wdenkca9bc762003-07-15 07:45:49 +0000249#endif
wdenk49c3f672003-10-08 22:33:00 +0000250 }
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000251#endif /* #ifndef CONFIG_EXYNOS5 */
252 i2c_ch_init(i2c, speed, slaveadd);
wdenk1fe2c702003-03-06 21:55:29 +0000253}
254
255/*
wdenk49c3f672003-10-08 22:33:00 +0000256 * cmd_type is 0 for write, 1 for read.
257 *
258 * addr_len can take any value from 0-255, it is only limited
259 * by the char, we could make it larger if needed. If it is
260 * 0 we skip the address write cycle.
261 */
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000262static int i2c_transfer(struct s3c24x0_i2c *i2c,
263 unsigned char cmd_type,
264 unsigned char chip,
265 unsigned char addr[],
266 unsigned char addr_len,
267 unsigned char data[],
268 unsigned short data_len)
wdenk1fe2c702003-03-06 21:55:29 +0000269{
kevin.morfitt@fearnside-systems.co.uk1464f4d2009-10-10 13:33:11 +0900270 int i, result;
wdenk1fe2c702003-03-06 21:55:29 +0000271
wdenk49c3f672003-10-08 22:33:00 +0000272 if (data == 0 || data_len == 0) {
273 /*Don't support data transfer of no length or to address 0 */
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000274 debug("i2c_transfer: bad call\n");
wdenk49c3f672003-10-08 22:33:00 +0000275 return I2C_NOK;
276 }
wdenk1fe2c702003-03-06 21:55:29 +0000277
wdenk49c3f672003-10-08 22:33:00 +0000278 /* Check I2C bus idle */
279 i = I2C_TIMEOUT * 1000;
C Nauman383c43e2010-10-26 23:04:31 +0900280 while ((readl(&i2c->iicstat) & I2CSTAT_BSY) && (i > 0)) {
kevin.morfitt@fearnside-systems.co.uk1464f4d2009-10-10 13:33:11 +0900281 udelay(1000);
wdenk49c3f672003-10-08 22:33:00 +0000282 i--;
283 }
wdenk1fe2c702003-03-06 21:55:29 +0000284
C Nauman383c43e2010-10-26 23:04:31 +0900285 if (readl(&i2c->iicstat) & I2CSTAT_BSY)
wdenk49c3f672003-10-08 22:33:00 +0000286 return I2C_NOK_TOUT;
wdenk1fe2c702003-03-06 21:55:29 +0000287
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000288 writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon);
wdenk49c3f672003-10-08 22:33:00 +0000289 result = I2C_OK;
wdenk1fe2c702003-03-06 21:55:29 +0000290
wdenk49c3f672003-10-08 22:33:00 +0000291 switch (cmd_type) {
wdenk7539dea2003-06-19 23:01:32 +0000292 case I2C_WRITE:
wdenk49c3f672003-10-08 22:33:00 +0000293 if (addr && addr_len) {
C Nauman383c43e2010-10-26 23:04:31 +0900294 writel(chip, &i2c->iicds);
wdenk49c3f672003-10-08 22:33:00 +0000295 /* send START */
kevin.morfitt@fearnside-systems.co.uk1464f4d2009-10-10 13:33:11 +0900296 writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
C Nauman383c43e2010-10-26 23:04:31 +0900297 &i2c->iicstat);
wdenk49c3f672003-10-08 22:33:00 +0000298 i = 0;
299 while ((i < addr_len) && (result == I2C_OK)) {
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000300 result = WaitForXfer(i2c);
C Nauman383c43e2010-10-26 23:04:31 +0900301 writel(addr[i], &i2c->iicds);
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000302 ReadWriteByte(i2c);
wdenk49c3f672003-10-08 22:33:00 +0000303 i++;
304 }
305 i = 0;
306 while ((i < data_len) && (result == I2C_OK)) {
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000307 result = WaitForXfer(i2c);
C Nauman383c43e2010-10-26 23:04:31 +0900308 writel(data[i], &i2c->iicds);
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000309 ReadWriteByte(i2c);
wdenk49c3f672003-10-08 22:33:00 +0000310 i++;
311 }
312 } else {
C Nauman383c43e2010-10-26 23:04:31 +0900313 writel(chip, &i2c->iicds);
wdenk49c3f672003-10-08 22:33:00 +0000314 /* send START */
kevin.morfitt@fearnside-systems.co.uk1464f4d2009-10-10 13:33:11 +0900315 writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
C Nauman383c43e2010-10-26 23:04:31 +0900316 &i2c->iicstat);
wdenk49c3f672003-10-08 22:33:00 +0000317 i = 0;
318 while ((i < data_len) && (result = I2C_OK)) {
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000319 result = WaitForXfer(i2c);
C Nauman383c43e2010-10-26 23:04:31 +0900320 writel(data[i], &i2c->iicds);
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000321 ReadWriteByte(i2c);
wdenk49c3f672003-10-08 22:33:00 +0000322 i++;
323 }
wdenk1fe2c702003-03-06 21:55:29 +0000324 }
wdenk1fe2c702003-03-06 21:55:29 +0000325
wdenk49c3f672003-10-08 22:33:00 +0000326 if (result == I2C_OK)
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000327 result = WaitForXfer(i2c);
wdenk1fe2c702003-03-06 21:55:29 +0000328
wdenk49c3f672003-10-08 22:33:00 +0000329 /* send STOP */
C Nauman383c43e2010-10-26 23:04:31 +0900330 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000331 ReadWriteByte(i2c);
wdenk49c3f672003-10-08 22:33:00 +0000332 break;
wdenk1fe2c702003-03-06 21:55:29 +0000333
wdenk7539dea2003-06-19 23:01:32 +0000334 case I2C_READ:
wdenk49c3f672003-10-08 22:33:00 +0000335 if (addr && addr_len) {
C Nauman383c43e2010-10-26 23:04:31 +0900336 writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
337 writel(chip, &i2c->iicds);
wdenk49c3f672003-10-08 22:33:00 +0000338 /* send START */
C Nauman383c43e2010-10-26 23:04:31 +0900339 writel(readl(&i2c->iicstat) | I2C_START_STOP,
340 &i2c->iicstat);
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000341 result = WaitForXfer(i2c);
342 if (IsACK(i2c)) {
wdenk49c3f672003-10-08 22:33:00 +0000343 i = 0;
344 while ((i < addr_len) && (result == I2C_OK)) {
C Nauman383c43e2010-10-26 23:04:31 +0900345 writel(addr[i], &i2c->iicds);
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000346 ReadWriteByte(i2c);
347 result = WaitForXfer(i2c);
wdenk49c3f672003-10-08 22:33:00 +0000348 i++;
349 }
wdenk1fe2c702003-03-06 21:55:29 +0000350
C Nauman383c43e2010-10-26 23:04:31 +0900351 writel(chip, &i2c->iicds);
wdenk49c3f672003-10-08 22:33:00 +0000352 /* resend START */
kevin.morfitt@fearnside-systems.co.uk1464f4d2009-10-10 13:33:11 +0900353 writel(I2C_MODE_MR | I2C_TXRX_ENA |
C Nauman383c43e2010-10-26 23:04:31 +0900354 I2C_START_STOP, &i2c->iicstat);
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000355 ReadWriteByte(i2c);
356 result = WaitForXfer(i2c);
wdenk49c3f672003-10-08 22:33:00 +0000357 i = 0;
358 while ((i < data_len) && (result == I2C_OK)) {
359 /* disable ACK for final READ */
360 if (i == data_len - 1)
C Nauman383c43e2010-10-26 23:04:31 +0900361 writel(readl(&i2c->iiccon)
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000362 & ~I2CCON_ACKGEN,
363 &i2c->iiccon);
364 ReadWriteByte(i2c);
365 result = WaitForXfer(i2c);
C Nauman383c43e2010-10-26 23:04:31 +0900366 data[i] = readl(&i2c->iicds);
wdenk49c3f672003-10-08 22:33:00 +0000367 i++;
368 }
369 } else {
370 result = I2C_NACK;
371 }
wdenk1fe2c702003-03-06 21:55:29 +0000372
wdenk1fe2c702003-03-06 21:55:29 +0000373 } else {
C Nauman383c43e2010-10-26 23:04:31 +0900374 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
375 writel(chip, &i2c->iicds);
wdenk49c3f672003-10-08 22:33:00 +0000376 /* send START */
C Nauman383c43e2010-10-26 23:04:31 +0900377 writel(readl(&i2c->iicstat) | I2C_START_STOP,
378 &i2c->iicstat);
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000379 result = WaitForXfer(i2c);
wdenk49c3f672003-10-08 22:33:00 +0000380
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000381 if (IsACK(i2c)) {
wdenk49c3f672003-10-08 22:33:00 +0000382 i = 0;
383 while ((i < data_len) && (result == I2C_OK)) {
384 /* disable ACK for final READ */
385 if (i == data_len - 1)
C Nauman383c43e2010-10-26 23:04:31 +0900386 writel(readl(&i2c->iiccon) &
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000387 ~I2CCON_ACKGEN,
388 &i2c->iiccon);
389 ReadWriteByte(i2c);
390 result = WaitForXfer(i2c);
C Nauman383c43e2010-10-26 23:04:31 +0900391 data[i] = readl(&i2c->iicds);
wdenk49c3f672003-10-08 22:33:00 +0000392 i++;
393 }
394 } else {
395 result = I2C_NACK;
396 }
wdenk1fe2c702003-03-06 21:55:29 +0000397 }
wdenk1fe2c702003-03-06 21:55:29 +0000398
wdenk49c3f672003-10-08 22:33:00 +0000399 /* send STOP */
C Nauman383c43e2010-10-26 23:04:31 +0900400 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000401 ReadWriteByte(i2c);
wdenk49c3f672003-10-08 22:33:00 +0000402 break;
wdenk1fe2c702003-03-06 21:55:29 +0000403
404 default:
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000405 debug("i2c_transfer: bad call\n");
wdenk49c3f672003-10-08 22:33:00 +0000406 result = I2C_NOK;
407 break;
408 }
wdenk1fe2c702003-03-06 21:55:29 +0000409
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000410 return result;
wdenk1fe2c702003-03-06 21:55:29 +0000411}
412
kevin.morfitt@fearnside-systems.co.uk1464f4d2009-10-10 13:33:11 +0900413int i2c_probe(uchar chip)
wdenk1fe2c702003-03-06 21:55:29 +0000414{
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000415 struct s3c24x0_i2c *i2c;
wdenk49c3f672003-10-08 22:33:00 +0000416 uchar buf[1];
wdenk1fe2c702003-03-06 21:55:29 +0000417
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000418 i2c = get_base_i2c();
wdenk49c3f672003-10-08 22:33:00 +0000419 buf[0] = 0;
wdenk1fe2c702003-03-06 21:55:29 +0000420
wdenk49c3f672003-10-08 22:33:00 +0000421 /*
422 * What is needed is to send the chip address and verify that the
423 * address was <ACK>ed (i.e. there was a chip at that address which
424 * drove the data line low).
425 */
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000426 return i2c_transfer(i2c, I2C_READ, chip << 1, 0, 0, buf, 1) != I2C_OK;
wdenk1fe2c702003-03-06 21:55:29 +0000427}
428
kevin.morfitt@fearnside-systems.co.uk1464f4d2009-10-10 13:33:11 +0900429int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
wdenk1fe2c702003-03-06 21:55:29 +0000430{
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000431 struct s3c24x0_i2c *i2c;
wdenk49c3f672003-10-08 22:33:00 +0000432 uchar xaddr[4];
433 int ret;
wdenk1fe2c702003-03-06 21:55:29 +0000434
wdenk49c3f672003-10-08 22:33:00 +0000435 if (alen > 4) {
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000436 debug("I2C read: addr len %d not supported\n", alen);
wdenk49c3f672003-10-08 22:33:00 +0000437 return 1;
438 }
wdenk1fe2c702003-03-06 21:55:29 +0000439
wdenk49c3f672003-10-08 22:33:00 +0000440 if (alen > 0) {
441 xaddr[0] = (addr >> 24) & 0xFF;
442 xaddr[1] = (addr >> 16) & 0xFF;
443 xaddr[2] = (addr >> 8) & 0xFF;
444 xaddr[3] = addr & 0xFF;
445 }
wdenk1fe2c702003-03-06 21:55:29 +0000446
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200447#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
wdenk49c3f672003-10-08 22:33:00 +0000448 /*
449 * EEPROM chips that implement "address overflow" are ones
450 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
451 * address and the extra bits end up in the "chip address"
452 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
453 * four 256 byte chips.
454 *
455 * Note that we consider the length of the address field to
456 * still be one byte because the extra address bits are
457 * hidden in the chip address.
458 */
459 if (alen > 0)
kevin.morfitt@fearnside-systems.co.uk1464f4d2009-10-10 13:33:11 +0900460 chip |= ((addr >> (alen * 8)) &
461 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
wdenk1fe2c702003-03-06 21:55:29 +0000462#endif
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000463 i2c = get_base_i2c();
464 ret = i2c_transfer(i2c, I2C_READ, chip << 1, &xaddr[4 - alen], alen,
465 buffer, len);
466 if (ret != 0) {
467 debug("I2c read: failed %d\n", ret);
wdenk49c3f672003-10-08 22:33:00 +0000468 return 1;
469 }
470 return 0;
wdenk1fe2c702003-03-06 21:55:29 +0000471}
472
kevin.morfitt@fearnside-systems.co.uk1464f4d2009-10-10 13:33:11 +0900473int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
wdenk1fe2c702003-03-06 21:55:29 +0000474{
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000475 struct s3c24x0_i2c *i2c;
wdenk49c3f672003-10-08 22:33:00 +0000476 uchar xaddr[4];
wdenk1fe2c702003-03-06 21:55:29 +0000477
wdenk49c3f672003-10-08 22:33:00 +0000478 if (alen > 4) {
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000479 debug("I2C write: addr len %d not supported\n", alen);
wdenk49c3f672003-10-08 22:33:00 +0000480 return 1;
481 }
wdenk1fe2c702003-03-06 21:55:29 +0000482
wdenk49c3f672003-10-08 22:33:00 +0000483 if (alen > 0) {
484 xaddr[0] = (addr >> 24) & 0xFF;
485 xaddr[1] = (addr >> 16) & 0xFF;
486 xaddr[2] = (addr >> 8) & 0xFF;
487 xaddr[3] = addr & 0xFF;
488 }
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200489#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
wdenk49c3f672003-10-08 22:33:00 +0000490 /*
491 * EEPROM chips that implement "address overflow" are ones
492 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
493 * address and the extra bits end up in the "chip address"
494 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
495 * four 256 byte chips.
496 *
497 * Note that we consider the length of the address field to
498 * still be one byte because the extra address bits are
499 * hidden in the chip address.
500 */
501 if (alen > 0)
kevin.morfitt@fearnside-systems.co.uk1464f4d2009-10-10 13:33:11 +0900502 chip |= ((addr >> (alen * 8)) &
503 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
wdenk1fe2c702003-03-06 21:55:29 +0000504#endif
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000505 i2c = get_base_i2c();
wdenk49c3f672003-10-08 22:33:00 +0000506 return (i2c_transfer
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000507 (i2c, I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer,
wdenk49c3f672003-10-08 22:33:00 +0000508 len) != 0);
wdenk1fe2c702003-03-06 21:55:29 +0000509}
kevin.morfitt@fearnside-systems.co.uk1464f4d2009-10-10 13:33:11 +0900510#endif /* CONFIG_HARD_I2C */