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git01.mediatek.com / filogic / uboot / e402b6c9e2dd3c29a25a06f2da08d6dc6be68f2c / . / include / power / max77686_pmic.h
blob: c2a772a8951eea4a2373eef22e849bb745d83e90 [file] [log] [blame]
Rajeshwari Shindee9e8be82012-08-24 00:39:23 +0000[diff] [blame]1/*
2 * Copyright (C) 2012 Samsung Electronics
3 * Rajeshwari Shinde <rajeshwari.s@samsung.com>
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]5 * SPDX-License-Identifier: GPL-2.0+
Rajeshwari Shindee9e8be82012-08-24 00:39:23 +0000[diff] [blame]6 */
7
8#ifndef __MAX77686_H_
9#define __MAX77686_H_
10
Przemyslaw Marczake5ef07f2014-01-22 11:24:11 +0100[diff] [blame]11#include <power/pmic.h>
12
Rajeshwari Shindee9e8be82012-08-24 00:39:23 +0000[diff] [blame]13enum {
14 MAX77686_REG_PMIC_ID = 0x0,
15 MAX77686_REG_PMIC_INTSRC,
16 MAX77686_REG_PMIC_INT1,
17 MAX77686_REG_PMIC_INT2,
18 MAX77686_REG_PMIC_INT1MSK,
19 MAX77686_REG_PMIC_INT2MSK,
20
21 MAX77686_REG_PMIC_STATUS1,
22 MAX77686_REG_PMIC_STATUS2,
23
24 MAX77686_REG_PMIC_PWRON,
25 MAX77686_REG_PMIC_ONOFFDELAY,
26 MAX77686_REG_PMIC_MRSTB,
27
28 MAX77686_REG_PMIC_BUCK1CRTL = 0x10,
29 MAX77686_REG_PMIC_BUCK1OUT,
30 MAX77686_REG_PMIC_BUCK2CTRL1,
31 MAX77686_REG_PMIC_BUCK234FREQ,
32 MAX77686_REG_PMIC_BUCK2DVS1,
33 MAX77686_REG_PMIC_BUCK2DVS2,
34 MAX77686_REG_PMIC_BUCK2DVS3,
35 MAX77686_REG_PMIC_BUCK2DVS4,
36 MAX77686_REG_PMIC_BUCK2DVS5,
37 MAX77686_REG_PMIC_BUCK2DVS6,
38 MAX77686_REG_PMIC_BUCK2DVS7,
39 MAX77686_REG_PMIC_BUCK2DVS8,
40 MAX77686_REG_PMIC_BUCK3CTRL,
Jaehoon Chung88ba8132013-09-30 14:23:37 +0900[diff] [blame]41 MAX77686_REG_PMIC_BUCK3DVS1 = 0x1e,
Rajeshwari Shindee9e8be82012-08-24 00:39:23 +0000[diff] [blame]42 MAX77686_REG_PMIC_BUCK3DVS2,
43 MAX77686_REG_PMIC_BUCK3DVS3,
44 MAX77686_REG_PMIC_BUCK3DVS4,
45 MAX77686_REG_PMIC_BUCK3DVS5,
46 MAX77686_REG_PMIC_BUCK3DVS6,
47 MAX77686_REG_PMIC_BUCK3DVS7,
48 MAX77686_REG_PMIC_BUCK3DVS8,
49 MAX77686_REG_PMIC_BUCK4CTRL1,
50 MAX77686_REG_PMIC_BUCK4DVS1 = 0x28,
51 MAX77686_REG_PMIC_BUCK4DVS2,
52 MAX77686_REG_PMIC_BUCK4DVS3,
53 MAX77686_REG_PMIC_BUCK4DVS4,
54 MAX77686_REG_PMIC_BUCK4DVS5,
55 MAX77686_REG_PMIC_BUCK4DVS6,
56 MAX77686_REG_PMIC_BUCK4DVS7,
57 MAX77686_REG_PMIC_BUCK4DVS8,
58 MAX77686_REG_PMIC_BUCK5CTRL,
59 MAX77686_REG_PMIC_BUCK5OUT,
60 MAX77686_REG_PMIC_BUCK6CRTL,
61 MAX77686_REG_PMIC_BUCK6OUT,
62 MAX77686_REG_PMIC_BUCK7CRTL,
63 MAX77686_REG_PMIC_BUCK7OUT,
64 MAX77686_REG_PMIC_BUCK8CRTL,
65 MAX77686_REG_PMIC_BUCK8OUT,
66 MAX77686_REG_PMIC_BUCK9CRTL,
67 MAX77686_REG_PMIC_BUCK9OUT,
68
69 MAX77686_REG_PMIC_LDO1CTRL1 = 0x40,
70 MAX77686_REG_PMIC_LDO2CTRL1,
71 MAX77686_REG_PMIC_LDO3CTRL1,
72 MAX77686_REG_PMIC_LDO4CTRL1,
73 MAX77686_REG_PMIC_LDO5CTRL1,
74 MAX77686_REG_PMIC_LDO6CTRL1,
75 MAX77686_REG_PMIC_LDO7CTRL1,
76 MAX77686_REG_PMIC_LDO8CTRL1,
77 MAX77686_REG_PMIC_LDO9CTRL1,
78 MAX77686_REG_PMIC_LDO10CTRL1,
79 MAX77686_REG_PMIC_LDO11CTRL1,
80 MAX77686_REG_PMIC_LDO12CTRL1,
81 MAX77686_REG_PMIC_LDO13CTRL1,
82 MAX77686_REG_PMIC_LDO14CTRL1,
83 MAX77686_REG_PMIC_LDO15CTRL1,
84 MAX77686_REG_PMIC_LDO16CTRL1,
85 MAX77686_REG_PMIC_LDO17CTRL1,
86 MAX77686_REG_PMIC_LDO18CTRL1,
87 MAX77686_REG_PMIC_LDO19CTRL1,
88 MAX77686_REG_PMIC_LDO20CTRL1,
89 MAX77686_REG_PMIC_LDO21CTRL1,
90 MAX77686_REG_PMIC_LDO22CTRL1,
91 MAX77686_REG_PMIC_LDO23CTRL1,
92 MAX77686_REG_PMIC_LDO24CTRL1,
93 MAX77686_REG_PMIC_LDO25CTRL1,
94 MAX77686_REG_PMIC_LDO26CTRL1,
95 MAX77686_REG_PMIC_LDO1CTRL2,
96 MAX77686_REG_PMIC_LDO2CTRL2,
97 MAX77686_REG_PMIC_LDO3CTRL2,
98 MAX77686_REG_PMIC_LDO4CTRL2,
99 MAX77686_REG_PMIC_LDO5CTRL2,
100 MAX77686_REG_PMIC_LDO6CTRL2,
101 MAX77686_REG_PMIC_LDO7CTRL2,
102 MAX77686_REG_PMIC_LDO8CTRL2,
103 MAX77686_REG_PMIC_LDO9CTRL2,
104 MAX77686_REG_PMIC_LDO10CTRL2,
105 MAX77686_REG_PMIC_LDO11CTRL2,
106 MAX77686_REG_PMIC_LDO12CTRL2,
107 MAX77686_REG_PMIC_LDO13CTRL2,
108 MAX77686_REG_PMIC_LDO14CTRL2,
109 MAX77686_REG_PMIC_LDO15CTRL2,
110 MAX77686_REG_PMIC_LDO16CTRL2,
111 MAX77686_REG_PMIC_LDO17CTRL2,
112 MAX77686_REG_PMIC_LDO18CTRL2,
113 MAX77686_REG_PMIC_LDO19CTRL2,
114 MAX77686_REG_PMIC_LDO20CTRL2,
115 MAX77686_REG_PMIC_LDO21CTRL2,
116 MAX77686_REG_PMIC_LDO22CTRL2,
117 MAX77686_REG_PMIC_LDO23CTRL2,
118 MAX77686_REG_PMIC_LDO24CTRL2,
119 MAX77686_REG_PMIC_LDO25CTRL2,
120 MAX77686_REG_PMIC_LDO26CTRL2,
121
122 MAX77686_REG_PMIC_BBAT = 0x7e,
123 MAX77686_REG_PMIC_32KHZ,
124
125 PMIC_NUM_OF_REGS,
126};
127
128/* I2C device address for pmic max77686 */
129#define MAX77686_I2C_ADDR (0x12 >> 1)
130
131enum {
132 REG_DISABLE = 0,
133 REG_ENABLE
134};
135
136enum {
137 LDO_OFF = 0,
138 LDO_ON,
139
140 DIS_LDO = (0x00 << 6),
141 EN_LDO = (0x3 << 6),
142};
143
Piotr Wilczek64a3d4d2013-06-25 09:59:47 +0200[diff] [blame]144enum {
145 OPMODE_OFF = 0,
146 OPMODE_STANDBY,
147 OPMODE_LPM,
148 OPMODE_ON,
149};
150
151int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV);
152int max77686_set_ldo_mode(struct pmic *p, int ldo, char opmode);
153int max77686_set_buck_mode(struct pmic *p, int buck, char opmode);
154
155#define MAX77686_LDO_VOLT_MAX_HEX 0x3f
156#define MAX77686_LDO_VOLT_MASK 0x3f
157#define MAX77686_LDO_MODE_MASK 0xc0
158#define MAX77686_LDO_MODE_OFF (0x00 << 0x06)
159#define MAX77686_LDO_MODE_STANDBY (0x01 << 0x06)
160#define MAX77686_LDO_MODE_LPM (0x02 << 0x06)
161#define MAX77686_LDO_MODE_ON (0x03 << 0x06)
162#define MAX77686_BUCK_MODE_MASK 0x03
163#define MAX77686_BUCK_MODE_SHIFT_1 0x00
164#define MAX77686_BUCK_MODE_SHIFT_2 0x04
165#define MAX77686_BUCK_MODE_OFF 0x00
166#define MAX77686_BUCK_MODE_STANDBY 0x01
167#define MAX77686_BUCK_MODE_LPM 0x02
168#define MAX77686_BUCK_MODE_ON 0x03
169
Rajeshwari Shinde0bdb3fb2013-02-12 20:40:02 +0000[diff] [blame]170/* Buck1 1 volt value */
171#define MAX77686_BUCK1OUT_1V 0x5
Bernie Thompsone450cb72013-04-15 10:34:34 -0700[diff] [blame]172/* Buck1 1.05 volt value */
173#define MAX77686_BUCK1OUT_1_05V 0x6
Rajeshwari Shinde0bdb3fb2013-02-12 20:40:02 +0000[diff] [blame]174#define MAX77686_BUCK1CTRL_EN (3 << 0)
175/* Buck2 1.3 volt value */
176#define MAX77686_BUCK2DVS1_1_3V 0x38
177#define MAX77686_BUCK2CTRL_ON (1 << 4)
178/* Buck3 1.0125 volt value */
179#define MAX77686_BUCK3DVS1_1_0125V 0x21
180#define MAX77686_BUCK3CTRL_ON (1 << 4)
181/* Buck4 1.2 volt value */
182#define MAX77686_BUCK4DVS1_1_2V 0x30
183#define MAX77686_BUCK4CTRL_ON (1 << 4)
184/* LDO2 1.5 volt value */
185#define MAX77686_LD02CTRL1_1_5V 0x1c
186/* LDO3 1.8 volt value */
187#define MAX77686_LD03CTRL1_1_8V 0x14
188/* LDO5 1.8 volt value */
189#define MAX77686_LD05CTRL1_1_8V 0x14
190/* LDO10 1.8 volt value */
191#define MAX77686_LD10CTRL1_1_8V 0x14
192/*
193 * MAX77686_REG_PMIC_32KHZ set to 32KH CP
194 * output is activated
195 */
196#define MAX77686_32KHCP_EN (1 << 1)
197/*
198 * MAX77686_REG_PMIC_BBAT set to
199 * Back up batery charger on and
200 * limit voltage setting to 3.5v
201 */
202#define MAX77686_BBCHOSTEN (1 << 0)
203#define MAX77686_BBCVS_3_5V (3 << 3)
Rajeshwari Shindee9e8be82012-08-24 00:39:23 +0000[diff] [blame]204#endif /* __MAX77686_PMIC_H_ */