| Vladimir Zapolskiy | 6b20ef8 | 2012-04-19 04:33:08 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or |
| 5 | * modify it under the terms of the GNU General Public License |
| 6 | * as published by the Free Software Foundation; either version 2 |
| 7 | * of the License, or (at your option) any later version. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License |
| 15 | * along with this program; if not, write to the Free Software |
| 16 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
| 17 | * MA 02110-1301, USA. |
| 18 | */ |
| 19 | |
| 20 | #include <common.h> |
| 21 | #include <asm/arch/cpu.h> |
| 22 | #include <asm/arch/clk.h> |
| 23 | #include <asm/arch/uart.h> |
| 24 | #include <asm/io.h> |
| 25 | |
| 26 | static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE; |
| 27 | static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE; |
| 28 | |
| 29 | void lpc32xx_uart_init(unsigned int uart_id) |
| 30 | { |
| 31 | if (uart_id < 1 || uart_id > 7) |
| 32 | return; |
| 33 | |
| 34 | /* Disable loopback mode, if it is set by S1L bootloader */ |
| 35 | clrbits_le32(&ctrl->loop, |
| 36 | UART_LOOPBACK(CONFIG_SYS_LPC32XX_UART)); |
| 37 | |
| 38 | if (uart_id < 3 || uart_id > 6) |
| 39 | return; |
| 40 | |
| 41 | /* Enable UART system clock */ |
| 42 | setbits_le32(&clk->uartclk_ctrl, CLK_UART(uart_id)); |
| 43 | |
| 44 | /* Set UART into autoclock mode */ |
| 45 | clrsetbits_le32(&ctrl->clkmode, |
| 46 | UART_CLKMODE_MASK(uart_id), |
| 47 | UART_CLKMODE_AUTO(uart_id)); |
| 48 | |
| 49 | /* Bypass pre-divider of UART clock */ |
| 50 | writel(CLK_UART_X_DIV(1) | CLK_UART_Y_DIV(1), |
| 51 | &clk->u3clk + (uart_id - 3)); |
| 52 | } |