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git01.mediatek.com / filogic / uboot / e3b47bedafa8f4ec1ba95c8339e1b9c81be5cf92 / . / board / atmel / sam9x60ek / sam9x60ek.c
blob: e352afc67ed3fbd0aa94b9f9730b7ad372665805 [file] [log] [blame]
Sandeep Sheriker Mallikarjun641b3352019-09-27 13:08:52 +0000[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
4 *
5 * Author: Sandeep Sheriker M <sandeep.sheriker@microchip.com>
6 */
7
8#include <common.h>
9#include <asm/io.h>
Tudor Ambaruse76c66a2019-09-27 13:09:07 +0000[diff] [blame]10#include <asm/arch/at91sam9_smc.h>
Sandeep Sheriker Mallikarjun641b3352019-09-27 13:08:52 +0000[diff] [blame]11#include <asm/arch/at91_common.h>
12#include <asm/arch/at91_rstc.h>
Tudor Ambaruse76c66a2019-09-27 13:09:07 +0000[diff] [blame]13#include <asm/arch/at91_sfr.h>
Sandeep Sheriker Mallikarjun641b3352019-09-27 13:08:52 +0000[diff] [blame]14#include <asm/arch/clk.h>
15#include <asm/arch/gpio.h>
16#include <debug_uart.h>
17#include <asm/mach-types.h>
18
19DECLARE_GLOBAL_DATA_PTR;
20
21void at91_prepare_cpu_var(void);
22
Tudor Ambaruse76c66a2019-09-27 13:09:07 +0000[diff] [blame]23#ifdef CONFIG_CMD_NAND
24static void sam9x60ek_nand_hw_init(void)
25{
26 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
27 struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
28 unsigned int csa;
29
30 at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
31 at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
32 at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 0); /* NAND ALE */
33 at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 0); /* NAND CLE */
34 /* Enable NandFlash */
35 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
36 /* Configure RDY/BSY */
37 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
38 at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1);
39 at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1);
40 at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1);
41 at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 1);
42 at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 1);
43 at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 1);
44 at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 1);
45 at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1);
46
47 at91_periph_clk_enable(ATMEL_ID_PIOD);
48
49 /* Enable CS3 */
50 csa = readl(&sfr->ebicsa);
51 csa |= AT91_SFR_CCFG_EBI_CSA(3, 1) | AT91_SFR_CCFG_NFD0_ON_D16;
52
53 /* Configure IO drive */
54 csa &= ~AT91_SFR_CCFG_EBI_DRIVE_SAM9X60;
55
56 writel(csa, &sfr->ebicsa);
57
58 /* Configure SMC CS3 for NAND/SmartMedia */
59 writel(AT91_SMC_SETUP_NWE(4), &smc->cs[3].setup);
60
61 writel(AT91_SMC_PULSE_NWE(10) | AT91_SMC_PULSE_NCS_WR(20) |
62 AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(20),
63 &smc->cs[3].pulse);
64
65 writel(AT91_SMC_CYCLE_NWE(20) | AT91_SMC_CYCLE_NRD(20),
66 &smc->cs[3].cycle);
67
68 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
69#ifdef CONFIG_SYS_NAND_DBW_16
70 AT91_SMC_MODE_DBW_16 |
71#else /* CONFIG_SYS_NAND_DBW_8 */
72 AT91_SMC_MODE_DBW_8 |
73#endif
74 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(15),
75 &smc->cs[3].mode);
76}
77#endif
78
Sandeep Sheriker Mallikarjun641b3352019-09-27 13:08:52 +0000[diff] [blame]79#ifdef CONFIG_BOARD_LATE_INIT
80int board_late_init(void)
81{
82 at91_prepare_cpu_var();
83 return 0;
84}
85#endif
86
87#ifdef CONFIG_DEBUG_UART_BOARD_INIT
88void board_debug_uart_init(void)
89{
90 at91_seriald_hw_init();
91}
92#endif
93
94#ifdef CONFIG_BOARD_EARLY_INIT_F
95int board_early_init_f(void)
96{
97#ifdef CONFIG_DEBUG_UART
98 debug_uart_init();
99#endif
100 return 0;
101}
102#endif
103
104int board_init(void)
105{
106 /* address of boot parameters */
107 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
108
Tudor Ambaruse76c66a2019-09-27 13:09:07 +0000[diff] [blame]109#ifdef CONFIG_CMD_NAND
110 sam9x60ek_nand_hw_init();
111#endif
Sandeep Sheriker Mallikarjun641b3352019-09-27 13:08:52 +0000[diff] [blame]112 return 0;
113}
114
115int dram_init(void)
116{
117 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
118 CONFIG_SYS_SDRAM_SIZE);
119 return 0;
120}