blob: 5729799b1221fbc5e0ce3ab8be7e4a52b50beb31 [file] [log] [blame]
Patrick Delaunay4b3f0122020-09-09 17:50:15 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2017-2020 STMicroelectronics - All Rights Reserved
4 */
5
Patrick Delaunay84a9a4e2020-11-06 19:01:32 +01006#define LOG_CATEGORY UCLASS_PINCTRL
7
Vikas Manocha07e9e412017-02-12 10:25:49 -08008#include <common.h>
Vikas Manocha07e9e412017-02-12 10:25:49 -08009#include <dm.h>
Benjamin Gaignard16f6f332018-11-27 13:49:53 +010010#include <hwspinlock.h>
Simon Glass0f2af882020-05-10 11:40:05 -060011#include <log.h>
Simon Glass9bc15642020-02-03 07:36:16 -070012#include <malloc.h>
Vikas Manochaec8630a2017-04-10 15:02:57 -070013#include <asm/gpio.h>
14#include <asm/io.h>
Simon Glass9bc15642020-02-03 07:36:16 -070015#include <dm/device_compat.h>
Patrice Chotarde16e8f42019-07-30 19:16:10 +020016#include <dm/lists.h>
17#include <dm/pinctrl.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060018#include <linux/bitops.h>
Simon Glassd66c5f72020-02-03 07:36:15 -070019#include <linux/err.h>
Simon Glass2dc9c342020-05-10 11:40:01 -060020#include <linux/libfdt.h>
Vikas Manocha07e9e412017-02-12 10:25:49 -080021
Patrick Delaunay7dccd892021-10-22 20:12:34 +020022#include "../gpio/stm32_gpio_priv.h"
23
Vikas Manocha40ddb3a2017-04-10 15:03:04 -070024#define MAX_PINS_ONE_IP 70
Vikas Manochaec8630a2017-04-10 15:02:57 -070025#define MODE_BITS_MASK 3
26#define OSPEED_MASK 3
27#define PUPD_MASK 3
28#define OTYPE_MSK 1
29#define AFR_MASK 0xF
30
Patrice Chotardaaf68e82018-10-24 14:10:18 +020031struct stm32_pinctrl_priv {
Benjamin Gaignard16f6f332018-11-27 13:49:53 +010032 struct hwspinlock hws;
Patrice Chotardaaf68e82018-10-24 14:10:18 +020033 int pinctrl_ngpios;
34 struct list_head gpio_dev;
35};
36
37struct stm32_gpio_bank {
38 struct udevice *gpio_dev;
39 struct list_head list;
40};
41
Benjamin Gaignard16f6f332018-11-27 13:49:53 +010042#ifndef CONFIG_SPL_BUILD
43
Patrice Chotard881e8672018-10-24 14:10:19 +020044static char pin_name[PINNAME_SIZE];
Patrice Chotarda46fb392018-10-24 14:10:20 +020045#define PINMUX_MODE_COUNT 5
46static const char * const pinmux_mode[PINMUX_MODE_COUNT] = {
47 "gpio input",
48 "gpio output",
49 "analog",
50 "unknown",
51 "alt function",
52};
53
Patrick Delaunay6347ed92020-10-28 10:49:07 +010054static const char * const pinmux_bias[] = {
55 [STM32_GPIO_PUPD_NO] = "",
56 [STM32_GPIO_PUPD_UP] = "pull-up",
57 [STM32_GPIO_PUPD_DOWN] = "pull-down",
Patrick Delaunay8274fab2020-06-04 14:30:33 +020058};
59
Patrick Delaunay764d3ba2021-01-21 17:39:07 +010060static const char * const pinmux_otype[] = {
Patrick Delaunay6347ed92020-10-28 10:49:07 +010061 [STM32_GPIO_OTYPE_PP] = "push-pull",
62 [STM32_GPIO_OTYPE_OD] = "open-drain",
Patrick Delaunay8274fab2020-06-04 14:30:33 +020063};
64
Patrice Chotarda46fb392018-10-24 14:10:20 +020065static int stm32_pinctrl_get_af(struct udevice *dev, unsigned int offset)
66{
67 struct stm32_gpio_priv *priv = dev_get_priv(dev);
68 struct stm32_gpio_regs *regs = priv->regs;
69 u32 af;
70 u32 alt_shift = (offset % 8) * 4;
71 u32 alt_index = offset / 8;
72
73 af = (readl(&regs->afr[alt_index]) &
74 GENMASK(alt_shift + 3, alt_shift)) >> alt_shift;
75
76 return af;
77}
78
Patrice Chotard7ef91082018-12-03 10:52:50 +010079static int stm32_populate_gpio_dev_list(struct udevice *dev)
80{
81 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
82 struct udevice *gpio_dev;
83 struct udevice *child;
84 struct stm32_gpio_bank *gpio_bank;
85 int ret;
86
87 /*
88 * parse pin-controller sub-nodes (ie gpio bank nodes) and fill
89 * a list with all gpio device reference which belongs to the
90 * current pin-controller. This list is used to find pin_name and
91 * pin muxing
92 */
93 list_for_each_entry(child, &dev->child_head, sibling_node) {
94 ret = uclass_get_device_by_name(UCLASS_GPIO, child->name,
95 &gpio_dev);
96 if (ret < 0)
97 continue;
98
99 gpio_bank = malloc(sizeof(*gpio_bank));
100 if (!gpio_bank) {
101 dev_err(dev, "Not enough memory\n");
102 return -ENOMEM;
103 }
104
105 gpio_bank->gpio_dev = gpio_dev;
106 list_add_tail(&gpio_bank->list, &priv->gpio_dev);
107 }
108
109 return 0;
110}
111
Patrice Chotardaaf68e82018-10-24 14:10:18 +0200112static int stm32_pinctrl_get_pins_count(struct udevice *dev)
113{
114 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
115 struct gpio_dev_priv *uc_priv;
116 struct stm32_gpio_bank *gpio_bank;
117
118 /*
119 * if get_pins_count has already been executed once on this
120 * pin-controller, no need to run it again
121 */
122 if (priv->pinctrl_ngpios)
123 return priv->pinctrl_ngpios;
124
Patrice Chotard7ef91082018-12-03 10:52:50 +0100125 if (list_empty(&priv->gpio_dev))
126 stm32_populate_gpio_dev_list(dev);
Patrice Chotardaaf68e82018-10-24 14:10:18 +0200127 /*
128 * walk through all banks to retrieve the pin-controller
129 * pins number
130 */
131 list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
132 uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
133
134 priv->pinctrl_ngpios += uc_priv->gpio_count;
135 }
136
137 return priv->pinctrl_ngpios;
138}
139
Patrice Chotard881e8672018-10-24 14:10:19 +0200140static struct udevice *stm32_pinctrl_get_gpio_dev(struct udevice *dev,
Patrice Chotard0b968002018-12-03 10:52:54 +0100141 unsigned int selector,
142 unsigned int *idx)
Patrice Chotard881e8672018-10-24 14:10:19 +0200143{
144 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
145 struct stm32_gpio_bank *gpio_bank;
146 struct gpio_dev_priv *uc_priv;
Patrice Chotard0b968002018-12-03 10:52:54 +0100147 int pin_count = 0;
Patrice Chotard881e8672018-10-24 14:10:19 +0200148
Patrice Chotard7ef91082018-12-03 10:52:50 +0100149 if (list_empty(&priv->gpio_dev))
150 stm32_populate_gpio_dev_list(dev);
151
Patrice Chotard881e8672018-10-24 14:10:19 +0200152 /* look up for the bank which owns the requested pin */
153 list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
154 uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
155
Patrice Chotard0b968002018-12-03 10:52:54 +0100156 if (selector < (pin_count + uc_priv->gpio_count)) {
157 /*
158 * we found the bank, convert pin selector to
159 * gpio bank index
160 */
161 *idx = stm32_offset_to_index(gpio_bank->gpio_dev,
162 selector - pin_count);
Patrick Delaunay4c11a112019-06-21 15:26:52 +0200163 if (IS_ERR_VALUE(*idx))
Patrice Chotard0b968002018-12-03 10:52:54 +0100164 return NULL;
Patrice Chotard881e8672018-10-24 14:10:19 +0200165
Patrice Chotard0b968002018-12-03 10:52:54 +0100166 return gpio_bank->gpio_dev;
167 }
168 pin_count += uc_priv->gpio_count;
Patrice Chotard881e8672018-10-24 14:10:19 +0200169 }
170
171 return NULL;
172}
173
174static const char *stm32_pinctrl_get_pin_name(struct udevice *dev,
175 unsigned int selector)
176{
177 struct gpio_dev_priv *uc_priv;
178 struct udevice *gpio_dev;
Patrice Chotard0b968002018-12-03 10:52:54 +0100179 unsigned int gpio_idx;
Patrice Chotard881e8672018-10-24 14:10:19 +0200180
181 /* look up for the bank which owns the requested pin */
Patrice Chotard0b968002018-12-03 10:52:54 +0100182 gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
Patrice Chotard881e8672018-10-24 14:10:19 +0200183 if (!gpio_dev) {
184 snprintf(pin_name, PINNAME_SIZE, "Error");
185 } else {
186 uc_priv = dev_get_uclass_priv(gpio_dev);
187
188 snprintf(pin_name, PINNAME_SIZE, "%s%d",
189 uc_priv->bank_name,
Patrice Chotard0b968002018-12-03 10:52:54 +0100190 gpio_idx);
Patrice Chotard881e8672018-10-24 14:10:19 +0200191 }
192
193 return pin_name;
194}
Patrice Chotarda46fb392018-10-24 14:10:20 +0200195
196static int stm32_pinctrl_get_pin_muxing(struct udevice *dev,
197 unsigned int selector,
198 char *buf,
199 int size)
200{
201 struct udevice *gpio_dev;
Patrick Delaunay8274fab2020-06-04 14:30:33 +0200202 struct stm32_gpio_priv *priv;
Patrice Chotarda46fb392018-10-24 14:10:20 +0200203 const char *label;
Patrice Chotarda46fb392018-10-24 14:10:20 +0200204 int mode;
205 int af_num;
Patrice Chotard0b968002018-12-03 10:52:54 +0100206 unsigned int gpio_idx;
Patrick Delaunay8274fab2020-06-04 14:30:33 +0200207 u32 pupd, otype;
Patrice Chotarda46fb392018-10-24 14:10:20 +0200208
209 /* look up for the bank which owns the requested pin */
Patrice Chotard0b968002018-12-03 10:52:54 +0100210 gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
Patrice Chotarda46fb392018-10-24 14:10:20 +0200211
212 if (!gpio_dev)
213 return -ENODEV;
214
Patrice Chotard0b968002018-12-03 10:52:54 +0100215 mode = gpio_get_raw_function(gpio_dev, gpio_idx, &label);
Patrice Chotard0b968002018-12-03 10:52:54 +0100216 dev_dbg(dev, "selector = %d gpio_idx = %d mode = %d\n",
217 selector, gpio_idx, mode);
Patrick Delaunay8274fab2020-06-04 14:30:33 +0200218 priv = dev_get_priv(gpio_dev);
Patrick Delaunay6347ed92020-10-28 10:49:07 +0100219 pupd = (readl(&priv->regs->pupdr) >> (gpio_idx * 2)) & PUPD_MASK;
Patrick Delaunay764d3ba2021-01-21 17:39:07 +0100220 otype = (readl(&priv->regs->otyper) >> gpio_idx) & OTYPE_MSK;
Patrice Chotarda46fb392018-10-24 14:10:20 +0200221
222 switch (mode) {
223 case GPIOF_UNKNOWN:
224 /* should never happen */
225 return -EINVAL;
226 case GPIOF_UNUSED:
227 snprintf(buf, size, "%s", pinmux_mode[mode]);
228 break;
229 case GPIOF_FUNC:
Patrice Chotard0b968002018-12-03 10:52:54 +0100230 af_num = stm32_pinctrl_get_af(gpio_dev, gpio_idx);
Patrick Delaunay764d3ba2021-01-21 17:39:07 +0100231 snprintf(buf, size, "%s %d %s %s", pinmux_mode[mode], af_num,
232 pinmux_otype[otype], pinmux_bias[pupd]);
Patrice Chotarda46fb392018-10-24 14:10:20 +0200233 break;
234 case GPIOF_OUTPUT:
Patrick Delaunay764d3ba2021-01-21 17:39:07 +0100235 snprintf(buf, size, "%s %s %s %s",
236 pinmux_mode[mode], pinmux_otype[otype],
237 pinmux_bias[pupd], label ? label : "");
Patrick Delaunay8274fab2020-06-04 14:30:33 +0200238 break;
Patrice Chotarda46fb392018-10-24 14:10:20 +0200239 case GPIOF_INPUT:
Patrick Delaunay764d3ba2021-01-21 17:39:07 +0100240 snprintf(buf, size, "%s %s %s", pinmux_mode[mode],
Patrick Delaunay6347ed92020-10-28 10:49:07 +0100241 pinmux_bias[pupd], label ? label : "");
Patrice Chotarda46fb392018-10-24 14:10:20 +0200242 break;
243 }
244
245 return 0;
246}
247
Benjamin Gaignard16f6f332018-11-27 13:49:53 +0100248#endif
249
Patrick Delaunay4c11a112019-06-21 15:26:52 +0200250static int stm32_pinctrl_probe(struct udevice *dev)
Patrice Chotardaaf68e82018-10-24 14:10:18 +0200251{
252 struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
Patrice Chotardaaf68e82018-10-24 14:10:18 +0200253 int ret;
254
255 INIT_LIST_HEAD(&priv->gpio_dev);
256
Benjamin Gaignard16f6f332018-11-27 13:49:53 +0100257 /* hwspinlock property is optional, just log the error */
258 ret = hwspinlock_get_by_index(dev, 0, &priv->hws);
259 if (ret)
Patrick Delaunay84a9a4e2020-11-06 19:01:32 +0100260 dev_dbg(dev, "hwspinlock_get_by_index may have failed (%d)\n",
261 ret);
Benjamin Gaignard16f6f332018-11-27 13:49:53 +0100262
Patrice Chotardaaf68e82018-10-24 14:10:18 +0200263 return 0;
264}
Patrice Chotardaaf68e82018-10-24 14:10:18 +0200265
Vikas Manochaec8630a2017-04-10 15:02:57 -0700266static int stm32_gpio_config(struct gpio_desc *desc,
267 const struct stm32_gpio_ctl *ctl)
268{
269 struct stm32_gpio_priv *priv = dev_get_priv(desc->dev);
270 struct stm32_gpio_regs *regs = priv->regs;
Benjamin Gaignard16f6f332018-11-27 13:49:53 +0100271 struct stm32_pinctrl_priv *ctrl_priv;
272 int ret;
Vikas Manochaec8630a2017-04-10 15:02:57 -0700273 u32 index;
274
275 if (!ctl || ctl->af > 15 || ctl->mode > 3 || ctl->otype > 1 ||
276 ctl->pupd > 2 || ctl->speed > 3)
277 return -EINVAL;
278
Benjamin Gaignard16f6f332018-11-27 13:49:53 +0100279 ctrl_priv = dev_get_priv(dev_get_parent(desc->dev));
280 ret = hwspinlock_lock_timeout(&ctrl_priv->hws, 10);
281 if (ret == -ETIME) {
282 dev_err(desc->dev, "HWSpinlock timeout\n");
283 return ret;
284 }
285
Vikas Manochaec8630a2017-04-10 15:02:57 -0700286 index = (desc->offset & 0x07) * 4;
287 clrsetbits_le32(&regs->afr[desc->offset >> 3], AFR_MASK << index,
288 ctl->af << index);
289
290 index = desc->offset * 2;
291 clrsetbits_le32(&regs->moder, MODE_BITS_MASK << index,
292 ctl->mode << index);
293 clrsetbits_le32(&regs->ospeedr, OSPEED_MASK << index,
294 ctl->speed << index);
295 clrsetbits_le32(&regs->pupdr, PUPD_MASK << index, ctl->pupd << index);
296
297 index = desc->offset;
298 clrsetbits_le32(&regs->otyper, OTYPE_MSK << index, ctl->otype << index);
299
Benjamin Gaignard16f6f332018-11-27 13:49:53 +0100300 hwspinlock_unlock(&ctrl_priv->hws);
301
Vikas Manochaec8630a2017-04-10 15:02:57 -0700302 return 0;
303}
Patrick Delaunayd252d752018-03-12 10:46:13 +0100304
Vikas Manocha07e9e412017-02-12 10:25:49 -0800305static int prep_gpio_dsc(struct stm32_gpio_dsc *gpio_dsc, u32 port_pin)
306{
Patrick Delaunayd252d752018-03-12 10:46:13 +0100307 gpio_dsc->port = (port_pin & 0x1F000) >> 12;
Vikas Manocha07e9e412017-02-12 10:25:49 -0800308 gpio_dsc->pin = (port_pin & 0x0F00) >> 8;
Patrick Delaunay84a9a4e2020-11-06 19:01:32 +0100309 log_debug("GPIO:port= %d, pin= %d\n", gpio_dsc->port, gpio_dsc->pin);
Vikas Manocha07e9e412017-02-12 10:25:49 -0800310
311 return 0;
312}
313
Patrick Delaunay11ec5972020-09-09 17:50:14 +0200314static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn,
315 ofnode node)
Vikas Manocha07e9e412017-02-12 10:25:49 -0800316{
317 gpio_fn &= 0x00FF;
Vikas Manochaec8630a2017-04-10 15:02:57 -0700318 gpio_ctl->af = 0;
Vikas Manocha07e9e412017-02-12 10:25:49 -0800319
320 switch (gpio_fn) {
321 case 0:
322 gpio_ctl->mode = STM32_GPIO_MODE_IN;
323 break;
324 case 1 ... 16:
325 gpio_ctl->mode = STM32_GPIO_MODE_AF;
326 gpio_ctl->af = gpio_fn - 1;
327 break;
328 case 17:
329 gpio_ctl->mode = STM32_GPIO_MODE_AN;
330 break;
331 default:
332 gpio_ctl->mode = STM32_GPIO_MODE_OUT;
333 break;
334 }
335
Patrick Delaunay11ec5972020-09-09 17:50:14 +0200336 gpio_ctl->speed = ofnode_read_u32_default(node, "slew-rate", 0);
Vikas Manocha07e9e412017-02-12 10:25:49 -0800337
Patrick Delaunay11ec5972020-09-09 17:50:14 +0200338 if (ofnode_read_bool(node, "drive-open-drain"))
Vikas Manocha07e9e412017-02-12 10:25:49 -0800339 gpio_ctl->otype = STM32_GPIO_OTYPE_OD;
340 else
341 gpio_ctl->otype = STM32_GPIO_OTYPE_PP;
342
Patrick Delaunay11ec5972020-09-09 17:50:14 +0200343 if (ofnode_read_bool(node, "bias-pull-up"))
Vikas Manocha07e9e412017-02-12 10:25:49 -0800344 gpio_ctl->pupd = STM32_GPIO_PUPD_UP;
Patrick Delaunay11ec5972020-09-09 17:50:14 +0200345 else if (ofnode_read_bool(node, "bias-pull-down"))
Vikas Manocha07e9e412017-02-12 10:25:49 -0800346 gpio_ctl->pupd = STM32_GPIO_PUPD_DOWN;
347 else
348 gpio_ctl->pupd = STM32_GPIO_PUPD_NO;
349
Patrick Delaunay84a9a4e2020-11-06 19:01:32 +0100350 log_debug("gpio fn= %d, slew-rate= %x, op type= %x, pull-upd is = %x\n",
351 gpio_fn, gpio_ctl->speed, gpio_ctl->otype,
352 gpio_ctl->pupd);
Vikas Manocha07e9e412017-02-12 10:25:49 -0800353
354 return 0;
355}
356
Patrick Delaunay11ec5972020-09-09 17:50:14 +0200357static int stm32_pinctrl_config(ofnode node)
Vikas Manocha07e9e412017-02-12 10:25:49 -0800358{
Vikas Manocha40ddb3a2017-04-10 15:03:04 -0700359 u32 pin_mux[MAX_PINS_ONE_IP];
Vikas Manocha07e9e412017-02-12 10:25:49 -0800360 int rv, len;
Patrick Delaunay11ec5972020-09-09 17:50:14 +0200361 ofnode subnode;
Vikas Manocha07e9e412017-02-12 10:25:49 -0800362
Vikas Manocha07e9e412017-02-12 10:25:49 -0800363 /*
364 * check for "pinmux" property in each subnode (e.g. pins1 and pins2 for
365 * usart1) of pin controller phandle "pinctrl-0"
366 * */
Patrick Delaunay11ec5972020-09-09 17:50:14 +0200367 ofnode_for_each_subnode(subnode, node) {
Vikas Manocha07e9e412017-02-12 10:25:49 -0800368 struct stm32_gpio_dsc gpio_dsc;
369 struct stm32_gpio_ctl gpio_ctl;
370 int i;
371
Patrick Delaunay11ec5972020-09-09 17:50:14 +0200372 rv = ofnode_read_size(subnode, "pinmux");
373 if (rv < 0)
374 return rv;
375 len = rv / sizeof(pin_mux[0]);
Patrick Delaunay84a9a4e2020-11-06 19:01:32 +0100376 log_debug("No of pinmux entries= %d\n", len);
Patrick Delaunay11ec5972020-09-09 17:50:14 +0200377 if (len > MAX_PINS_ONE_IP)
Vikas Manocha07e9e412017-02-12 10:25:49 -0800378 return -EINVAL;
Patrick Delaunay11ec5972020-09-09 17:50:14 +0200379 rv = ofnode_read_u32_array(subnode, "pinmux", pin_mux, len);
380 if (rv < 0)
381 return rv;
Vikas Manocha07e9e412017-02-12 10:25:49 -0800382 for (i = 0; i < len; i++) {
Vikas Manocha1a8fde72017-04-10 15:02:59 -0700383 struct gpio_desc desc;
Patrick Delaunayd252d752018-03-12 10:46:13 +0100384
Patrick Delaunay84a9a4e2020-11-06 19:01:32 +0100385 log_debug("pinmux = %x\n", *(pin_mux + i));
Vikas Manocha07e9e412017-02-12 10:25:49 -0800386 prep_gpio_dsc(&gpio_dsc, *(pin_mux + i));
Patrick Delaunay11ec5972020-09-09 17:50:14 +0200387 prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), subnode);
Vikas Manocha1a8fde72017-04-10 15:02:59 -0700388 rv = uclass_get_device_by_seq(UCLASS_GPIO,
Patrick Delaunayd252d752018-03-12 10:46:13 +0100389 gpio_dsc.port,
390 &desc.dev);
Vikas Manocha1a8fde72017-04-10 15:02:59 -0700391 if (rv)
392 return rv;
393 desc.offset = gpio_dsc.pin;
394 rv = stm32_gpio_config(&desc, &gpio_ctl);
Patrick Delaunay84a9a4e2020-11-06 19:01:32 +0100395 log_debug("rv = %d\n\n", rv);
Vikas Manocha07e9e412017-02-12 10:25:49 -0800396 if (rv)
397 return rv;
398 }
Christophe Kerelloa466d212017-06-20 17:04:18 +0200399 }
400
401 return 0;
402}
403
Patrice Chotard05a93192019-06-21 15:39:23 +0200404static int stm32_pinctrl_bind(struct udevice *dev)
405{
406 ofnode node;
407 const char *name;
408 int ret;
409
410 dev_for_each_subnode(node, dev) {
Patrick Delaunay84a9a4e2020-11-06 19:01:32 +0100411 dev_dbg(dev, "bind %s\n", ofnode_get_name(node));
Patrice Chotard05a93192019-06-21 15:39:23 +0200412
Patrick Delaunay13fd15c2021-01-21 17:39:08 +0100413 if (!ofnode_is_enabled(node))
414 continue;
415
Patrice Chotard05a93192019-06-21 15:39:23 +0200416 ofnode_get_property(node, "gpio-controller", &ret);
417 if (ret < 0)
418 continue;
419 /* Get the name of each gpio node */
420 name = ofnode_get_name(node);
421 if (!name)
422 return -EINVAL;
423
424 /* Bind each gpio node */
425 ret = device_bind_driver_to_node(dev, "gpio_stm32",
426 name, node, NULL);
427 if (ret)
428 return ret;
429
Patrick Delaunay84a9a4e2020-11-06 19:01:32 +0100430 dev_dbg(dev, "bind %s\n", name);
Patrice Chotard05a93192019-06-21 15:39:23 +0200431 }
432
433 return 0;
434}
435
Christophe Kerellod6661552017-06-20 17:04:19 +0200436#if CONFIG_IS_ENABLED(PINCTRL_FULL)
437static int stm32_pinctrl_set_state(struct udevice *dev, struct udevice *config)
438{
Patrick Delaunay11ec5972020-09-09 17:50:14 +0200439 return stm32_pinctrl_config(dev_ofnode(config));
Christophe Kerellod6661552017-06-20 17:04:19 +0200440}
441#else /* PINCTRL_FULL */
Christophe Kerelloa466d212017-06-20 17:04:18 +0200442static int stm32_pinctrl_set_state_simple(struct udevice *dev,
443 struct udevice *periph)
444{
Christophe Kerelloa466d212017-06-20 17:04:18 +0200445 const fdt32_t *list;
446 uint32_t phandle;
Patrick Delaunay11ec5972020-09-09 17:50:14 +0200447 ofnode config_node;
Christophe Kerelloa466d212017-06-20 17:04:18 +0200448 int size, i, ret;
449
Patrick Delaunay11ec5972020-09-09 17:50:14 +0200450 list = ofnode_get_property(dev_ofnode(periph), "pinctrl-0", &size);
Christophe Kerelloa466d212017-06-20 17:04:18 +0200451 if (!list)
452 return -EINVAL;
453
Patrick Delaunay84a9a4e2020-11-06 19:01:32 +0100454 dev_dbg(dev, "periph->name = %s\n", periph->name);
Christophe Kerelloa466d212017-06-20 17:04:18 +0200455
456 size /= sizeof(*list);
457 for (i = 0; i < size; i++) {
458 phandle = fdt32_to_cpu(*list++);
459
Patrick Delaunay11ec5972020-09-09 17:50:14 +0200460 config_node = ofnode_get_by_phandle(phandle);
461 if (!ofnode_valid(config_node)) {
Patrick Delaunay84a9a4e2020-11-06 19:01:32 +0100462 dev_err(periph,
463 "prop pinctrl-0 index %d invalid phandle\n", i);
Christophe Kerelloa466d212017-06-20 17:04:18 +0200464 return -EINVAL;
465 }
466
467 ret = stm32_pinctrl_config(config_node);
468 if (ret)
469 return ret;
Vikas Manocha07e9e412017-02-12 10:25:49 -0800470 }
471
472 return 0;
473}
Christophe Kerellod6661552017-06-20 17:04:19 +0200474#endif /* PINCTRL_FULL */
Vikas Manocha07e9e412017-02-12 10:25:49 -0800475
476static struct pinctrl_ops stm32_pinctrl_ops = {
Christophe Kerellod6661552017-06-20 17:04:19 +0200477#if CONFIG_IS_ENABLED(PINCTRL_FULL)
478 .set_state = stm32_pinctrl_set_state,
479#else /* PINCTRL_FULL */
Vikas Manocha07e9e412017-02-12 10:25:49 -0800480 .set_state_simple = stm32_pinctrl_set_state_simple,
Christophe Kerellod6661552017-06-20 17:04:19 +0200481#endif /* PINCTRL_FULL */
Patrice Chotardaaf68e82018-10-24 14:10:18 +0200482#ifndef CONFIG_SPL_BUILD
Patrice Chotard881e8672018-10-24 14:10:19 +0200483 .get_pin_name = stm32_pinctrl_get_pin_name,
Patrice Chotardaaf68e82018-10-24 14:10:18 +0200484 .get_pins_count = stm32_pinctrl_get_pins_count,
Patrice Chotarda46fb392018-10-24 14:10:20 +0200485 .get_pin_muxing = stm32_pinctrl_get_pin_muxing,
Patrice Chotardaaf68e82018-10-24 14:10:18 +0200486#endif
Vikas Manocha07e9e412017-02-12 10:25:49 -0800487};
488
489static const struct udevice_id stm32_pinctrl_ids[] = {
Patrice Chotardb5652b72017-12-12 09:49:35 +0100490 { .compatible = "st,stm32f429-pinctrl" },
491 { .compatible = "st,stm32f469-pinctrl" },
Vikas Manocha07e9e412017-02-12 10:25:49 -0800492 { .compatible = "st,stm32f746-pinctrl" },
Patrice Chotard636768f2018-12-11 14:49:18 +0100493 { .compatible = "st,stm32f769-pinctrl" },
Patrice Chotard6502c472017-09-13 18:00:04 +0200494 { .compatible = "st,stm32h743-pinctrl" },
Patrick Delaunayd252d752018-03-12 10:46:13 +0100495 { .compatible = "st,stm32mp157-pinctrl" },
496 { .compatible = "st,stm32mp157-z-pinctrl" },
Vikas Manocha07e9e412017-02-12 10:25:49 -0800497 { }
498};
499
500U_BOOT_DRIVER(pinctrl_stm32) = {
Patrice Chotardaaf68e82018-10-24 14:10:18 +0200501 .name = "pinctrl_stm32",
502 .id = UCLASS_PINCTRL,
503 .of_match = stm32_pinctrl_ids,
504 .ops = &stm32_pinctrl_ops,
Patrice Chotard05a93192019-06-21 15:39:23 +0200505 .bind = stm32_pinctrl_bind,
Patrice Chotardaaf68e82018-10-24 14:10:18 +0200506 .probe = stm32_pinctrl_probe,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700507 .priv_auto = sizeof(struct stm32_pinctrl_priv),
Vikas Manocha07e9e412017-02-12 10:25:49 -0800508};