Patrick Delaunay | 4b3f012 | 2020-09-09 17:50:15 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright (C) 2017-2020 STMicroelectronics - All Rights Reserved |
| 4 | */ |
| 5 | |
Patrick Delaunay | 84a9a4e | 2020-11-06 19:01:32 +0100 | [diff] [blame] | 6 | #define LOG_CATEGORY UCLASS_PINCTRL |
| 7 | |
Vikas Manocha | 07e9e41 | 2017-02-12 10:25:49 -0800 | [diff] [blame] | 8 | #include <common.h> |
Vikas Manocha | 07e9e41 | 2017-02-12 10:25:49 -0800 | [diff] [blame] | 9 | #include <dm.h> |
Benjamin Gaignard | 16f6f33 | 2018-11-27 13:49:53 +0100 | [diff] [blame] | 10 | #include <hwspinlock.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 11 | #include <log.h> |
Simon Glass | 9bc1564 | 2020-02-03 07:36:16 -0700 | [diff] [blame] | 12 | #include <malloc.h> |
Vikas Manocha | ec8630a | 2017-04-10 15:02:57 -0700 | [diff] [blame] | 13 | #include <asm/gpio.h> |
| 14 | #include <asm/io.h> |
Simon Glass | 9bc1564 | 2020-02-03 07:36:16 -0700 | [diff] [blame] | 15 | #include <dm/device_compat.h> |
Patrice Chotard | e16e8f4 | 2019-07-30 19:16:10 +0200 | [diff] [blame] | 16 | #include <dm/lists.h> |
| 17 | #include <dm/pinctrl.h> |
Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 18 | #include <linux/bitops.h> |
Simon Glass | d66c5f7 | 2020-02-03 07:36:15 -0700 | [diff] [blame] | 19 | #include <linux/err.h> |
Simon Glass | 2dc9c34 | 2020-05-10 11:40:01 -0600 | [diff] [blame] | 20 | #include <linux/libfdt.h> |
Vikas Manocha | 07e9e41 | 2017-02-12 10:25:49 -0800 | [diff] [blame] | 21 | |
Patrick Delaunay | 7dccd89 | 2021-10-22 20:12:34 +0200 | [diff] [blame] | 22 | #include "../gpio/stm32_gpio_priv.h" |
| 23 | |
Vikas Manocha | 40ddb3a | 2017-04-10 15:03:04 -0700 | [diff] [blame] | 24 | #define MAX_PINS_ONE_IP 70 |
Vikas Manocha | ec8630a | 2017-04-10 15:02:57 -0700 | [diff] [blame] | 25 | #define MODE_BITS_MASK 3 |
| 26 | #define OSPEED_MASK 3 |
| 27 | #define PUPD_MASK 3 |
| 28 | #define OTYPE_MSK 1 |
| 29 | #define AFR_MASK 0xF |
| 30 | |
Patrice Chotard | aaf68e8 | 2018-10-24 14:10:18 +0200 | [diff] [blame] | 31 | struct stm32_pinctrl_priv { |
Benjamin Gaignard | 16f6f33 | 2018-11-27 13:49:53 +0100 | [diff] [blame] | 32 | struct hwspinlock hws; |
Patrice Chotard | aaf68e8 | 2018-10-24 14:10:18 +0200 | [diff] [blame] | 33 | int pinctrl_ngpios; |
| 34 | struct list_head gpio_dev; |
| 35 | }; |
| 36 | |
| 37 | struct stm32_gpio_bank { |
| 38 | struct udevice *gpio_dev; |
| 39 | struct list_head list; |
| 40 | }; |
| 41 | |
Benjamin Gaignard | 16f6f33 | 2018-11-27 13:49:53 +0100 | [diff] [blame] | 42 | #ifndef CONFIG_SPL_BUILD |
| 43 | |
Patrice Chotard | 881e867 | 2018-10-24 14:10:19 +0200 | [diff] [blame] | 44 | static char pin_name[PINNAME_SIZE]; |
Patrice Chotard | a46fb39 | 2018-10-24 14:10:20 +0200 | [diff] [blame] | 45 | #define PINMUX_MODE_COUNT 5 |
| 46 | static const char * const pinmux_mode[PINMUX_MODE_COUNT] = { |
| 47 | "gpio input", |
| 48 | "gpio output", |
| 49 | "analog", |
| 50 | "unknown", |
| 51 | "alt function", |
| 52 | }; |
| 53 | |
Patrick Delaunay | 6347ed9 | 2020-10-28 10:49:07 +0100 | [diff] [blame] | 54 | static const char * const pinmux_bias[] = { |
| 55 | [STM32_GPIO_PUPD_NO] = "", |
| 56 | [STM32_GPIO_PUPD_UP] = "pull-up", |
| 57 | [STM32_GPIO_PUPD_DOWN] = "pull-down", |
Patrick Delaunay | 8274fab | 2020-06-04 14:30:33 +0200 | [diff] [blame] | 58 | }; |
| 59 | |
Patrick Delaunay | 764d3ba | 2021-01-21 17:39:07 +0100 | [diff] [blame] | 60 | static const char * const pinmux_otype[] = { |
Patrick Delaunay | 6347ed9 | 2020-10-28 10:49:07 +0100 | [diff] [blame] | 61 | [STM32_GPIO_OTYPE_PP] = "push-pull", |
| 62 | [STM32_GPIO_OTYPE_OD] = "open-drain", |
Patrick Delaunay | 8274fab | 2020-06-04 14:30:33 +0200 | [diff] [blame] | 63 | }; |
| 64 | |
Patrice Chotard | a46fb39 | 2018-10-24 14:10:20 +0200 | [diff] [blame] | 65 | static int stm32_pinctrl_get_af(struct udevice *dev, unsigned int offset) |
| 66 | { |
| 67 | struct stm32_gpio_priv *priv = dev_get_priv(dev); |
| 68 | struct stm32_gpio_regs *regs = priv->regs; |
| 69 | u32 af; |
| 70 | u32 alt_shift = (offset % 8) * 4; |
| 71 | u32 alt_index = offset / 8; |
| 72 | |
| 73 | af = (readl(®s->afr[alt_index]) & |
| 74 | GENMASK(alt_shift + 3, alt_shift)) >> alt_shift; |
| 75 | |
| 76 | return af; |
| 77 | } |
| 78 | |
Patrice Chotard | 7ef9108 | 2018-12-03 10:52:50 +0100 | [diff] [blame] | 79 | static int stm32_populate_gpio_dev_list(struct udevice *dev) |
| 80 | { |
| 81 | struct stm32_pinctrl_priv *priv = dev_get_priv(dev); |
| 82 | struct udevice *gpio_dev; |
| 83 | struct udevice *child; |
| 84 | struct stm32_gpio_bank *gpio_bank; |
| 85 | int ret; |
| 86 | |
| 87 | /* |
| 88 | * parse pin-controller sub-nodes (ie gpio bank nodes) and fill |
| 89 | * a list with all gpio device reference which belongs to the |
| 90 | * current pin-controller. This list is used to find pin_name and |
| 91 | * pin muxing |
| 92 | */ |
| 93 | list_for_each_entry(child, &dev->child_head, sibling_node) { |
| 94 | ret = uclass_get_device_by_name(UCLASS_GPIO, child->name, |
| 95 | &gpio_dev); |
| 96 | if (ret < 0) |
| 97 | continue; |
| 98 | |
| 99 | gpio_bank = malloc(sizeof(*gpio_bank)); |
| 100 | if (!gpio_bank) { |
| 101 | dev_err(dev, "Not enough memory\n"); |
| 102 | return -ENOMEM; |
| 103 | } |
| 104 | |
| 105 | gpio_bank->gpio_dev = gpio_dev; |
| 106 | list_add_tail(&gpio_bank->list, &priv->gpio_dev); |
| 107 | } |
| 108 | |
| 109 | return 0; |
| 110 | } |
| 111 | |
Patrice Chotard | aaf68e8 | 2018-10-24 14:10:18 +0200 | [diff] [blame] | 112 | static int stm32_pinctrl_get_pins_count(struct udevice *dev) |
| 113 | { |
| 114 | struct stm32_pinctrl_priv *priv = dev_get_priv(dev); |
| 115 | struct gpio_dev_priv *uc_priv; |
| 116 | struct stm32_gpio_bank *gpio_bank; |
| 117 | |
| 118 | /* |
| 119 | * if get_pins_count has already been executed once on this |
| 120 | * pin-controller, no need to run it again |
| 121 | */ |
| 122 | if (priv->pinctrl_ngpios) |
| 123 | return priv->pinctrl_ngpios; |
| 124 | |
Patrice Chotard | 7ef9108 | 2018-12-03 10:52:50 +0100 | [diff] [blame] | 125 | if (list_empty(&priv->gpio_dev)) |
| 126 | stm32_populate_gpio_dev_list(dev); |
Patrice Chotard | aaf68e8 | 2018-10-24 14:10:18 +0200 | [diff] [blame] | 127 | /* |
| 128 | * walk through all banks to retrieve the pin-controller |
| 129 | * pins number |
| 130 | */ |
| 131 | list_for_each_entry(gpio_bank, &priv->gpio_dev, list) { |
| 132 | uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev); |
| 133 | |
| 134 | priv->pinctrl_ngpios += uc_priv->gpio_count; |
| 135 | } |
| 136 | |
| 137 | return priv->pinctrl_ngpios; |
| 138 | } |
| 139 | |
Patrice Chotard | 881e867 | 2018-10-24 14:10:19 +0200 | [diff] [blame] | 140 | static struct udevice *stm32_pinctrl_get_gpio_dev(struct udevice *dev, |
Patrice Chotard | 0b96800 | 2018-12-03 10:52:54 +0100 | [diff] [blame] | 141 | unsigned int selector, |
| 142 | unsigned int *idx) |
Patrice Chotard | 881e867 | 2018-10-24 14:10:19 +0200 | [diff] [blame] | 143 | { |
| 144 | struct stm32_pinctrl_priv *priv = dev_get_priv(dev); |
| 145 | struct stm32_gpio_bank *gpio_bank; |
| 146 | struct gpio_dev_priv *uc_priv; |
Patrice Chotard | 0b96800 | 2018-12-03 10:52:54 +0100 | [diff] [blame] | 147 | int pin_count = 0; |
Patrice Chotard | 881e867 | 2018-10-24 14:10:19 +0200 | [diff] [blame] | 148 | |
Patrice Chotard | 7ef9108 | 2018-12-03 10:52:50 +0100 | [diff] [blame] | 149 | if (list_empty(&priv->gpio_dev)) |
| 150 | stm32_populate_gpio_dev_list(dev); |
| 151 | |
Patrice Chotard | 881e867 | 2018-10-24 14:10:19 +0200 | [diff] [blame] | 152 | /* look up for the bank which owns the requested pin */ |
| 153 | list_for_each_entry(gpio_bank, &priv->gpio_dev, list) { |
| 154 | uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev); |
| 155 | |
Patrice Chotard | 0b96800 | 2018-12-03 10:52:54 +0100 | [diff] [blame] | 156 | if (selector < (pin_count + uc_priv->gpio_count)) { |
| 157 | /* |
| 158 | * we found the bank, convert pin selector to |
| 159 | * gpio bank index |
| 160 | */ |
| 161 | *idx = stm32_offset_to_index(gpio_bank->gpio_dev, |
| 162 | selector - pin_count); |
Patrick Delaunay | 4c11a11 | 2019-06-21 15:26:52 +0200 | [diff] [blame] | 163 | if (IS_ERR_VALUE(*idx)) |
Patrice Chotard | 0b96800 | 2018-12-03 10:52:54 +0100 | [diff] [blame] | 164 | return NULL; |
Patrice Chotard | 881e867 | 2018-10-24 14:10:19 +0200 | [diff] [blame] | 165 | |
Patrice Chotard | 0b96800 | 2018-12-03 10:52:54 +0100 | [diff] [blame] | 166 | return gpio_bank->gpio_dev; |
| 167 | } |
| 168 | pin_count += uc_priv->gpio_count; |
Patrice Chotard | 881e867 | 2018-10-24 14:10:19 +0200 | [diff] [blame] | 169 | } |
| 170 | |
| 171 | return NULL; |
| 172 | } |
| 173 | |
| 174 | static const char *stm32_pinctrl_get_pin_name(struct udevice *dev, |
| 175 | unsigned int selector) |
| 176 | { |
| 177 | struct gpio_dev_priv *uc_priv; |
| 178 | struct udevice *gpio_dev; |
Patrice Chotard | 0b96800 | 2018-12-03 10:52:54 +0100 | [diff] [blame] | 179 | unsigned int gpio_idx; |
Patrice Chotard | 881e867 | 2018-10-24 14:10:19 +0200 | [diff] [blame] | 180 | |
| 181 | /* look up for the bank which owns the requested pin */ |
Patrice Chotard | 0b96800 | 2018-12-03 10:52:54 +0100 | [diff] [blame] | 182 | gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx); |
Patrice Chotard | 881e867 | 2018-10-24 14:10:19 +0200 | [diff] [blame] | 183 | if (!gpio_dev) { |
| 184 | snprintf(pin_name, PINNAME_SIZE, "Error"); |
| 185 | } else { |
| 186 | uc_priv = dev_get_uclass_priv(gpio_dev); |
| 187 | |
| 188 | snprintf(pin_name, PINNAME_SIZE, "%s%d", |
| 189 | uc_priv->bank_name, |
Patrice Chotard | 0b96800 | 2018-12-03 10:52:54 +0100 | [diff] [blame] | 190 | gpio_idx); |
Patrice Chotard | 881e867 | 2018-10-24 14:10:19 +0200 | [diff] [blame] | 191 | } |
| 192 | |
| 193 | return pin_name; |
| 194 | } |
Patrice Chotard | a46fb39 | 2018-10-24 14:10:20 +0200 | [diff] [blame] | 195 | |
| 196 | static int stm32_pinctrl_get_pin_muxing(struct udevice *dev, |
| 197 | unsigned int selector, |
| 198 | char *buf, |
| 199 | int size) |
| 200 | { |
| 201 | struct udevice *gpio_dev; |
Patrick Delaunay | 8274fab | 2020-06-04 14:30:33 +0200 | [diff] [blame] | 202 | struct stm32_gpio_priv *priv; |
Patrice Chotard | a46fb39 | 2018-10-24 14:10:20 +0200 | [diff] [blame] | 203 | const char *label; |
Patrice Chotard | a46fb39 | 2018-10-24 14:10:20 +0200 | [diff] [blame] | 204 | int mode; |
| 205 | int af_num; |
Patrice Chotard | 0b96800 | 2018-12-03 10:52:54 +0100 | [diff] [blame] | 206 | unsigned int gpio_idx; |
Patrick Delaunay | 8274fab | 2020-06-04 14:30:33 +0200 | [diff] [blame] | 207 | u32 pupd, otype; |
Patrice Chotard | a46fb39 | 2018-10-24 14:10:20 +0200 | [diff] [blame] | 208 | |
| 209 | /* look up for the bank which owns the requested pin */ |
Patrice Chotard | 0b96800 | 2018-12-03 10:52:54 +0100 | [diff] [blame] | 210 | gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx); |
Patrice Chotard | a46fb39 | 2018-10-24 14:10:20 +0200 | [diff] [blame] | 211 | |
| 212 | if (!gpio_dev) |
| 213 | return -ENODEV; |
| 214 | |
Patrice Chotard | 0b96800 | 2018-12-03 10:52:54 +0100 | [diff] [blame] | 215 | mode = gpio_get_raw_function(gpio_dev, gpio_idx, &label); |
Patrice Chotard | 0b96800 | 2018-12-03 10:52:54 +0100 | [diff] [blame] | 216 | dev_dbg(dev, "selector = %d gpio_idx = %d mode = %d\n", |
| 217 | selector, gpio_idx, mode); |
Patrick Delaunay | 8274fab | 2020-06-04 14:30:33 +0200 | [diff] [blame] | 218 | priv = dev_get_priv(gpio_dev); |
Patrick Delaunay | 6347ed9 | 2020-10-28 10:49:07 +0100 | [diff] [blame] | 219 | pupd = (readl(&priv->regs->pupdr) >> (gpio_idx * 2)) & PUPD_MASK; |
Patrick Delaunay | 764d3ba | 2021-01-21 17:39:07 +0100 | [diff] [blame] | 220 | otype = (readl(&priv->regs->otyper) >> gpio_idx) & OTYPE_MSK; |
Patrice Chotard | a46fb39 | 2018-10-24 14:10:20 +0200 | [diff] [blame] | 221 | |
| 222 | switch (mode) { |
| 223 | case GPIOF_UNKNOWN: |
| 224 | /* should never happen */ |
| 225 | return -EINVAL; |
| 226 | case GPIOF_UNUSED: |
| 227 | snprintf(buf, size, "%s", pinmux_mode[mode]); |
| 228 | break; |
| 229 | case GPIOF_FUNC: |
Patrice Chotard | 0b96800 | 2018-12-03 10:52:54 +0100 | [diff] [blame] | 230 | af_num = stm32_pinctrl_get_af(gpio_dev, gpio_idx); |
Patrick Delaunay | 764d3ba | 2021-01-21 17:39:07 +0100 | [diff] [blame] | 231 | snprintf(buf, size, "%s %d %s %s", pinmux_mode[mode], af_num, |
| 232 | pinmux_otype[otype], pinmux_bias[pupd]); |
Patrice Chotard | a46fb39 | 2018-10-24 14:10:20 +0200 | [diff] [blame] | 233 | break; |
| 234 | case GPIOF_OUTPUT: |
Patrick Delaunay | 764d3ba | 2021-01-21 17:39:07 +0100 | [diff] [blame] | 235 | snprintf(buf, size, "%s %s %s %s", |
| 236 | pinmux_mode[mode], pinmux_otype[otype], |
| 237 | pinmux_bias[pupd], label ? label : ""); |
Patrick Delaunay | 8274fab | 2020-06-04 14:30:33 +0200 | [diff] [blame] | 238 | break; |
Patrice Chotard | a46fb39 | 2018-10-24 14:10:20 +0200 | [diff] [blame] | 239 | case GPIOF_INPUT: |
Patrick Delaunay | 764d3ba | 2021-01-21 17:39:07 +0100 | [diff] [blame] | 240 | snprintf(buf, size, "%s %s %s", pinmux_mode[mode], |
Patrick Delaunay | 6347ed9 | 2020-10-28 10:49:07 +0100 | [diff] [blame] | 241 | pinmux_bias[pupd], label ? label : ""); |
Patrice Chotard | a46fb39 | 2018-10-24 14:10:20 +0200 | [diff] [blame] | 242 | break; |
| 243 | } |
| 244 | |
| 245 | return 0; |
| 246 | } |
| 247 | |
Benjamin Gaignard | 16f6f33 | 2018-11-27 13:49:53 +0100 | [diff] [blame] | 248 | #endif |
| 249 | |
Patrick Delaunay | 4c11a11 | 2019-06-21 15:26:52 +0200 | [diff] [blame] | 250 | static int stm32_pinctrl_probe(struct udevice *dev) |
Patrice Chotard | aaf68e8 | 2018-10-24 14:10:18 +0200 | [diff] [blame] | 251 | { |
| 252 | struct stm32_pinctrl_priv *priv = dev_get_priv(dev); |
Patrice Chotard | aaf68e8 | 2018-10-24 14:10:18 +0200 | [diff] [blame] | 253 | int ret; |
| 254 | |
| 255 | INIT_LIST_HEAD(&priv->gpio_dev); |
| 256 | |
Benjamin Gaignard | 16f6f33 | 2018-11-27 13:49:53 +0100 | [diff] [blame] | 257 | /* hwspinlock property is optional, just log the error */ |
| 258 | ret = hwspinlock_get_by_index(dev, 0, &priv->hws); |
| 259 | if (ret) |
Patrick Delaunay | 84a9a4e | 2020-11-06 19:01:32 +0100 | [diff] [blame] | 260 | dev_dbg(dev, "hwspinlock_get_by_index may have failed (%d)\n", |
| 261 | ret); |
Benjamin Gaignard | 16f6f33 | 2018-11-27 13:49:53 +0100 | [diff] [blame] | 262 | |
Patrice Chotard | aaf68e8 | 2018-10-24 14:10:18 +0200 | [diff] [blame] | 263 | return 0; |
| 264 | } |
Patrice Chotard | aaf68e8 | 2018-10-24 14:10:18 +0200 | [diff] [blame] | 265 | |
Vikas Manocha | ec8630a | 2017-04-10 15:02:57 -0700 | [diff] [blame] | 266 | static int stm32_gpio_config(struct gpio_desc *desc, |
| 267 | const struct stm32_gpio_ctl *ctl) |
| 268 | { |
| 269 | struct stm32_gpio_priv *priv = dev_get_priv(desc->dev); |
| 270 | struct stm32_gpio_regs *regs = priv->regs; |
Benjamin Gaignard | 16f6f33 | 2018-11-27 13:49:53 +0100 | [diff] [blame] | 271 | struct stm32_pinctrl_priv *ctrl_priv; |
| 272 | int ret; |
Vikas Manocha | ec8630a | 2017-04-10 15:02:57 -0700 | [diff] [blame] | 273 | u32 index; |
| 274 | |
| 275 | if (!ctl || ctl->af > 15 || ctl->mode > 3 || ctl->otype > 1 || |
| 276 | ctl->pupd > 2 || ctl->speed > 3) |
| 277 | return -EINVAL; |
| 278 | |
Benjamin Gaignard | 16f6f33 | 2018-11-27 13:49:53 +0100 | [diff] [blame] | 279 | ctrl_priv = dev_get_priv(dev_get_parent(desc->dev)); |
| 280 | ret = hwspinlock_lock_timeout(&ctrl_priv->hws, 10); |
| 281 | if (ret == -ETIME) { |
| 282 | dev_err(desc->dev, "HWSpinlock timeout\n"); |
| 283 | return ret; |
| 284 | } |
| 285 | |
Vikas Manocha | ec8630a | 2017-04-10 15:02:57 -0700 | [diff] [blame] | 286 | index = (desc->offset & 0x07) * 4; |
| 287 | clrsetbits_le32(®s->afr[desc->offset >> 3], AFR_MASK << index, |
| 288 | ctl->af << index); |
| 289 | |
| 290 | index = desc->offset * 2; |
| 291 | clrsetbits_le32(®s->moder, MODE_BITS_MASK << index, |
| 292 | ctl->mode << index); |
| 293 | clrsetbits_le32(®s->ospeedr, OSPEED_MASK << index, |
| 294 | ctl->speed << index); |
| 295 | clrsetbits_le32(®s->pupdr, PUPD_MASK << index, ctl->pupd << index); |
| 296 | |
| 297 | index = desc->offset; |
| 298 | clrsetbits_le32(®s->otyper, OTYPE_MSK << index, ctl->otype << index); |
| 299 | |
Benjamin Gaignard | 16f6f33 | 2018-11-27 13:49:53 +0100 | [diff] [blame] | 300 | hwspinlock_unlock(&ctrl_priv->hws); |
| 301 | |
Vikas Manocha | ec8630a | 2017-04-10 15:02:57 -0700 | [diff] [blame] | 302 | return 0; |
| 303 | } |
Patrick Delaunay | d252d75 | 2018-03-12 10:46:13 +0100 | [diff] [blame] | 304 | |
Vikas Manocha | 07e9e41 | 2017-02-12 10:25:49 -0800 | [diff] [blame] | 305 | static int prep_gpio_dsc(struct stm32_gpio_dsc *gpio_dsc, u32 port_pin) |
| 306 | { |
Patrick Delaunay | d252d75 | 2018-03-12 10:46:13 +0100 | [diff] [blame] | 307 | gpio_dsc->port = (port_pin & 0x1F000) >> 12; |
Vikas Manocha | 07e9e41 | 2017-02-12 10:25:49 -0800 | [diff] [blame] | 308 | gpio_dsc->pin = (port_pin & 0x0F00) >> 8; |
Patrick Delaunay | 84a9a4e | 2020-11-06 19:01:32 +0100 | [diff] [blame] | 309 | log_debug("GPIO:port= %d, pin= %d\n", gpio_dsc->port, gpio_dsc->pin); |
Vikas Manocha | 07e9e41 | 2017-02-12 10:25:49 -0800 | [diff] [blame] | 310 | |
| 311 | return 0; |
| 312 | } |
| 313 | |
Patrick Delaunay | 11ec597 | 2020-09-09 17:50:14 +0200 | [diff] [blame] | 314 | static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn, |
| 315 | ofnode node) |
Vikas Manocha | 07e9e41 | 2017-02-12 10:25:49 -0800 | [diff] [blame] | 316 | { |
| 317 | gpio_fn &= 0x00FF; |
Vikas Manocha | ec8630a | 2017-04-10 15:02:57 -0700 | [diff] [blame] | 318 | gpio_ctl->af = 0; |
Vikas Manocha | 07e9e41 | 2017-02-12 10:25:49 -0800 | [diff] [blame] | 319 | |
| 320 | switch (gpio_fn) { |
| 321 | case 0: |
| 322 | gpio_ctl->mode = STM32_GPIO_MODE_IN; |
| 323 | break; |
| 324 | case 1 ... 16: |
| 325 | gpio_ctl->mode = STM32_GPIO_MODE_AF; |
| 326 | gpio_ctl->af = gpio_fn - 1; |
| 327 | break; |
| 328 | case 17: |
| 329 | gpio_ctl->mode = STM32_GPIO_MODE_AN; |
| 330 | break; |
| 331 | default: |
| 332 | gpio_ctl->mode = STM32_GPIO_MODE_OUT; |
| 333 | break; |
| 334 | } |
| 335 | |
Patrick Delaunay | 11ec597 | 2020-09-09 17:50:14 +0200 | [diff] [blame] | 336 | gpio_ctl->speed = ofnode_read_u32_default(node, "slew-rate", 0); |
Vikas Manocha | 07e9e41 | 2017-02-12 10:25:49 -0800 | [diff] [blame] | 337 | |
Patrick Delaunay | 11ec597 | 2020-09-09 17:50:14 +0200 | [diff] [blame] | 338 | if (ofnode_read_bool(node, "drive-open-drain")) |
Vikas Manocha | 07e9e41 | 2017-02-12 10:25:49 -0800 | [diff] [blame] | 339 | gpio_ctl->otype = STM32_GPIO_OTYPE_OD; |
| 340 | else |
| 341 | gpio_ctl->otype = STM32_GPIO_OTYPE_PP; |
| 342 | |
Patrick Delaunay | 11ec597 | 2020-09-09 17:50:14 +0200 | [diff] [blame] | 343 | if (ofnode_read_bool(node, "bias-pull-up")) |
Vikas Manocha | 07e9e41 | 2017-02-12 10:25:49 -0800 | [diff] [blame] | 344 | gpio_ctl->pupd = STM32_GPIO_PUPD_UP; |
Patrick Delaunay | 11ec597 | 2020-09-09 17:50:14 +0200 | [diff] [blame] | 345 | else if (ofnode_read_bool(node, "bias-pull-down")) |
Vikas Manocha | 07e9e41 | 2017-02-12 10:25:49 -0800 | [diff] [blame] | 346 | gpio_ctl->pupd = STM32_GPIO_PUPD_DOWN; |
| 347 | else |
| 348 | gpio_ctl->pupd = STM32_GPIO_PUPD_NO; |
| 349 | |
Patrick Delaunay | 84a9a4e | 2020-11-06 19:01:32 +0100 | [diff] [blame] | 350 | log_debug("gpio fn= %d, slew-rate= %x, op type= %x, pull-upd is = %x\n", |
| 351 | gpio_fn, gpio_ctl->speed, gpio_ctl->otype, |
| 352 | gpio_ctl->pupd); |
Vikas Manocha | 07e9e41 | 2017-02-12 10:25:49 -0800 | [diff] [blame] | 353 | |
| 354 | return 0; |
| 355 | } |
| 356 | |
Patrick Delaunay | 11ec597 | 2020-09-09 17:50:14 +0200 | [diff] [blame] | 357 | static int stm32_pinctrl_config(ofnode node) |
Vikas Manocha | 07e9e41 | 2017-02-12 10:25:49 -0800 | [diff] [blame] | 358 | { |
Vikas Manocha | 40ddb3a | 2017-04-10 15:03:04 -0700 | [diff] [blame] | 359 | u32 pin_mux[MAX_PINS_ONE_IP]; |
Vikas Manocha | 07e9e41 | 2017-02-12 10:25:49 -0800 | [diff] [blame] | 360 | int rv, len; |
Patrick Delaunay | 11ec597 | 2020-09-09 17:50:14 +0200 | [diff] [blame] | 361 | ofnode subnode; |
Vikas Manocha | 07e9e41 | 2017-02-12 10:25:49 -0800 | [diff] [blame] | 362 | |
Vikas Manocha | 07e9e41 | 2017-02-12 10:25:49 -0800 | [diff] [blame] | 363 | /* |
| 364 | * check for "pinmux" property in each subnode (e.g. pins1 and pins2 for |
| 365 | * usart1) of pin controller phandle "pinctrl-0" |
| 366 | * */ |
Patrick Delaunay | 11ec597 | 2020-09-09 17:50:14 +0200 | [diff] [blame] | 367 | ofnode_for_each_subnode(subnode, node) { |
Vikas Manocha | 07e9e41 | 2017-02-12 10:25:49 -0800 | [diff] [blame] | 368 | struct stm32_gpio_dsc gpio_dsc; |
| 369 | struct stm32_gpio_ctl gpio_ctl; |
| 370 | int i; |
| 371 | |
Patrick Delaunay | 11ec597 | 2020-09-09 17:50:14 +0200 | [diff] [blame] | 372 | rv = ofnode_read_size(subnode, "pinmux"); |
| 373 | if (rv < 0) |
| 374 | return rv; |
| 375 | len = rv / sizeof(pin_mux[0]); |
Patrick Delaunay | 84a9a4e | 2020-11-06 19:01:32 +0100 | [diff] [blame] | 376 | log_debug("No of pinmux entries= %d\n", len); |
Patrick Delaunay | 11ec597 | 2020-09-09 17:50:14 +0200 | [diff] [blame] | 377 | if (len > MAX_PINS_ONE_IP) |
Vikas Manocha | 07e9e41 | 2017-02-12 10:25:49 -0800 | [diff] [blame] | 378 | return -EINVAL; |
Patrick Delaunay | 11ec597 | 2020-09-09 17:50:14 +0200 | [diff] [blame] | 379 | rv = ofnode_read_u32_array(subnode, "pinmux", pin_mux, len); |
| 380 | if (rv < 0) |
| 381 | return rv; |
Vikas Manocha | 07e9e41 | 2017-02-12 10:25:49 -0800 | [diff] [blame] | 382 | for (i = 0; i < len; i++) { |
Vikas Manocha | 1a8fde7 | 2017-04-10 15:02:59 -0700 | [diff] [blame] | 383 | struct gpio_desc desc; |
Patrick Delaunay | d252d75 | 2018-03-12 10:46:13 +0100 | [diff] [blame] | 384 | |
Patrick Delaunay | 84a9a4e | 2020-11-06 19:01:32 +0100 | [diff] [blame] | 385 | log_debug("pinmux = %x\n", *(pin_mux + i)); |
Vikas Manocha | 07e9e41 | 2017-02-12 10:25:49 -0800 | [diff] [blame] | 386 | prep_gpio_dsc(&gpio_dsc, *(pin_mux + i)); |
Patrick Delaunay | 11ec597 | 2020-09-09 17:50:14 +0200 | [diff] [blame] | 387 | prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), subnode); |
Vikas Manocha | 1a8fde7 | 2017-04-10 15:02:59 -0700 | [diff] [blame] | 388 | rv = uclass_get_device_by_seq(UCLASS_GPIO, |
Patrick Delaunay | d252d75 | 2018-03-12 10:46:13 +0100 | [diff] [blame] | 389 | gpio_dsc.port, |
| 390 | &desc.dev); |
Vikas Manocha | 1a8fde7 | 2017-04-10 15:02:59 -0700 | [diff] [blame] | 391 | if (rv) |
| 392 | return rv; |
| 393 | desc.offset = gpio_dsc.pin; |
| 394 | rv = stm32_gpio_config(&desc, &gpio_ctl); |
Patrick Delaunay | 84a9a4e | 2020-11-06 19:01:32 +0100 | [diff] [blame] | 395 | log_debug("rv = %d\n\n", rv); |
Vikas Manocha | 07e9e41 | 2017-02-12 10:25:49 -0800 | [diff] [blame] | 396 | if (rv) |
| 397 | return rv; |
| 398 | } |
Christophe Kerello | a466d21 | 2017-06-20 17:04:18 +0200 | [diff] [blame] | 399 | } |
| 400 | |
| 401 | return 0; |
| 402 | } |
| 403 | |
Patrice Chotard | 05a9319 | 2019-06-21 15:39:23 +0200 | [diff] [blame] | 404 | static int stm32_pinctrl_bind(struct udevice *dev) |
| 405 | { |
| 406 | ofnode node; |
| 407 | const char *name; |
| 408 | int ret; |
| 409 | |
| 410 | dev_for_each_subnode(node, dev) { |
Patrick Delaunay | 84a9a4e | 2020-11-06 19:01:32 +0100 | [diff] [blame] | 411 | dev_dbg(dev, "bind %s\n", ofnode_get_name(node)); |
Patrice Chotard | 05a9319 | 2019-06-21 15:39:23 +0200 | [diff] [blame] | 412 | |
Patrick Delaunay | 13fd15c | 2021-01-21 17:39:08 +0100 | [diff] [blame] | 413 | if (!ofnode_is_enabled(node)) |
| 414 | continue; |
| 415 | |
Patrice Chotard | 05a9319 | 2019-06-21 15:39:23 +0200 | [diff] [blame] | 416 | ofnode_get_property(node, "gpio-controller", &ret); |
| 417 | if (ret < 0) |
| 418 | continue; |
| 419 | /* Get the name of each gpio node */ |
| 420 | name = ofnode_get_name(node); |
| 421 | if (!name) |
| 422 | return -EINVAL; |
| 423 | |
| 424 | /* Bind each gpio node */ |
| 425 | ret = device_bind_driver_to_node(dev, "gpio_stm32", |
| 426 | name, node, NULL); |
| 427 | if (ret) |
| 428 | return ret; |
| 429 | |
Patrick Delaunay | 84a9a4e | 2020-11-06 19:01:32 +0100 | [diff] [blame] | 430 | dev_dbg(dev, "bind %s\n", name); |
Patrice Chotard | 05a9319 | 2019-06-21 15:39:23 +0200 | [diff] [blame] | 431 | } |
| 432 | |
| 433 | return 0; |
| 434 | } |
| 435 | |
Christophe Kerello | d666155 | 2017-06-20 17:04:19 +0200 | [diff] [blame] | 436 | #if CONFIG_IS_ENABLED(PINCTRL_FULL) |
| 437 | static int stm32_pinctrl_set_state(struct udevice *dev, struct udevice *config) |
| 438 | { |
Patrick Delaunay | 11ec597 | 2020-09-09 17:50:14 +0200 | [diff] [blame] | 439 | return stm32_pinctrl_config(dev_ofnode(config)); |
Christophe Kerello | d666155 | 2017-06-20 17:04:19 +0200 | [diff] [blame] | 440 | } |
| 441 | #else /* PINCTRL_FULL */ |
Christophe Kerello | a466d21 | 2017-06-20 17:04:18 +0200 | [diff] [blame] | 442 | static int stm32_pinctrl_set_state_simple(struct udevice *dev, |
| 443 | struct udevice *periph) |
| 444 | { |
Christophe Kerello | a466d21 | 2017-06-20 17:04:18 +0200 | [diff] [blame] | 445 | const fdt32_t *list; |
| 446 | uint32_t phandle; |
Patrick Delaunay | 11ec597 | 2020-09-09 17:50:14 +0200 | [diff] [blame] | 447 | ofnode config_node; |
Christophe Kerello | a466d21 | 2017-06-20 17:04:18 +0200 | [diff] [blame] | 448 | int size, i, ret; |
| 449 | |
Patrick Delaunay | 11ec597 | 2020-09-09 17:50:14 +0200 | [diff] [blame] | 450 | list = ofnode_get_property(dev_ofnode(periph), "pinctrl-0", &size); |
Christophe Kerello | a466d21 | 2017-06-20 17:04:18 +0200 | [diff] [blame] | 451 | if (!list) |
| 452 | return -EINVAL; |
| 453 | |
Patrick Delaunay | 84a9a4e | 2020-11-06 19:01:32 +0100 | [diff] [blame] | 454 | dev_dbg(dev, "periph->name = %s\n", periph->name); |
Christophe Kerello | a466d21 | 2017-06-20 17:04:18 +0200 | [diff] [blame] | 455 | |
| 456 | size /= sizeof(*list); |
| 457 | for (i = 0; i < size; i++) { |
| 458 | phandle = fdt32_to_cpu(*list++); |
| 459 | |
Patrick Delaunay | 11ec597 | 2020-09-09 17:50:14 +0200 | [diff] [blame] | 460 | config_node = ofnode_get_by_phandle(phandle); |
| 461 | if (!ofnode_valid(config_node)) { |
Patrick Delaunay | 84a9a4e | 2020-11-06 19:01:32 +0100 | [diff] [blame] | 462 | dev_err(periph, |
| 463 | "prop pinctrl-0 index %d invalid phandle\n", i); |
Christophe Kerello | a466d21 | 2017-06-20 17:04:18 +0200 | [diff] [blame] | 464 | return -EINVAL; |
| 465 | } |
| 466 | |
| 467 | ret = stm32_pinctrl_config(config_node); |
| 468 | if (ret) |
| 469 | return ret; |
Vikas Manocha | 07e9e41 | 2017-02-12 10:25:49 -0800 | [diff] [blame] | 470 | } |
| 471 | |
| 472 | return 0; |
| 473 | } |
Christophe Kerello | d666155 | 2017-06-20 17:04:19 +0200 | [diff] [blame] | 474 | #endif /* PINCTRL_FULL */ |
Vikas Manocha | 07e9e41 | 2017-02-12 10:25:49 -0800 | [diff] [blame] | 475 | |
| 476 | static struct pinctrl_ops stm32_pinctrl_ops = { |
Christophe Kerello | d666155 | 2017-06-20 17:04:19 +0200 | [diff] [blame] | 477 | #if CONFIG_IS_ENABLED(PINCTRL_FULL) |
| 478 | .set_state = stm32_pinctrl_set_state, |
| 479 | #else /* PINCTRL_FULL */ |
Vikas Manocha | 07e9e41 | 2017-02-12 10:25:49 -0800 | [diff] [blame] | 480 | .set_state_simple = stm32_pinctrl_set_state_simple, |
Christophe Kerello | d666155 | 2017-06-20 17:04:19 +0200 | [diff] [blame] | 481 | #endif /* PINCTRL_FULL */ |
Patrice Chotard | aaf68e8 | 2018-10-24 14:10:18 +0200 | [diff] [blame] | 482 | #ifndef CONFIG_SPL_BUILD |
Patrice Chotard | 881e867 | 2018-10-24 14:10:19 +0200 | [diff] [blame] | 483 | .get_pin_name = stm32_pinctrl_get_pin_name, |
Patrice Chotard | aaf68e8 | 2018-10-24 14:10:18 +0200 | [diff] [blame] | 484 | .get_pins_count = stm32_pinctrl_get_pins_count, |
Patrice Chotard | a46fb39 | 2018-10-24 14:10:20 +0200 | [diff] [blame] | 485 | .get_pin_muxing = stm32_pinctrl_get_pin_muxing, |
Patrice Chotard | aaf68e8 | 2018-10-24 14:10:18 +0200 | [diff] [blame] | 486 | #endif |
Vikas Manocha | 07e9e41 | 2017-02-12 10:25:49 -0800 | [diff] [blame] | 487 | }; |
| 488 | |
| 489 | static const struct udevice_id stm32_pinctrl_ids[] = { |
Patrice Chotard | b5652b7 | 2017-12-12 09:49:35 +0100 | [diff] [blame] | 490 | { .compatible = "st,stm32f429-pinctrl" }, |
| 491 | { .compatible = "st,stm32f469-pinctrl" }, |
Vikas Manocha | 07e9e41 | 2017-02-12 10:25:49 -0800 | [diff] [blame] | 492 | { .compatible = "st,stm32f746-pinctrl" }, |
Patrice Chotard | 636768f | 2018-12-11 14:49:18 +0100 | [diff] [blame] | 493 | { .compatible = "st,stm32f769-pinctrl" }, |
Patrice Chotard | 6502c47 | 2017-09-13 18:00:04 +0200 | [diff] [blame] | 494 | { .compatible = "st,stm32h743-pinctrl" }, |
Patrick Delaunay | d252d75 | 2018-03-12 10:46:13 +0100 | [diff] [blame] | 495 | { .compatible = "st,stm32mp157-pinctrl" }, |
| 496 | { .compatible = "st,stm32mp157-z-pinctrl" }, |
Vikas Manocha | 07e9e41 | 2017-02-12 10:25:49 -0800 | [diff] [blame] | 497 | { } |
| 498 | }; |
| 499 | |
| 500 | U_BOOT_DRIVER(pinctrl_stm32) = { |
Patrice Chotard | aaf68e8 | 2018-10-24 14:10:18 +0200 | [diff] [blame] | 501 | .name = "pinctrl_stm32", |
| 502 | .id = UCLASS_PINCTRL, |
| 503 | .of_match = stm32_pinctrl_ids, |
| 504 | .ops = &stm32_pinctrl_ops, |
Patrice Chotard | 05a9319 | 2019-06-21 15:39:23 +0200 | [diff] [blame] | 505 | .bind = stm32_pinctrl_bind, |
Patrice Chotard | aaf68e8 | 2018-10-24 14:10:18 +0200 | [diff] [blame] | 506 | .probe = stm32_pinctrl_probe, |
Simon Glass | 8a2b47f | 2020-12-03 16:55:17 -0700 | [diff] [blame] | 507 | .priv_auto = sizeof(struct stm32_pinctrl_priv), |
Vikas Manocha | 07e9e41 | 2017-02-12 10:25:49 -0800 | [diff] [blame] | 508 | }; |