blob: ab423253663ec11c56ed60b8efd3769cf219afcd [file] [log] [blame]
Hou Zhiqiang224999f2019-08-20 09:35:28 +00001// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * P1020RDB-PC Device Tree Source
4 *
5 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
6 * Copyright 2019 NXP
7 */
8
9/include/ "p1020.dtsi"
10
11/ {
12 model = "fsl,P1020RDB-PC";
13 compatible = "fsl,P1020RDB-PC";
14 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&mpic>;
17
18 soc: soc@ffe00000 {
19 ranges = <0x0 0x0 0xffe00000 0x100000>;
20 };
Hou Zhiqiang802865c2019-08-27 11:04:04 +000021
22 pci1: pcie@ffe09000 {
23 reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */
24 ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000 /* downstream I/O */
25 0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
26 };
27
28 pci0: pcie@ffe0a000 {
29 reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */
30 ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */
31 0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
32 };
Xiaowei Baocb75b4e2020-06-04 23:16:35 +080033
34 aliases {
35 spi0 = &espi0;
36 };
Hou Zhiqiang224999f2019-08-20 09:35:28 +000037};
38
Hou Zhiqiang8eb8a9f2020-09-21 14:59:05 +053039/include/ "p1020rdb-pc.dtsi"
Hou Zhiqiang224999f2019-08-20 09:35:28 +000040/include/ "p1020-post.dtsi"
Xiaowei Baocb75b4e2020-06-04 23:16:35 +080041
42&espi0 {
43 status = "okay";
44 flash@0 {
45 compatible = "jedec,spi-nor";
46 #address-cells = <1>;
47 #size-cells = <1>;
48 reg = <0>;
49 spi-max-frequency = <10000000>; /* input clock */
50 };
51};