blob: 9d0c0cdcd08fd5d201df7142635ae26a49e042c4 [file] [log] [blame]
developere021c152022-09-09 19:59:09 +08001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2022 MediaTek Inc.
4 * Author: Sam Shih <sam.shih@mediatek.com>
5 */
6
Tom Rinie3b32642023-03-09 11:22:07 -05007#include <cpu_func.h>
developere021c152022-09-09 19:59:09 +08008#include <init.h>
9#include <asm/armv8/mmu.h>
10#include <asm/system.h>
11#include <asm/global_data.h>
Tom Rini5ba346a2022-10-28 20:27:08 -040012#include <linux/sizes.h>
developere021c152022-09-09 19:59:09 +080013
14DECLARE_GLOBAL_DATA_PTR;
15
16int dram_init(void)
17{
Tom Rinibb4dd962022-11-16 13:10:37 -050018 gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_2G);
developere021c152022-09-09 19:59:09 +080019
20 return 0;
21}
22
Tom Rinie3b32642023-03-09 11:22:07 -050023void reset_cpu(void)
developere021c152022-09-09 19:59:09 +080024{
25 psci_system_reset();
26}
27
28static struct mm_region mt7986_mem_map[] = {
29 {
30 /* DDR */
31 .virt = 0x40000000UL,
32 .phys = 0x40000000UL,
33 .size = 0x80000000UL,
34 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
35 }, {
36 .virt = 0x00000000UL,
37 .phys = 0x00000000UL,
38 .size = 0x40000000UL,
39 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
40 PTE_BLOCK_NON_SHARE |
41 PTE_BLOCK_PXN | PTE_BLOCK_UXN
42 }, {
43 0,
44 }
45};
46
47struct mm_region *mem_map = mt7986_mem_map;