developer | e021c15 | 2022-09-09 19:59:09 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright (C) 2022 MediaTek Inc. |
| 4 | * Author: Sam Shih <sam.shih@mediatek.com> |
| 5 | */ |
| 6 | |
Tom Rini | e3b3264 | 2023-03-09 11:22:07 -0500 | [diff] [blame^] | 7 | #include <cpu_func.h> |
developer | e021c15 | 2022-09-09 19:59:09 +0800 | [diff] [blame] | 8 | #include <init.h> |
| 9 | #include <asm/armv8/mmu.h> |
| 10 | #include <asm/system.h> |
| 11 | #include <asm/global_data.h> |
Tom Rini | 5ba346a | 2022-10-28 20:27:08 -0400 | [diff] [blame] | 12 | #include <linux/sizes.h> |
developer | e021c15 | 2022-09-09 19:59:09 +0800 | [diff] [blame] | 13 | |
| 14 | DECLARE_GLOBAL_DATA_PTR; |
| 15 | |
| 16 | int dram_init(void) |
| 17 | { |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 18 | gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_2G); |
developer | e021c15 | 2022-09-09 19:59:09 +0800 | [diff] [blame] | 19 | |
| 20 | return 0; |
| 21 | } |
| 22 | |
Tom Rini | e3b3264 | 2023-03-09 11:22:07 -0500 | [diff] [blame^] | 23 | void reset_cpu(void) |
developer | e021c15 | 2022-09-09 19:59:09 +0800 | [diff] [blame] | 24 | { |
| 25 | psci_system_reset(); |
| 26 | } |
| 27 | |
| 28 | static struct mm_region mt7986_mem_map[] = { |
| 29 | { |
| 30 | /* DDR */ |
| 31 | .virt = 0x40000000UL, |
| 32 | .phys = 0x40000000UL, |
| 33 | .size = 0x80000000UL, |
| 34 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, |
| 35 | }, { |
| 36 | .virt = 0x00000000UL, |
| 37 | .phys = 0x00000000UL, |
| 38 | .size = 0x40000000UL, |
| 39 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 40 | PTE_BLOCK_NON_SHARE | |
| 41 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 42 | }, { |
| 43 | 0, |
| 44 | } |
| 45 | }; |
| 46 | |
| 47 | struct mm_region *mem_map = mt7986_mem_map; |