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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0 */
Tom Warrenc47e7172013-01-28 13:32:07 +00002/*
3 * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
Tom Warrenc47e7172013-01-28 13:32:07 +00004 */
5
6#ifndef _TEGRA114_GP_PADCTRL_H_
7#define _TEGRA114_GP_PADCTRL_H_
8
9#include <asm/arch-tegra/gp_padctrl.h>
10
11/* APB_MISC_GP and padctrl registers */
12struct apb_misc_gp_ctlr {
13 u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */
14 u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */
15 u32 reserved0[22]; /* 0x08 - 0x5C: */
16 u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */
17 u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
18 u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
Tom Warren54774012013-03-13 15:13:47 -070019 u32 aocfg2; /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */
Tom Warrenc47e7172013-01-28 13:32:07 +000020 u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
21 u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
22 u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
23 u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */
24 u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */
25 u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */
26 u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */
Tom Warren54774012013-03-13 15:13:47 -070027 u32 reserved1; /* 0x8C: */
Tom Warrenc47e7172013-01-28 13:32:07 +000028 u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */
29 u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */
30 u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */
31 u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */
32 u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */
Tom Warren54774012013-03-13 15:13:47 -070033 u32 reserved2[3]; /* 0xA4 - 0xAC: */
Tom Warrenc47e7172013-01-28 13:32:07 +000034 u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */
35 u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */
36 u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */
37 u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */
38 u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */
39 u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */
Tom Warren54774012013-03-13 15:13:47 -070040 u32 reserved3[9]; /* 0xC8-0xE8: */
Tom Warrenc47e7172013-01-28 13:32:07 +000041 u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */
Tom Warren54774012013-03-13 15:13:47 -070042 u32 reserved4[3]; /* 0xF0-0xF8: */
43 u32 ddccfg; /* 0xFC: APB_MISC_GP_DDCCFGPADCTRL */
44 u32 gmacfg; /* 0x100: APB_MISC_GP_GMACFGPADCTRL */
45 u32 reserved5[3]; /* 0x104-0x10C: */
46 u32 gmecfg; /* 0x110: APB_MISC_GP_GMECFGPADCTRL */
47 u32 gmfcfg; /* 0x114: APB_MISC_GP_GMFCFGPADCTRL */
48 u32 gmgcfg; /* 0x118: APB_MISC_GP_GMGCFGPADCTRL */
49 u32 gmhcfg; /* 0x11C: APB_MISC_GP_GMHCFGPADCTRL */
50 u32 owrcfg; /* 0x120: APB_MISC_GP_OWRCFGPADCTRL */
51 u32 uadcfg; /* 0x124: APB_MISC_GP_UADCFGPADCTRL */
52 u32 reserved6; /* 0x128: */
53 u32 dev3cfg; /* 0x12C: APB_MISC_GP_DEV3CFGPADCTRL */
54 u32 reserved7[2]; /* 0x130 - 0x134: */
55 u32 ceccfg; /* 0x138: APB_MISC_GP_CECCFGPADCTRL */
56 u32 reserved8[22]; /* 0x13C - 0x190: */
57 u32 atcfg6; /* 0x194: APB_MISC_GP_ATCFG6PADCTRL */
58 u32 dap5cfg; /* 0x198: APB_MISC_GP_DAP5CFGPADCTRL */
59 u32 vbuscfg; /* 0x19C: APB_MISC_GP_USBVBUSENCFGPADCTRL */
60 u32 aocfg3; /* 0x1A0: APB_MISC_GP_AOCFG3PADCTRL */
61 u32 hvccfg0; /* 0x1A4: APB_MISC_GP_HVCCFG0PADCTRL */
62 u32 sdio4cfg; /* 0x1A8: APB_MISC_GP_SDIO4CFGPADCTRL */
63 u32 aocfg0; /* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */
Tom Warrenc47e7172013-01-28 13:32:07 +000064};
65
Tom Warren3086f6a2013-03-18 14:47:55 -070066/* SDMMC1/3 settings from section 27.5 of T114 TRM */
67#define SDIOCFG_DRVUP_SLWF 0
68#define SDIOCFG_DRVDN_SLWR 0
69#define SDIOCFG_DRVUP 0x24
70#define SDIOCFG_DRVDN 0x14
71
Tom Warrenc47e7172013-01-28 13:32:07 +000072#endif /* _TEGRA114_GP_PADCTRL_H_ */