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git01.mediatek.com / filogic / uboot / e370d023f11402973aafc31111bee10d0655cb3b / . / arch / arm / dts / imx8mp-dhcom-som.dtsi
blob: 63cc6c92c412452ca4147ec082c0ce71a9d173bf [file] [log] [blame]
Marek Vasutf670cd72022-05-21 16:56:26 +0200[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2021-2022 Marek Vasut <marex@denx.de>
4 */
5
6#include "imx8mp.dtsi"
7
8/ {
9 model = "DH electronics i.MX8M Plus DHCOM SoM";
10 compatible = "dh,imx8mp-dhcom-som", "fsl,imx8mp";
11
12 aliases {
13 ethernet0 = &eqos;
14 ethernet1 = &fec;
15 rtc0 = &rv3032;
16 rtc1 = &snvs_rtc;
17 spi0 = &flexspi;
18 };
19
20 memory@40000000 {
21 device_type = "memory";
22 /* Memory size 512 MiB..8 GiB will be filled by U-Boot */
23 reg = <0x0 0x40000000 0 0x08000000>;
24 };
25
26 reg_eth_vio: regulator-eth-vio {
27 compatible = "regulator-fixed";
28 gpio = <&gpio2 10 GPIO_ACTIVE_LOW>;
29 pinctrl-0 = <&pinctrl_enet_vio>;
30 pinctrl-names = "default";
31 regulator-always-on;
32 regulator-boot-on;
33 regulator-min-microvolt = <3300000>;
34 regulator-max-microvolt = <3300000>;
35 regulator-name = "eth_vio";
36 vin-supply = <&buck4>;
37 };
38
39 reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
40 compatible = "regulator-fixed";
41 enable-active-high;
42 gpio = <&gpio2 19 0>; /* SD2_RESET */
43 off-on-delay-us = <12000>;
44 pinctrl-names = "default";
45 pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
46 regulator-max-microvolt = <3300000>;
47 regulator-min-microvolt = <3300000>;
48 regulator-name = "VDD_3V3_SD";
49 startup-delay-us = <100>;
50 vin-supply = <&buck4>;
51 };
52};
53
54&A53_0 {
55 cpu-supply = <&buck2>;
56};
57
58&A53_1 {
59 cpu-supply = <&buck2>;
60};
61
62&A53_2 {
63 cpu-supply = <&buck2>;
64};
65
66&A53_3 {
67 cpu-supply = <&buck2>;
68};
69
70&ecspi1 {
71 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_ecspi1>;
73 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
74 status = "disabled";
75};
76
77&ecspi2 {
78 pinctrl-names = "default";
79 pinctrl-0 = <&pinctrl_ecspi2>;
80 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
81 status = "disabled";
82};
83
84&eqos { /* First ethernet */
85 pinctrl-names = "default";
86 pinctrl-0 = <&pinctrl_eqos>;
87 phy-handle = <&ethphy0g>;
88 phy-mode = "rgmii-id";
89 status = "okay";
90
91 mdio {
92 compatible = "snps,dwmac-mdio";
93 #address-cells = <1>;
94 #size-cells = <0>;
95
96 /* Up to one of these two PHYs may be populated. */
97 ethphy0f: ethernet-phy@1 { /* SMSC LAN8740Ai */
98 compatible = "ethernet-phy-id0007.c110",
99 "ethernet-phy-ieee802.3-c22";
100 interrupt-parent = <&gpio3>;
101 interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
102 pinctrl-0 = <&pinctrl_ethphy0>;
103 pinctrl-names = "default";
104 reg = <1>;
105 reset-assert-us = <1000>;
106 reset-deassert-us = <1000>;
107 reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
108 /* Non-default PHY population option. */
109 status = "disabled";
110 };
111
112 ethphy0g: ethernet-phy@5 { /* Micrel KSZ9131RNXI */
113 compatible = "ethernet-phy-id0022.1642",
114 "ethernet-phy-ieee802.3-c22";
115 interrupt-parent = <&gpio3>;
116 interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
117 micrel,led-mode = <0>;
118 pinctrl-0 = <&pinctrl_ethphy0>;
119 pinctrl-names = "default";
120 reg = <5>;
121 reset-assert-us = <1000>;
122 reset-deassert-us = <1000>;
123 reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
124 /* Default PHY population option. */
125 status = "okay";
126 };
127 };
128};
129
130&fec { /* Second ethernet */
131 pinctrl-names = "default";
132 pinctrl-0 = <&pinctrl_fec>;
133 phy-handle = <&ethphy1f>;
134 phy-mode = "rgmii";
135 fsl,magic-packet;
136 status = "okay";
137
138 mdio {
139 #address-cells = <1>;
140 #size-cells = <0>;
141
142 /* Up to one PHY may be populated. */
143 ethphy1f: ethernet-phy@1 { /* SMSC LAN8740Ai */
144 compatible = "ethernet-phy-id0007.c110",
145 "ethernet-phy-ieee802.3-c22";
146 interrupt-parent = <&gpio4>;
147 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
148 pinctrl-0 = <&pinctrl_ethphy1>;
149 pinctrl-names = "default";
150 reg = <1>;
151 reset-assert-us = <1000>;
152 reset-deassert-us = <1000>;
153 reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
154 /* Non-default PHY population option. */
155 status = "disabled";
156 };
157 };
158};
159
160&flexcan1 {
161 pinctrl-names = "default";
162 pinctrl-0 = <&pinctrl_flexcan1>;
163 status = "disabled";
164};
165
166&flexcan2 {
167 pinctrl-names = "default";
168 pinctrl-0 = <&pinctrl_flexcan2>;
169 status = "disabled";
170};
171
172&flexspi {
173 pinctrl-names = "default";
174 pinctrl-0 = <&pinctrl_flexspi>;
175 status = "okay";
176
177 flash@0 { /* W25Q128JWPIM */
178 compatible = "jedec,spi-nor";
179 reg = <0>;
180 spi-max-frequency = <80000000>;
181 spi-tx-bus-width = <4>;
182 spi-rx-bus-width = <4>;
183 };
184};
185
186&gpio1 {
187 gpio-line-names =
188 "DHCOM-G", "", "", "", "", "DHCOM-I", "DHCOM-J", "DHCOM-L",
189 "DHCOM-B", "DHCOM-A", "", "DHCOM-H", "", "", "", "",
190 "", "", "", "", "", "", "", "",
191 "", "", "", "", "", "", "", "";
192};
193
194&gpio2 {
195 gpio-line-names =
196 "", "", "", "", "", "", "", "",
197 "", "", "", "DHCOM-K", "", "", "", "",
198 "", "", "", "", "DHCOM-INT", "", "", "",
199 "", "", "", "", "", "", "", "";
200};
201
202&gpio3 {
203 gpio-line-names =
204 "", "", "", "", "", "", "", "",
205 "", "", "", "", "", "", "SOM-HW0", "",
206 "", "", "", "", "", "", "SOM-MEM0", "SOM-MEM1",
207 "SOM-MEM2", "SOM-HW2", "", "", "", "", "", "";
208};
209
210&gpio4 {
211 gpio-line-names =
212 "", "", "", "", "", "", "", "",
213 "", "", "", "", "", "", "", "",
214 "", "", "", "SOM-HW1", "", "", "", "",
215 "", "", "", "DHCOM-D", "", "", "", "";
216};
217
218&gpio5 {
219 gpio-line-names =
220 "", "", "DHCOM-C", "", "", "", "", "",
221 "", "", "", "", "", "", "", "",
222 "", "", "", "", "", "", "DHCOM-E", "DHCOM-F",
223 "", "", "", "", "", "", "", "";
224};
225
226&i2c3 {
227 /*
228 * iMX8MP 1P33A Errata ERR007805
229 * I2C is limited to 384 kHz due to SoC bug.
230 */
231 clock-frequency = <100000>;
232 pinctrl-names = "default", "gpio";
233 pinctrl-0 = <&pinctrl_i2c3>;
234 pinctrl-1 = <&pinctrl_i2c3_gpio>;
235 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
236 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
237 status = "okay";
238
239 pmic: pmic@25 {
240 compatible = "nxp,pca9450c";
241 reg = <0x25>;
242 pinctrl-names = "default";
243 pinctrl-0 = <&pinctrl_pmic>;
244 interrupt-parent = <&gpio1>;
245 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
246 sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
247
248 /*
249 * i.MX 8M Plus Data Sheet for Consumer Products
250 * 3.1.4 Operating ranges
251 * MIMX8ML8CVNKZAB
252 */
253 regulators {
254 buck1: BUCK1 { /* VDD_SOC (dual-phase with BUCK3) */
255 regulator-compatible = "BUCK1";
256 regulator-min-microvolt = <850000>;
257 regulator-max-microvolt = <1000000>;
258 regulator-ramp-delay = <3125>;
259 regulator-always-on;
260 regulator-boot-on;
261 };
262
263 buck2: BUCK2 { /* VDD_ARM */
264 regulator-compatible = "BUCK2";
265 regulator-min-microvolt = <850000>;
266 regulator-max-microvolt = <1000000>;
267 regulator-ramp-delay = <3125>;
268 regulator-always-on;
269 regulator-boot-on;
270 };
271
272 buck4: BUCK4 { /* VDD_3V3 */
273 regulator-compatible = "BUCK4";
274 regulator-min-microvolt = <3300000>;
275 regulator-max-microvolt = <3300000>;
276 regulator-always-on;
277 regulator-boot-on;
278 };
279
280 buck5: BUCK5 { /* VDD_1V8 */
281 regulator-compatible = "BUCK5";
282 regulator-min-microvolt = <1800000>;
283 regulator-max-microvolt = <1800000>;
284 regulator-always-on;
285 regulator-boot-on;
286 };
287
288 buck6: BUCK6 { /* NVCC_DRAM_1V1 */
289 regulator-compatible = "BUCK6";
290 regulator-min-microvolt = <1100000>;
291 regulator-max-microvolt = <1100000>;
292 regulator-always-on;
293 regulator-boot-on;
294 };
295
296 ldo1: LDO1 { /* NVCC_SNVS_1V8 */
297 regulator-compatible = "LDO1";
298 regulator-min-microvolt = <1800000>;
299 regulator-max-microvolt = <1800000>;
300 regulator-always-on;
301 regulator-boot-on;
302 };
303
304 ldo3: LDO3 { /* VDDA_1V8 */
305 regulator-compatible = "LDO3";
306 regulator-min-microvolt = <1800000>;
307 regulator-max-microvolt = <1800000>;
308 regulator-always-on;
309 regulator-boot-on;
310 };
311
312 ldo4: LDO4 { /* PMIC_LDO4 */
313 regulator-compatible = "LDO4";
314 regulator-min-microvolt = <3300000>;
315 regulator-max-microvolt = <3300000>;
316 };
317
318 ldo5: LDO5 { /* NVCC_SD2 */
319 regulator-compatible = "LDO5";
320 regulator-min-microvolt = <1800000>;
321 regulator-max-microvolt = <3300000>;
322 };
323 };
324 };
325
326 adc@48 {
327 compatible = "ti,tla2024";
328 reg = <0x48>;
329 #address-cells = <1>;
330 #size-cells = <0>;
331
332 channel@0 { /* Voltage over AIN0 and AIN1. */
333 reg = <0>;
334 };
335
336 channel@1 { /* Voltage over AIN0 and AIN3. */
337 reg = <1>;
338 };
339
340 channel@2 { /* Voltage over AIN1 and AIN3. */
341 reg = <2>;
342 };
343
344 channel@3 { /* Voltage over AIN2 and AIN3. */
345 reg = <3>;
346 };
347
348 channel@4 { /* Voltage over AIN0 and GND. */
349 reg = <4>;
350 };
351
352 channel@5 { /* Voltage over AIN1 and GND. */
353 reg = <5>;
354 };
355
356 channel@6 { /* Voltage over AIN2 and GND. */
357 reg = <6>;
358 };
359
360 channel@7 { /* Voltage over AIN3 and GND. */
361 reg = <7>;
362 };
363 };
364
365 touchscreen@49 {
366 compatible = "ti,tsc2004";
367 reg = <0x49>;
368 interrupts-extended = <&gpio4 0 IRQ_TYPE_EDGE_FALLING>;
369 pinctrl-names = "default";
370 pinctrl-0 = <&pinctrl_touch>;
371 vio-supply = <&buck4>;
372 };
373
374 eeprom0: eeprom@50 { /* EEPROM with EQoS MAC address */
375 compatible = "atmel,24c02";
376 pagesize = <16>;
377 reg = <0x50>;
378 };
379
380 rv3032: rtc@51 {
381 compatible = "microcrystal,rv3032";
382 reg = <0x51>;
383 interrupts-extended = <&gpio5 5 IRQ_TYPE_LEVEL_LOW>;
384 pinctrl-names = "default";
385 pinctrl-0 = <&pinctrl_rtc>;
386 };
387
388 eeprom1: eeprom@53 { /* EEPROM with FEC MAC address */
389 compatible = "atmel,24c02";
390 pagesize = <16>;
391 reg = <0x53>;
392 };
393};
394
395&i2c4 {
396 /*
397 * iMX8MP 1P33A Errata ERR007805
398 * I2C is limited to 384 kHz due to SoC bug.
399 */
400 clock-frequency = <100000>;
401 pinctrl-names = "default", "gpio";
402 pinctrl-0 = <&pinctrl_i2c4>;
403 pinctrl-1 = <&pinctrl_i2c4_gpio>;
404 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
405 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
406 status = "okay";
407};
408
409&i2c5 { /* HDMI EDID bus */
410 /*
411 * iMX8MP 1P33A Errata ERR007805
412 * I2C is limited to 384 kHz due to SoC bug.
413 */
414 clock-frequency = <100000>;
415 pinctrl-names = "default", "gpio";
416 pinctrl-0 = <&pinctrl_i2c5>;
417 pinctrl-1 = <&pinctrl_i2c5_gpio>;
418 scl-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
419 sda-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
420 status = "okay";
421};
422
423&pwm1 {
424 pinctrl-0 = <&pinctrl_pwm1>;
425 pinctrl-names = "default";
426 status = "disabled";
427};
428
429&uart1 {
430 /* CA53 console */
431 pinctrl-names = "default";
432 pinctrl-0 = <&pinctrl_uart1>;
433 status = "okay";
434};
435
436&uart2 {
437 /* Bluetooth */
438 pinctrl-names = "default";
439 pinctrl-0 = <&pinctrl_uart2>;
440 uart-has-rtscts;
441 status = "okay";
442};
443
444&uart3 {
445 pinctrl-names = "default";
446 pinctrl-0 = <&pinctrl_uart3>;
447 uart-has-rtscts;
448 status = "okay";
449};
450
451&uart4 {
452 pinctrl-names = "default";
453 pinctrl-0 = <&pinctrl_uart4>;
454 status = "okay";
455};
456
457&usb3_phy0 {
458 status = "okay";
459};
460
461&usb3_0 {
462 status = "okay";
463};
464
465&usb_dwc3_0 {
466 pinctrl-names = "default";
467 pinctrl-0 = <&pinctrl_usb0_vbus>;
468 dr_mode = "otg";
469 status = "okay";
470};
471
472&usb3_phy1 {
473 status = "okay";
474};
475
476&usb3_1 {
477 status = "okay";
478};
479
480&usb_dwc3_1 {
481 pinctrl-names = "default";
482 pinctrl-0 = <&pinctrl_usb1_vbus>;
483 dr_mode = "host";
484 status = "okay";
485};
486
487/* SDIO WiFi */
488&usdhc1 {
489 pinctrl-names = "default", "state_100mhz", "state_200mhz";
490 pinctrl-0 = <&pinctrl_usdhc1>;
491 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
492 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
493 vmmc-supply = <&buck4>;
494 bus-width = <4>;
495 non-removable;
496 cap-power-off-card;
497 keep-power-in-suspend;
498 status = "okay";
499
500 #address-cells = <1>;
501 #size-cells = <0>;
502
503 brcmf: bcrmf@1 { /* muRata 2AE */
504 reg = <1>;
505 compatible = "cypress,cyw4373-fmac", "brcm,bcm4329-fmac";
506 /*
507 * The "host-wake" interrupt output is by default not
508 * connected to the SoC, but can be connected on to
509 * SoC pin on the carrier board.
510 */
511 reset-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
512 };
513};
514
515/* SD slot */
516&usdhc2 {
517 pinctrl-names = "default", "state_100mhz", "state_200mhz";
518 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
519 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
520 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
521 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
522 vmmc-supply = <&reg_usdhc2_vmmc>;
523 bus-width = <4>;
524 status = "okay";
525};
526
527/* eMMC */
528&usdhc3 {
529 pinctrl-names = "default", "state_100mhz", "state_200mhz";
530 pinctrl-0 = <&pinctrl_usdhc3>;
531 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
532 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
533 vmmc-supply = <&buck4>;
534 vqmmc-supply = <&buck5>;
535 bus-width = <8>;
536 non-removable;
537 status = "okay";
538};
539
540&wdog1 {
541 pinctrl-names = "default";
542 pinctrl-0 = <&pinctrl_wdog>;
543 fsl,ext-reset-output;
544 status = "okay";
545};
546
547&iomuxc {
548 pinctrl-0 = <&pinctrl_hog_base
549 &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c
550 &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f
551 &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i
552 &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l
553 /* GPIO_M is connected to CLKOUT2 */
554 &pinctrl_dhcom_int>;
555 pinctrl-names = "default";
556
557 pinctrl_dhcom_a: dhcom-a-grp {
558 fsl,pins = <
559 /* ENET_QOS_EVENT0-OUT */
560 MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x2
561 >;
562 };
563
564 pinctrl_dhcom_b: dhcom-b-grp {
565 fsl,pins = <
566 /* ENET_QOS_EVENT0-IN */
567 MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x2
568 >;
569 };
570
571 pinctrl_dhcom_c: dhcom-c-grp {
572 fsl,pins = <
573 /* GPIO_C */
574 MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x2
575 >;
576 };
577
578 pinctrl_dhcom_d: dhcom-d-grp {
579 fsl,pins = <
580 /* GPIO_D */
581 MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x2
582 >;
583 };
584
585 pinctrl_dhcom_e: dhcom-e-grp {
586 fsl,pins = <
587 /* GPIO_E */
588 MX8MP_IOMUXC_UART1_RXD__GPIO5_IO22 0x2
589 >;
590 };
591
592 pinctrl_dhcom_f: dhcom-f-grp {
593 fsl,pins = <
594 /* GPIO_F */
595 MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23 0x2
596 >;
597 };
598
599 pinctrl_dhcom_g: dhcom-g-grp {
600 fsl,pins = <
601 /* GPIO_G */
602 MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x2
603 >;
604 };
605
606 pinctrl_dhcom_h: dhcom-h-grp {
607 fsl,pins = <
608 /* GPIO_H */
609 MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x2
610 >;
611 };
612
613 pinctrl_dhcom_i: dhcom-i-grp {
614 fsl,pins = <
615 /* CSI1_SYNC */
616 MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x2
617 >;
618 };
619
620 pinctrl_dhcom_j: dhcom-j-grp {
621 fsl,pins = <
622 /* CSIx_#RST */
623 MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x2
624 >;
625 };
626
627 pinctrl_dhcom_k: dhcom-k-grp {
628 fsl,pins = <
629 /* CSIx_PWDN */
630 MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x2
631 >;
632 };
633
634 pinctrl_dhcom_l: dhcom-l-grp {
635 fsl,pins = <
636 /* CSI2_SYNC */
637 MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x2
638 >;
639 };
640
641 pinctrl_dhcom_int: dhcom-int-grp {
642 fsl,pins = <
643 /* INT_HIGHEST_PRIO */
644 MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x2
645 >;
646 };
647
648 pinctrl_hog_base: dhcom-hog-base-grp {
649 fsl,pins = <
650 /* GPIOs for memory coding */
651 MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x40000080
652 MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x40000080
653 MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x40000080
654 /* GPIOs for hardware coding */
655 MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000080
656 MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x40000080
657 MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25 0x40000080
658 >;
659 };
660
661 pinctrl_ecspi1: dhcom-ecspi1-grp {
662 fsl,pins = <
663 MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x44
664 MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x44
665 MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x44
666 MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x40
667 >;
668 };
669
670 pinctrl_ecspi2: dhcom-ecspi2-grp {
671 fsl,pins = <
672 MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x44
673 MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x44
674 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x44
675 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40
676 >;
677 };
678
679 pinctrl_eqos: dhcom-eqos-grp { /* RGMII */
680 fsl,pins = <
681 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
682 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
683 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
684 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
685 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
686 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
687 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
688 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
689 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
690 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
691 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
692 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
693 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
694 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
695 >;
696 };
697
698 pinctrl_enet_vio: dhcom-enet-vio-grp {
699 fsl,pins = <
700 MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x22
701 >;
702 };
703
704 pinctrl_ethphy0: dhcom-ethphy0-grp {
705 fsl,pins = <
706 /* ENET1_#RST Reset */
707 MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x22
708 /* ENET1_#INT Interrupt */
709 MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x22
710 >;
711 };
712
713 pinctrl_ethphy1: dhcom-ethphy1-grp {
714 fsl,pins = <
715 /* ENET1_#RST Reset */
716 MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x11
717 /* ENET1_#INT Interrupt */
718 MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x11
719 >;
720 };
721
722 pinctrl_fec: dhcom-fec-grp {
723 fsl,pins = <
724 MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK 0x1f
725 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
726 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
727 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
728 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
729 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
730 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
731 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
732 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
733 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
734 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
735 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
736 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
737 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
738 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
739 MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER 0x1f
740 >;
741 };
742
743 pinctrl_flexcan1: dhcom-flexcan1-grp {
744 fsl,pins = <
745 MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
746 MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
747 >;
748 };
749
750 pinctrl_flexcan2: dhcom-flexcan2-grp {
751 fsl,pins = <
752 MX8MP_IOMUXC_UART3_RXD__CAN2_TX 0x154
753 MX8MP_IOMUXC_UART3_TXD__CAN2_RX 0x154
754 >;
755 };
756
757 pinctrl_flexspi: dhcom-flexspi-grp {
758 fsl,pins = <
759 MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2
760 MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82
761 MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82
762 MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82
763 MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82
764 MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
765 >;
766 };
767
768 pinctrl_hdmi: dhcom-hdmi-grp {
769 fsl,pins = <
770 MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x154
771 MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x154
772 >;
773 };
774
775 pinctrl_i2c3: dhcom-i2c3-grp {
776 fsl,pins = <
777 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x40000084
778 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x40000084
779 >;
780 };
781
782 pinctrl_i2c3_gpio: dhcom-i2c3-gpio-grp {
783 fsl,pins = <
784 MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x84
785 MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x84
786 >;
787 };
788
789 pinctrl_i2c4: dhcom-i2c4-grp {
790 fsl,pins = <
791 MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x40000084
792 MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x40000084
793 >;
794 };
795
796 pinctrl_i2c4_gpio: dhcom-i2c4-gpio-grp {
797 fsl,pins = <
798 MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x84
799 MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x84
800 >;
801 };
802
803 pinctrl_i2c5: dhcom-i2c5-grp {
804 fsl,pins = <
805 MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x40000084
806 MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x40000084
807 >;
808 };
809
810 pinctrl_i2c5_gpio: dhcom-i2c5-gpio-grp {
811 fsl,pins = <
812 MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0x84
813 MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0x84
814 >;
815 };
816
817 pinctrl_pmic: dhcom-pmic-grp {
818 fsl,pins = <
819 /* PMIC_nINT */
820 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x40000090
821 >;
822 };
823
824 pinctrl_pwm1: dhcom-pwm1-grp {
825 fsl,pins = <
826 MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x6
827 >;
828 };
829
830 pinctrl_rtc: dhcom-rtc-grp {
831 fsl,pins = <
832 /* RTC_#INT Interrupt */
833 MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x400001c6
834 >;
835 };
836
837 pinctrl_touch: dhcom-touch-grp {
838 fsl,pins = <
839 /* #TOUCH_INT */
840 MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x40000080
841 >;
842 };
843
844 pinctrl_uart1: dhcom-uart1-grp {
845 fsl,pins = <
846 /* Console UART */
847 MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX 0x49
848 MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x49
849 MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x49
850 MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x49
851 >;
852 };
853
854 pinctrl_uart2: dhcom-uart2-grp {
855 fsl,pins = <
856 /* Bluetooth UART */
857 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
858 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
859 MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x49
860 MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x49
861 >;
862 };
863
864 pinctrl_uart3: dhcom-uart3-grp {
865 fsl,pins = <
866 MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x49
867 MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x49
868 MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x49
869 MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x49
870 >;
871 };
872
873 pinctrl_uart4: dhcom-uart4-grp {
874 fsl,pins = <
875 MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49
876 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49
877 >;
878 };
879
880 pinctrl_usb0_vbus: dhcom-usb0-grp {
881 fsl,pins = <
882 MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x0
883 >;
884 };
885
886 pinctrl_usb1_vbus: dhcom-usb1-grp {
887 fsl,pins = <
888 MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x6
889 MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC 0x80
890 >;
891 };
892
893 pinctrl_usdhc1: dhcom-usdhc1-grp {
894 fsl,pins = <
895 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
896 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
897 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
898 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
899 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
900 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
901 /* BT_REG_EN */
902 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144
903 /* WL_REG_EN */
904 MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144
905 >;
906 };
907
908 pinctrl_usdhc1_100mhz: dhcom-usdhc1-100mhz-grp {
909 fsl,pins = <
910 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194
911 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4
912 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4
913 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4
914 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4
915 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4
916 /* BT_REG_EN */
917 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144
918 /* WL_REG_EN */
919 MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144
920 >;
921 };
922
923 pinctrl_usdhc1_200mhz: dhcom-usdhc1-200mhz-grp {
924 fsl,pins = <
925 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196
926 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6
927 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6
928 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6
929 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6
930 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6
931 /* BT_REG_EN */
932 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144
933 /* WL_REG_EN */
934 MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144
935 >;
936 };
937
938 pinctrl_usdhc2: dhcom-usdhc2-grp {
939 fsl,pins = <
940 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
941 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
942 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
943 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
944 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
945 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
946 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
947 >;
948 };
949
950 pinctrl_usdhc2_100mhz: dhcom-usdhc2-100mhz-grp {
951 fsl,pins = <
952 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
953 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
954 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
955 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
956 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
957 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
958 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
959 >;
960 };
961
962 pinctrl_usdhc2_200mhz: dhcom-usdhc2-200mhz-grp {
963 fsl,pins = <
964 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
965 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
966 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
967 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
968 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
969 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
970 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
971 >;
972 };
973
974 pinctrl_usdhc2_vmmc: dhcom-usdhc2-vmmc-grp {
975 fsl,pins = <
976 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x20
977 >;
978 };
979
980 pinctrl_usdhc2_gpio: dhcom-usdhc2-gpio-grp {
981 fsl,pins = <
982 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x40000080
983 >;
984 };
985
986 pinctrl_usdhc3: dhcom-usdhc3-grp {
987 fsl,pins = <
988 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
989 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
990 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
991 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
992 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
993 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
994 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
995 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
996 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
997 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
998 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
999 MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141
1000 >;
1001 };
1002
1003 pinctrl_usdhc3_100mhz: dhcom-usdhc3-100mhz-grp {
1004 fsl,pins = <
1005 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
1006 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
1007 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
1008 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
1009 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
1010 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
1011 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
1012 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
1013 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
1014 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
1015 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
1016 MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141
1017 >;
1018 };
1019
1020 pinctrl_usdhc3_200mhz: dhcom-usdhc3-200mhz-grp {
1021 fsl,pins = <
1022 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
1023 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
1024 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
1025 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
1026 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
1027 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
1028 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
1029 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
1030 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
1031 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
1032 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
1033 MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141
1034 >;
1035 };
1036
1037 pinctrl_wdog: dhcom-wdog-grp {
1038 fsl,pins = <
1039 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
1040 >;
1041 };
1042};