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git01.mediatek.com / filogic / uboot / e36bd3ee1f9a83748a7e3ef55e1736d66fe85d82 / . / board / liebherr / xea / spl_xea.c
blob: 88c157eca45ae0bf4f243e88cc71dc07378fbd32 [file] [log] [blame]
Lukasz Majewskif3adb662019-12-08 22:06:56 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * DENX M28 Boot setup
4 *
5 * Copyright (C) 2019 DENX Software Engineering
6 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
7 *
8 * Copyright (C) 2018 DENX Software Engineering
9 * Måns Rullgård, DENX Software Engineering, mans@mansr.com
10 *
11 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
12 * on behalf of DENX Software Engineering GmbH
13 */
14
Lukasz Majewskif3adb662019-12-08 22:06:56 +0100[diff] [blame]15#include <config.h>
16#include <asm/io.h>
17#include <asm/arch/iomux-mx28.h>
18#include <asm/arch/imx-regs.h>
19#include <asm/arch/sys_proto.h>
20
21#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
Lukasz Majewski0b61ace2020-12-26 01:09:00 +0100[diff] [blame]22#define MUX_CONFIG_BOOT (MXS_PAD_3V3)
Lukasz Majewskif3adb662019-12-08 22:06:56 +0100[diff] [blame]23#define MUX_CONFIG_TSC (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
24#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
25#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
26#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_NOPULL)
27#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
28
29const iomux_cfg_t iomux_setup[] = {
30 /* AUART0 IRDA */
31 MX28_PAD_AUART0_RX__AUART0_RX,
32 MX28_PAD_AUART0_TX__AUART0_TX,
33
34 /* AUART 4 RS422 */
35 MX28_PAD_AUART0_CTS__AUART4_RX,
36 MX28_PAD_AUART0_RTS__AUART4_TX,
37
38 /* USB0 */
39 MX28_PAD_AUART1_CTS__USB0_OVERCURRENT,
40 MX28_PAD_AUART1_RTS__USB0_ID,
41 MX28_PAD_LCD_VSYNC__GPIO_1_28, /* PRW_On */
42
43 /* USB1 */
44 MX28_PAD_PWM2__USB1_OVERCURRENT,
45
46 /* eMMC */
47 MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
48 MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
49 MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
50 MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
51 MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
52 MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0,
53 MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0,
54 MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0,
55 MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0,
56 MX28_PAD_SSP0_DETECT__GPIO_2_9, /* Reset for eMMC */
57 MX28_PAD_SSP0_SCK__SSP0_SCK | MUX_CONFIG_SSP0,
58
59 /* DIG Keys */
60 MX28_PAD_GPMI_D00__GPIO_0_0,
61 MX28_PAD_GPMI_D01__GPIO_0_1,
62 MX28_PAD_GPMI_D02__GPIO_0_2,
63 MX28_PAD_GPMI_D03__GPIO_0_3,
64 MX28_PAD_GPMI_D04__GPIO_0_4,
65 MX28_PAD_GPMI_D05__GPIO_0_5,
66 MX28_PAD_GPMI_D06__GPIO_0_6,
67 MX28_PAD_GPMI_D07__GPIO_0_7,
68
69 /* ADR_0-2 */
70 MX28_PAD_GPMI_CE1N__GPIO_0_17,
71 MX28_PAD_GPMI_CE2N__GPIO_0_18,
72 MX28_PAD_GPMI_CE3N__GPIO_0_19,
73
74 /* Read Keys */
75 MX28_PAD_GPMI_RDY0__GPIO_0_20,
76
77 /* LATCH_EN */
78 MX28_PAD_GPMI_RDY1__GPIO_0_21,
79
80 /* Power off */
81 MX28_PAD_GPMI_RDN__GPIO_0_24,
82
83 /* I2C1 Touch */
84 MX28_PAD_AUART2_CTS__GPIO_3_10,
85 MX28_PAD_AUART2_RTS__GPIO_3_11,
86 MX28_PAD_GPMI_RDY2__GPIO_0_22, /* Touch Reset */
87
88 /* TIVA */
89 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT,
90 MX28_PAD_SSP2_MISO__SSP2_D0,
91 MX28_PAD_SSP2_MOSI__SSP2_CMD,
92 MX28_PAD_SSP2_SCK__SSP2_SCK,
93 MX28_PAD_SSP2_SS0__SSP2_D3,
94 MX28_PAD_SSP2_SS1__GPIO_2_20,
95 MX28_PAD_SSP2_SS2__GPIO_2_21,
96
97 /* SPI3 NOR-Flash */
98 MX28_PAD_AUART1_TX__SSP3_CARD_DETECT,
99 MX28_PAD_AUART2_RX__SSP3_D1,
100 MX28_PAD_AUART2_TX__SSP3_D2,
101 MX28_PAD_SSP3_MISO__SSP3_D0,
102 MX28_PAD_SSP3_MOSI__SSP3_CMD,
103 MX28_PAD_SSP3_SCK__SSP3_SCK,
104 MX28_PAD_SSP3_SS0__SSP3_D3,
105
106 /* NOR-Flash CMD */
107 MX28_PAD_LCD_RS__GPIO_1_26, /* Hold */
108 MX28_PAD_LCD_WR_RWN__GPIO_1_25, /* write protect */
109
110 /* I2C0 Codec */
111 MX28_PAD_I2C0_SCL__I2C0_SCL,
112 MX28_PAD_I2C0_SDA__I2C0_SDA,
113
Lukasz Majewskif3adb662019-12-08 22:06:56 +0100[diff] [blame]114 /* PWR-Hold */
115 MX28_PAD_SPDIF__GPIO_3_27,
116
117 /* EMI */
118 MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
119 MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
120 MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
121 MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
122 MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
123 MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
124 MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
125 MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
126 MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
127 MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
128 MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
129 MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
130 MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
131 MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
132 MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
133 MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
134 MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
135 MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
136 MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
137 MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
138 MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
139 MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
140 MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
141 MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
142 MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
143
144 MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
145 MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
146 MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
147 MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
148 MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
149 MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
150 MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
151 MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
152 MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
153 MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
154 MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
155 MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
156 MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
157 MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
158 MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
159 MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
160 MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
161 MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
162 MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
163 MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
164 MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
165 MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
166 MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
167 MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
168
169 /* Uart3 Bluetooth-Interface */
170 MX28_PAD_AUART3_CTS__AUART3_CTS,
171 MX28_PAD_AUART3_RTS__AUART3_RTS,
172 MX28_PAD_AUART3_RX__AUART3_RX,
173 MX28_PAD_AUART3_TX__AUART3_TX,
174
175 /* framebuffer */
176 MX28_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD,
177 MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD,
178 MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD,
179 MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD,
180 MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD,
181 MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD,
182 MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD,
183 MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD,
184 MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD,
185 MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD,
186 MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD,
187 MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
188 MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
189 MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
190 MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
191 MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
192 MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
193 MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
194 MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
195 MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD,
196 MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD,
197 MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD,
198 MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD,
199 MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD,
200 MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD,
201 MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MUX_CONFIG_LCD,
202 MX28_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD,
203 MX28_PAD_LCD_HSYNC__LCD_HSYNC | MUX_CONFIG_LCD,
204 MX28_PAD_LCD_RD_E__LCD_VSYNC | MUX_CONFIG_LCD,
205 MX28_PAD_LCD_RESET__LCD_RESET | MUX_CONFIG_LCD,
206
207 /* DUART RS232 */
208 MX28_PAD_PWM0__DUART_RX,
209 MX28_PAD_PWM1__DUART_TX,
210
211 /* FEC Ethernet */
212 MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
213 MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET,
214 MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET,
215 MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
216 MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
217 MX28_PAD_ENET0_RX_CLK__GPIO_4_13, /* Phy Interrupt */
218 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,
219 MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,
220 MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,
221 MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET,
222 MX28_PAD_ENET0_TX_CLK__GPIO_4_5, /* n.c. */
223 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
224 MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
225 MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
226 MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET,
Lukasz Majewskiad778a32024-03-29 12:18:07 +0100[diff] [blame]227 MX28_PAD_SSP1_CMD__GPIO_2_13, /* PHY reset HW Rev. 1*/
228 MX28_PAD_SAIF0_LRCLK__GPIO_3_21, /* PHY reset HW Rev. 2*/
Lukasz Majewskif3adb662019-12-08 22:06:56 +0100[diff] [blame]229
230 /* TIVA boot control */
231 MX28_PAD_GPMI_RDY3__GPIO_0_23 | MUX_CONFIG_BOOT, /* TIVA0 */
232 MX28_PAD_GPMI_WRN__GPIO_0_25 | MUX_CONFIG_BOOT, /* TIVA1 */
Lukasz Majewski80361a12024-03-29 12:18:08 +0100[diff] [blame]233
234 /* HW revision ID Base Board */
235 MX28_PAD_LCD_D12__GPIO_1_12,
236 MX28_PAD_LCD_D13__GPIO_1_13,
237 MX28_PAD_LCD_D14__GPIO_1_14,
238
239 /* HW revision ID (SoM) */
240 MX28_PAD_LCD_D15__GPIO_1_15,
241 MX28_PAD_LCD_D16__GPIO_1_16,
242 MX28_PAD_LCD_D17__GPIO_1_17,
243 MX28_PAD_LCD_D18__GPIO_1_18,
Lukasz Majewskif3adb662019-12-08 22:06:56 +0100[diff] [blame]244};
245
246u32 mxs_dram_vals[] = {
247 0x00000000, 0x00000000, 0x00000000, 0x00000000,
248 0x00000000, 0x00000000, 0x00000000, 0x00000000,
249 0x00000000, 0x00000000, 0x00000000, 0x00000000,
250 0x00000000, 0x00000000, 0x00000000, 0x00000000,
251 0x00000000, 0x00000100, 0x00000000, 0x00000000,
252 0x00000000, 0x00000000, 0x00000000, 0x00000000,
253 0x00000000, 0x00000000, 0x00010101, 0x01010101,
254 0x000f0f01, 0x0f02010a, 0x00000000, 0x00010101,
255 0x00000100, 0x00000100, 0x00000000, 0x00000002,
256 0x01010000, 0x07080403, 0x07005303, 0x0b0000c8,
257 0x0200a0c1, 0x0002040c, 0x0038430a, 0x04290322,
258 0x02040203, 0x00c8002b, 0x00000000, 0x00000000,
259 0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
260 0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
261 0x00000003, 0x00000000, 0x00000000, 0x00000000,
262 0x00000000, 0x00000000, 0x00000000, 0x00000000,
263 0x00000000, 0x00000000, 0x00000612, 0x01000102,
264 0x06120612, 0x00000200, 0x00020007, 0xf4004a27,
265 0xf4004a27, 0xf4004a27, 0xf4004a27, 0x07400300,
266 0x07400300, 0x07400300, 0x07400300, 0x00000005,
267 0x00000000, 0x00000000, 0x01000000, 0x00000000,
268 0x00000001, 0x000f1133, 0x00000000, 0x00001f04,
269 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04,
270 0x00001f04, 0x00001f04, 0x00001f04, 0x00000000,
271 0x00000000, 0x00000000, 0x00000000, 0x00000000,
272 0x00000000, 0x00000000, 0x00000000, 0x00000000,
273 0x00000000, 0x00000000, 0x00000000, 0x00000000,
274 0x00000000, 0x00000000, 0x00000000, 0x00000000,
275 0x00000000, 0x00000000, 0x00000000, 0x00000000,
276 0x00000000, 0x00000000, 0x00000000, 0x00000000,
277 0x00000000, 0x00000000, 0x00000000, 0x00000000,
278 0x00000000, 0x00000000, 0x00000000, 0x00000000,
279 0x00000000, 0x00000000, 0x00000000, 0x00000000,
280 0x00000000, 0x00000000, 0x00000000, 0x00000000,
281 0x00000000, 0x00000000, 0x00000000, 0x00000000,
282 0x00000000, 0x00000000, 0x00000000, 0x00000000,
283 0x00000000, 0x00000000, 0x00000000, 0x00000000,
284 0x00000000, 0x00000000, 0x00000000, 0x00000000,
285 0x00000000, 0x00000000, 0x00000000, 0x00000000,
286 0x00000000, 0x00000000, 0x00000000, 0x00000000,
287 0x00000000, 0x00000000, 0x00010000, 0x00030404,
288 0x00000002, 0x00000000, 0x00000000, 0x00000000,
289 0x00000000, 0x00000000, 0x00000000, 0x01010000,
290 0x01000000, 0x03030000, 0x00010303, 0x01020202,
291 0x00000000, 0x02040101, 0x21002103, 0x00061200,
292 0x06120612, 0x00000642, 0x00000000, 0x00000004,
293 0x00000000, 0x00000080, 0x00000000, 0x00000000,
294 0x00000000, 0xffffffff
295};
296
Lukasz Majewski09207162021-12-27 11:38:21 +0100[diff] [blame]297#ifndef CONFIG_SPL_FRAMEWORK
298void board_init_ll(const u32 arg, const uint32_t *resptr)
299{
300 mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
301}
302#else
Lukasz Majewskif3adb662019-12-08 22:06:56 +0100[diff] [blame]303void lowlevel_init(void)
304{
305 struct mxs_pinctrl_regs *pinctrl_regs =
306 (struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE;
307
308 /* Set EMI drive strength */
309 writel(0x00003fff, &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_clr);
310 writel(0x00002aaa, &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set);
311
312 mxs_common_spl_init(0, NULL, iomux_setup, ARRAY_SIZE(iomux_setup));
313}
Lukasz Majewski09207162021-12-27 11:38:21 +0100[diff] [blame]314#endif