blob: a214c04ddadfbf06dc5864683d601c7b314f2b03 [file] [log] [blame]
Peng Fanb72606c2022-07-26 16:41:10 +08001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2022 NXP
4 */
5
Peng Fanb72606c2022-07-26 16:41:10 +08006#include <command.h>
7#include <cpu_func.h>
8#include <hang.h>
9#include <image.h>
10#include <init.h>
11#include <log.h>
12#include <spl.h>
13#include <asm/global_data.h>
14#include <asm/io.h>
15#include <asm/arch/imx93_pins.h>
Mathieu Othacehe72c6afe2024-02-09 11:30:07 +010016#include <asm/arch/mu.h>
Peng Fanb72606c2022-07-26 16:41:10 +080017#include <asm/arch/clock.h>
18#include <asm/arch/sys_proto.h>
19#include <asm/mach-imx/boot_mode.h>
20#include <asm/mach-imx/mxc_i2c.h>
21#include <asm/arch-mx7ulp/gpio.h>
Mathieu Othacehe8bb6ede2024-02-26 18:37:18 +010022#include <asm/mach-imx/ele_api.h>
Peng Fanb72606c2022-07-26 16:41:10 +080023#include <asm/mach-imx/syscounter.h>
Shiji Yangbb112342023-08-03 09:47:16 +080024#include <asm/sections.h>
Peng Fanb72606c2022-07-26 16:41:10 +080025#include <dm/uclass.h>
26#include <dm/device.h>
27#include <dm/uclass-internal.h>
28#include <dm/device-internal.h>
29#include <linux/delay.h>
30#include <asm/arch/clock.h>
31#include <asm/arch/ccm_regs.h>
32#include <asm/arch/ddr.h>
33#include <power/pmic.h>
34#include <power/pca9450.h>
35#include <asm/arch/trdc.h>
36
37DECLARE_GLOBAL_DATA_PTR;
38
39int spl_board_boot_device(enum boot_device boot_dev_spl)
40{
41 return BOOT_DEVICE_BOOTROM;
42}
43
44void spl_board_init(void)
45{
Mathieu Othacehe8bb6ede2024-02-26 18:37:18 +010046 int ret;
47
48 ret = ele_start_rng();
49 if (ret)
50 printf("Fail to start RNG: %d\n", ret);
51
Peng Fanb72606c2022-07-26 16:41:10 +080052 puts("Normal Boot\n");
53}
54
Peng Fanffb8c372024-09-19 12:01:39 +080055extern struct dram_timing_info dram_timing_1866mts;
Peng Fanb72606c2022-07-26 16:41:10 +080056void spl_dram_init(void)
57{
Peng Fanffb8c372024-09-19 12:01:39 +080058 struct dram_timing_info *ptiming = &dram_timing;
59
60 if (is_voltage_mode(VOLT_LOW_DRIVE))
61 ptiming = &dram_timing_1866mts;
62
63 printf("DDR: %uMTS\n", ptiming->fsp_msg[0].drate);
64 ddr_init(ptiming);
Peng Fanb72606c2022-07-26 16:41:10 +080065}
66
67#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450)
68int power_init_board(void)
69{
70 struct udevice *dev;
71 int ret;
Peng Fan0ddb8952024-09-19 12:01:37 +080072 unsigned int val = 0, buck_val;
Peng Fanb72606c2022-07-26 16:41:10 +080073
74 ret = pmic_get("pmic@25", &dev);
75 if (ret == -ENODEV) {
76 puts("No pca9450@25\n");
77 return 0;
78 }
79 if (ret != 0)
80 return ret;
81
82 /* BUCKxOUT_DVS0/1 control BUCK123 output */
83 pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
84
Peng Fan513d5082023-04-28 12:08:35 +080085 /* enable DVS control through PMIC_STBY_REQ */
86 pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
87
Peng Fan0ddb8952024-09-19 12:01:37 +080088 ret = pmic_reg_read(dev, PCA9450_PWR_CTRL);
89 if (ret < 0)
90 return ret;
91
92 val = ret;
93
94 if (is_voltage_mode(VOLT_LOW_DRIVE)) {
95 buck_val = 0x0c; /* 0.8v for Low drive mode */
96 printf("PMIC: Low Drive Voltage Mode\n");
97 } else if (is_voltage_mode(VOLT_NOMINAL_DRIVE)) {
98 buck_val = 0x10; /* 0.85v for Nominal drive mode */
99 printf("PMIC: Nominal Voltage Mode\n");
100 } else {
101 buck_val = 0x14; /* 0.9v for Over drive mode */
102 printf("PMIC: Over Drive Voltage Mode\n");
103 }
104
105 if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) {
106 pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val);
107 pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val);
Peng Fan513d5082023-04-28 12:08:35 +0800108 } else {
Peng Fan0ddb8952024-09-19 12:01:37 +0800109 pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val + 0x4);
110 pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val + 0x4);
Peng Fan513d5082023-04-28 12:08:35 +0800111 }
112
Peng Fan0ddb8952024-09-19 12:01:37 +0800113 if (IS_ENABLED(CONFIG_IMX93_EVK_LPDDR4X)) {
114 /* Set VDDQ to 1.1V from buck2 */
115 pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x28);
116 }
117
Peng Fan513d5082023-04-28 12:08:35 +0800118 /* set standby voltage to 0.65v */
Peng Fan0ddb8952024-09-19 12:01:37 +0800119 if (val & PCA9450_REG_PWRCTRL_TOFF_DEB)
120 pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x0);
121 else
122 pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4);
Peng Fanb72606c2022-07-26 16:41:10 +0800123
124 /* I2C_LT_EN*/
125 pmic_reg_write(dev, 0xa, 0x3);
Peng Fanb72606c2022-07-26 16:41:10 +0800126 return 0;
127}
128#endif
129
Peng Fanb72606c2022-07-26 16:41:10 +0800130void board_init_f(ulong dummy)
131{
132 int ret;
133
134 /* Clear the BSS. */
135 memset(__bss_start, 0, __bss_end - __bss_start);
136
137 timer_init();
138
139 arch_cpu_init();
140
141 board_early_init_f();
142
143 spl_early_init();
144
145 preloader_console_init();
146
Ye Li81bfc1a2024-04-01 09:41:08 +0800147 ret = imx9_probe_mu();
Peng Fanb72606c2022-07-26 16:41:10 +0800148 if (ret) {
149 printf("Fail to init Sentinel API\n");
150 } else {
Fabio Estevam67480712024-04-15 18:57:17 -0300151 debug("SOC: 0x%x\n", gd->arch.soc_rev);
152 debug("LC: 0x%x\n", gd->arch.lifecycle);
Peng Fanb72606c2022-07-26 16:41:10 +0800153 }
Peng Fan513d5082023-04-28 12:08:35 +0800154
Ye Li66af10a2024-09-19 12:01:27 +0800155 clock_init_late();
156
Peng Fanb72606c2022-07-26 16:41:10 +0800157 power_init_board();
158
Ye Li66af10a2024-09-19 12:01:27 +0800159 if (!is_voltage_mode(VOLT_LOW_DRIVE))
Peng Fan513d5082023-04-28 12:08:35 +0800160 set_arm_clk(get_cpu_speed_grade_hz());
Peng Fan10fde4e2022-07-26 16:41:11 +0800161
Peng Fanb72606c2022-07-26 16:41:10 +0800162 /* Init power of mix */
163 soc_power_init();
164
165 /* Setup TRDC for DDR access */
166 trdc_init();
167
168 /* DDR initialization */
169 spl_dram_init();
170
171 /* Put M33 into CPUWAIT for following kick */
172 ret = m33_prepare();
173 if (!ret)
174 printf("M33 prepare ok\n");
175
176 board_init_r(NULL, 0);
177}