Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / b85efc244db5dd226708d07d5d89e1f43f4513bb / . / examples / Makefile
blob: 300ac537224a349ca225d147a96293989802504b [file] [log] [blame]
wdenk717b5aa2002-04-27 11:09:31 +0000[diff] [blame]1#
wdenk3203c8f2004-07-10 21:45:47 +0000[diff] [blame]2# (C) Copyright 2000-2004
wdenk717b5aa2002-04-27 11:09:31 +0000[diff] [blame]3# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4#
5# See file CREDITS for list of people who contributed to this
6# project.
7#
8# This program is free software; you can redistribute it and/or
9# modify it under the terms of the GNU General Public License as
10# published by the Free Software Foundation; either version 2 of
11# the License, or (at your option) any later version.
12#
13# This program is distributed in the hope that it will be useful,
14# but WITHOUT ANY WARRANTY; without even the implied warranty of
15# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16# GNU General Public License for more details.
17#
18# You should have received a copy of the GNU General Public License
19# along with this program; if not, write to the Free Software
20# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21# MA 02111-1307 USA
22#
23
wdenk874ac262003-07-24 23:38:38 +0000[diff] [blame]24ifeq ($(ARCH),ppc)
wdenk717b5aa2002-04-27 11:09:31 +0000[diff] [blame]25LOAD_ADDR = 0x40000
wdenk874ac262003-07-24 23:38:38 +0000[diff] [blame]26endif
27
28ifeq ($(ARCH),i386)
29LOAD_ADDR = 0x40000
30endif
31
32ifeq ($(ARCH),arm)
33LOAD_ADDR = 0xc100000
34endif
35
36ifeq ($(ARCH),mips)
37LOAD_ADDR = 0x80200000 -T mips.lds
38endif
wdenk717b5aa2002-04-27 11:09:31 +0000[diff] [blame]39
wdenk60164a82003-10-08 23:26:14 +0000[diff] [blame]40ifeq ($(ARCH),nios)
wdenke4adb352004-05-19 21:33:14 +0000[diff] [blame]41LOAD_ADDR = 0x00800000 -L $(gcclibdir)/m32 -T nios.lds
wdenk60164a82003-10-08 23:26:14 +0000[diff] [blame]42endif
43
wdenkef3386f2004-10-10 21:27:30 +0000[diff] [blame]44ifeq ($(ARCH),nios2)
45LOAD_ADDR = 0x00800000 -L $(gcclibdir) -T nios2.lds
46endif
47
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]48ifeq ($(ARCH),m68k)
49LOAD_ADDR = 0x20000 -L $(clibdir)
50endif
51
wdenk12490652004-04-18 21:13:41 +0000[diff] [blame]52ifeq ($(ARCH),microblaze)
53LOAD_ADDR = 0x80F00000
54endif
55
wdenk717b5aa2002-04-27 11:09:31 +0000[diff] [blame]56include $(TOPDIR)/config.mk
57
58SREC = hello_world.srec
wdenk5da7f2f2004-01-03 00:43:19 +0000[diff] [blame]59BIN = hello_world.bin hello_world
wdenk717b5aa2002-04-27 11:09:31 +0000[diff] [blame]60
wdenkabda5ca2003-05-31 18:35:21 +0000[diff] [blame]61ifeq ($(ARCH),i386)
62SREC += 82559_eeprom.srec
wdenk5da7f2f2004-01-03 00:43:19 +0000[diff] [blame]63BIN += 82559_eeprom.bin 82559_eeprom
wdenkabda5ca2003-05-31 18:35:21 +0000[diff] [blame]64endif
65
wdenk8dba0502003-03-31 16:34:49 +0000[diff] [blame]66ifeq ($(ARCH),ppc)
67SREC += sched.srec
wdenk5da7f2f2004-01-03 00:43:19 +0000[diff] [blame]68BIN += sched.bin sched
wdenk8dba0502003-03-31 16:34:49 +0000[diff] [blame]69endif
70
wdenk717b5aa2002-04-27 11:09:31 +0000[diff] [blame]71# The following example is pretty 8xx specific...
72ifeq ($(CPU),mpc8xx)
73SREC += timer.srec
wdenk5da7f2f2004-01-03 00:43:19 +0000[diff] [blame]74BIN += timer.bin timer
wdenk717b5aa2002-04-27 11:09:31 +0000[diff] [blame]75endif
76
wdenkb02744a2003-04-05 00:53:31 +0000[diff] [blame]77# The following example is 8260 specific...
78ifeq ($(CPU),mpc8260)
79SREC += mem_to_mem_idma2intr.srec
wdenk5da7f2f2004-01-03 00:43:19 +0000[diff] [blame]80BIN += mem_to_mem_idma2intr.bin mem_to_mem_idma2intr
wdenkb02744a2003-04-05 00:53:31 +0000[diff] [blame]81endif
82
wdenk717b5aa2002-04-27 11:09:31 +0000[diff] [blame]83# Utility for resetting i82559 EEPROM
84ifeq ($(BOARD),oxc)
85SREC += eepro100_eeprom.srec
wdenk5da7f2f2004-01-03 00:43:19 +0000[diff] [blame]86BIN += eepro100_eeprom.bin eepro100_eeprom
wdenk717b5aa2002-04-27 11:09:31 +0000[diff] [blame]87endif
88
wdenkbd1575f2003-10-14 19:43:55 +0000[diff] [blame]89ifeq ($(BIG_ENDIAN),y)
90EX_LDFLAGS += -EB
91endif
92
wdenk717b5aa2002-04-27 11:09:31 +0000[diff] [blame]93OBJS = $(SREC:.srec=.o)
94
wdenk874ac262003-07-24 23:38:38 +0000[diff] [blame]95LIB = libstubs.a
96LIBAOBJS=
wdenk8dba0502003-03-31 16:34:49 +0000[diff] [blame]97ifeq ($(ARCH),ppc)
98LIBAOBJS+= $(ARCH)_longjmp.o $(ARCH)_setjmp.o
99endif
wdenk874ac262003-07-24 23:38:38 +0000[diff] [blame]100LIBCOBJS= stubs.o
wdenk717b5aa2002-04-27 11:09:31 +0000[diff] [blame]101LIBOBJS = $(LIBAOBJS) $(LIBCOBJS)
102
wdenk710e3502003-08-29 20:57:53 +0000[diff] [blame]103gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]104clibdir := $(shell dirname `$(CC) $(CFLAGS) -print-file-name=libc.a`)
wdenk710e3502003-08-29 20:57:53 +0000[diff] [blame]105
wdenk717b5aa2002-04-27 11:09:31 +0000[diff] [blame]106CPPFLAGS += -I..
107
wdenkd3341052005-01-09 23:48:14 +0000[diff] [blame]108all: .depend $(OBJS) $(LIB) $(SREC) $(BIN)
wdenk717b5aa2002-04-27 11:09:31 +0000[diff] [blame]109
110#########################################################################
111$(LIB): .depend $(LIBOBJS)
112 $(AR) crv $@ $(LIBOBJS)
113
wdenk5da7f2f2004-01-03 00:43:19 +0000[diff] [blame]114%: %.o $(LIB)
wdenkbd1575f2003-10-14 19:43:55 +0000[diff] [blame]115 $(LD) -g $(EX_LDFLAGS) -Ttext $(LOAD_ADDR) \
wdenk5da7f2f2004-01-03 00:43:19 +0000[diff] [blame]116 -o $@ -e $(<:.o=) $< $(LIB) \
wdenk710e3502003-08-29 20:57:53 +0000[diff] [blame]117 -L$(gcclibdir) -lgcc
wdenk5da7f2f2004-01-03 00:43:19 +0000[diff] [blame]118%.srec: %
119 $(OBJCOPY) -O srec $< $@ 2>/dev/null
wdenk717b5aa2002-04-27 11:09:31 +0000[diff] [blame]120
wdenk5da7f2f2004-01-03 00:43:19 +0000[diff] [blame]121%.bin: %
122 $(OBJCOPY) -O binary $< $@ 2>/dev/null
wdenkc8434db2003-03-26 06:55:25 +0000[diff] [blame]123
wdenk717b5aa2002-04-27 11:09:31 +0000[diff] [blame]124#########################################################################
125
126.depend: Makefile $(OBJS:.o=.c) $(LIBCOBJS:.o=.c) $(LIBAOBJS:.o=.S)
127 $(CC) -M $(CFLAGS) $(OBJS:.o=.c) $(LIBCOBJS:.o=.c) $(LIBAOBJS:.o=.S) > $@
128
129sinclude .depend
130
131#########################################################################