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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Angelo Dureghello67c4e482017-08-07 01:17:18 +02002/*
3 * Sysam stmark2 board configuration
4 *
5 * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
Angelo Dureghello67c4e482017-08-07 01:17:18 +02006 */
7
8#ifndef __STMARK2_CONFIG_H
9#define __STMARK2_CONFIG_H
10
Mario Six790d8442018-03-28 14:38:20 +020011#define CONFIG_HOSTNAME "stmark2"
Angelo Dureghello67c4e482017-08-07 01:17:18 +020012
Angelo Dureghello67c4e482017-08-07 01:17:18 +020013#define CONFIG_SYS_UART_PORT 0
Angelo Dureghello67c4e482017-08-07 01:17:18 +020014
15#define LDS_BOARD_TEXT \
16 board/sysam/stmark2/sbf_dram_init.o (.text*)
17
Angelo Dureghello67c4e482017-08-07 01:17:18 +020018#define CONFIG_EXTRA_ENV_SETTINGS \
19 "kern_size=0x700000\0" \
20 "loadaddr=0x40001000\0" \
21 "-(rootfs)\0" \
22 "update_uboot=loady ${loadaddr}; " \
23 "sf probe 0:1 50000000; " \
24 "sf erase 0 0x80000; " \
25 "sf write ${loadaddr} 0 ${filesize}\0" \
26 "update_kernel=loady ${loadaddr}; " \
27 "setenv kern_size ${filesize}; saveenv; " \
28 "sf probe 0:1 50000000; " \
29 "sf erase 0x100000 0x700000; " \
30 "sf write ${loadaddr} 0x100000 ${filesize}\0" \
31 "update_rootfs=loady ${loadaddr}; " \
32 "sf probe 0:1 50000000; " \
33 "sf erase 0x00800000 0x100000; " \
34 "sf write ${loadaddr} 0x00800000 ${filesize}\0" \
35 ""
36
37/* Realtime clock */
Angelo Dureghello67c4e482017-08-07 01:17:18 +020038#define CONFIG_RTC_MCFRRTC
39#define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000
40
Angelo Dureghello67c4e482017-08-07 01:17:18 +020041#define CONFIG_SYS_SBFHDR_SIZE 0x7
42
Angelo Dureghello67c4e482017-08-07 01:17:18 +020043/* Input, PCI, Flexbus, and VCO */
44#define CONFIG_EXTRA_CLOCK
45
46#define CONFIG_PRAM 2048 /* 2048 KB */
Angelo Dureghello67c4e482017-08-07 01:17:18 +020047#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
48
49/* Print Buffer Size */
50#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
51 sizeof(CONFIG_SYS_PROMPT) + 16)
52#define CONFIG_SYS_MAXARGS 16
53/* Boot Argument Buffer Size */
54#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
55
Angelo Dureghello67c4e482017-08-07 01:17:18 +020056#define CONFIG_SYS_MBAR 0xFC000000
57
58/*
59 * Definitions for initial stack pointer and data area (in internal SRAM)
60 */
61#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
62/* End of used area in internal SRAM */
63#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
64#define CONFIG_SYS_INIT_RAM_CTRL 0x221
65#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \
66 GENERATED_GBL_DATA_SIZE) - 32)
67#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
68#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
69
70/*
71 * Start addresses for the final memory configuration
72 * (Set up by the startup code)
73 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
74 */
75#define CONFIG_SYS_SDRAM_BASE 0x40000000
76#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
77
Angelo Dureghello67c4e482017-08-07 01:17:18 +020078#define CONFIG_SYS_DRAM_TEST
79
80#if defined(CONFIG_CF_SBF)
81#define CONFIG_SERIAL_BOOT
82#endif
83
Angelo Dureghello67c4e482017-08-07 01:17:18 +020084#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024)
85/* Reserve 256 kB for Monitor */
86#define CONFIG_SYS_MONITOR_LEN (256 << 10)
Angelo Dureghello67c4e482017-08-07 01:17:18 +020087
88/*
89 * For booting Linux, the board info and command line data
90 * have to be in the first 8 MB of memory, since this is
91 * the maximum mapped by the Linux kernel during initialization ??
92 */
93/* Initial Memory map for Linux */
94#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
95 (CONFIG_SYS_SDRAM_SIZE << 20))
96
97/* Configuration for environment
98 * Environment is embedded in u-boot in the second sector of the flash
99 */
100
Angelo Dureghello67c4e482017-08-07 01:17:18 +0200101/* Cache Configuration */
Angelo Dureghello67c4e482017-08-07 01:17:18 +0200102#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
103 CONFIG_SYS_INIT_RAM_SIZE - 8)
104#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
105 CONFIG_SYS_INIT_RAM_SIZE - 4)
106#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
107#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
108#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
109 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
110 CF_ACR_EN | CF_ACR_SM_ALL)
111#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
112 CF_CACR_ICINVA | CF_CACR_EUSP)
113#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
114 CF_CACR_DEC | CF_CACR_DDCM_P | \
115 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
116
117#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
118 CONFIG_SYS_INIT_RAM_SIZE - 12)
119
Angelo Durgehello68d46ad2019-11-15 23:54:15 +0100120#ifdef CONFIG_MCFFEC
Angelo Durgehello68d46ad2019-11-15 23:54:15 +0100121#define CONFIG_SYS_DISCOVER_PHY
Angelo Durgehello68d46ad2019-11-15 23:54:15 +0100122/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
123#ifndef CONFIG_SYS_DISCOVER_PHY
124#define FECDUPLEX FULL
125#define FECSPEED _100BASET
Angelo Durgehello68d46ad2019-11-15 23:54:15 +0100126#endif /* CONFIG_SYS_DISCOVER_PHY */
127#endif
Angelo Dureghello67c4e482017-08-07 01:17:18 +0200128#endif /* __STMARK2_CONFIG_H */