| developer | 18ec8d6 | 2020-11-12 16:35:52 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. |
| 4 | * |
| 5 | * Author: Weijie Gao <weijie.gao@mediatek.com> |
| 6 | */ |
| 7 | |
| 8 | #ifndef __CONFIG_MT7620_H |
| 9 | #define __CONFIG_MT7620_H |
| 10 | |
| developer | 18ec8d6 | 2020-11-12 16:35:52 +0800 | [diff] [blame] | 11 | #define CONFIG_SYS_MIPS_TIMER_FREQ 290000000 |
| 12 | |
| developer | 18ec8d6 | 2020-11-12 16:35:52 +0800 | [diff] [blame] | 13 | #define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 |
| 14 | |
| 15 | #define CONFIG_SYS_SDRAM_BASE 0x80000000 |
| developer | 18ec8d6 | 2020-11-12 16:35:52 +0800 | [diff] [blame] | 16 | |
| 17 | #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 |
| 18 | |
| 19 | #define CONFIG_SYS_BOOTM_LEN 0x1000000 |
| 20 | |
| 21 | #define CONFIG_SYS_MAXARGS 16 |
| 22 | #define CONFIG_SYS_CBSIZE 1024 |
| 23 | |
| developer | 18ec8d6 | 2020-11-12 16:35:52 +0800 | [diff] [blame] | 24 | /* SPL */ |
| developer | 18ec8d6 | 2020-11-12 16:35:52 +0800 | [diff] [blame] | 25 | |
| 26 | #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE |
| 27 | #define CONFIG_SPL_BSS_START_ADDR 0x80010000 |
| 28 | #define CONFIG_SPL_BSS_MAX_SIZE 0x10000 |
| 29 | #define CONFIG_SPL_MAX_SIZE 0x10000 |
| 30 | #define CONFIG_SPL_PAD_TO 0 |
| 31 | |
| 32 | /* Dummy value */ |
| 33 | #define CONFIG_SYS_UBOOT_BASE 0 |
| 34 | |
| 35 | #endif /* __CONFIG_MT7620_H */ |