| Vignesh R | 3a9dbf3 | 2019-02-05 17:31:24 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com |
| 4 | * |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | */ |
| 11 | |
| 12 | #ifndef K3_NAVSS_UDMA_HWDEF_H_ |
| 13 | #define K3_NAVSS_UDMA_HWDEF_H_ |
| 14 | |
| 15 | #define UDMA_PSIL_DST_THREAD_ID_OFFSET 0x8000 |
| 16 | |
| 17 | /* Global registers */ |
| 18 | #define UDMA_REV_REG 0x0 |
| 19 | #define UDMA_PERF_CTL_REG 0x4 |
| 20 | #define UDMA_EMU_CTL_REG 0x8 |
| 21 | #define UDMA_PSIL_TO_REG 0x10 |
| 22 | #define UDMA_UTC_CTL_REG 0x1c |
| 23 | #define UDMA_CAP_REG(i) (0x20 + (i * 4)) |
| 24 | #define UDMA_RX_FLOW_ID_FW_OES_REG 0x80 |
| 25 | #define UDMA_RX_FLOW_ID_FW_STATUS_REG 0x88 |
| 26 | |
| 27 | /* RX Flow regs */ |
| 28 | #define UDMA_RFLOW_RFA_REG 0x0 |
| 29 | #define UDMA_RFLOW_RFB_REG 0x4 |
| 30 | #define UDMA_RFLOW_RFC_REG 0x8 |
| 31 | #define UDMA_RFLOW_RFD_REG 0xc |
| 32 | #define UDMA_RFLOW_RFE_REG 0x10 |
| 33 | #define UDMA_RFLOW_RFF_REG 0x14 |
| 34 | #define UDMA_RFLOW_RFG_REG 0x18 |
| 35 | #define UDMA_RFLOW_RFH_REG 0x1c |
| 36 | |
| 37 | #define UDMA_RFLOW_REG(x) (UDMA_RFLOW_RF##x##_REG) |
| 38 | |
| 39 | /* TX chan regs */ |
| 40 | #define UDMA_TCHAN_TCFG_REG 0x0 |
| 41 | #define UDMA_TCHAN_TCREDIT_REG 0x4 |
| 42 | #define UDMA_TCHAN_TCQ_REG 0x14 |
| 43 | #define UDMA_TCHAN_TOES_REG(i) (0x20 + (i) * 4) |
| 44 | #define UDMA_TCHAN_TEOES_REG 0x60 |
| 45 | #define UDMA_TCHAN_TPRI_CTRL_REG 0x64 |
| 46 | #define UDMA_TCHAN_THREAD_ID_REG 0x68 |
| 47 | #define UDMA_TCHAN_TFIFO_DEPTH_REG 0x70 |
| 48 | #define UDMA_TCHAN_TST_SCHED_REG 0x80 |
| 49 | |
| 50 | /* RX chan regs */ |
| 51 | #define UDMA_RCHAN_RCFG_REG 0x0 |
| 52 | #define UDMA_RCHAN_RCQ_REG 0x14 |
| 53 | #define UDMA_RCHAN_ROES_REG(i) (0x20 + (i) * 4) |
| 54 | #define UDMA_RCHAN_REOES_REG 0x60 |
| 55 | #define UDMA_RCHAN_RPRI_CTRL_REG 0x64 |
| 56 | #define UDMA_RCHAN_THREAD_ID_REG 0x68 |
| 57 | #define UDMA_RCHAN_RST_SCHED_REG 0x80 |
| 58 | #define UDMA_RCHAN_RFLOW_RNG_REG 0xf0 |
| 59 | |
| 60 | /* TX chan RT regs */ |
| 61 | #define UDMA_TCHAN_RT_CTL_REG 0x0 |
| 62 | #define UDMA_TCHAN_RT_SWTRIG_REG 0x8 |
| 63 | #define UDMA_TCHAN_RT_STDATA_REG 0x80 |
| 64 | |
| 65 | #define UDMA_TCHAN_RT_PEERn_REG(i) (0x200 + (i * 0x4)) |
| 66 | #define UDMA_TCHAN_RT_PEER_STATIC_TR_XY_REG \ |
| 67 | UDMA_TCHAN_RT_PEERn_REG(0) /* PSI-L: 0x400 */ |
| 68 | #define UDMA_TCHAN_RT_PEER_STATIC_TR_Z_REG \ |
| 69 | UDMA_TCHAN_RT_PEERn_REG(1) /* PSI-L: 0x401 */ |
| 70 | #define UDMA_TCHAN_RT_PEER_BCNT_REG \ |
| 71 | UDMA_TCHAN_RT_PEERn_REG(4) /* PSI-L: 0x404 */ |
| 72 | #define UDMA_TCHAN_RT_PEER_RT_EN_REG \ |
| 73 | UDMA_TCHAN_RT_PEERn_REG(8) /* PSI-L: 0x408 */ |
| 74 | |
| 75 | #define UDMA_TCHAN_RT_PCNT_REG 0x400 |
| 76 | #define UDMA_TCHAN_RT_BCNT_REG 0x408 |
| 77 | #define UDMA_TCHAN_RT_SBCNT_REG 0x410 |
| 78 | |
| 79 | /* RX chan RT regs */ |
| 80 | #define UDMA_RCHAN_RT_CTL_REG 0x0 |
| 81 | #define UDMA_RCHAN_RT_SWTRIG_REG 0x8 |
| 82 | #define UDMA_RCHAN_RT_STDATA_REG 0x80 |
| 83 | |
| 84 | #define UDMA_RCHAN_RT_PEERn_REG(i) (0x200 + (i * 0x4)) |
| 85 | #define UDMA_RCHAN_RT_PEER_STATIC_TR_XY_REG \ |
| 86 | UDMA_RCHAN_RT_PEERn_REG(0) /* PSI-L: 0x400 */ |
| 87 | #define UDMA_RCHAN_RT_PEER_STATIC_TR_Z_REG \ |
| 88 | UDMA_RCHAN_RT_PEERn_REG(1) /* PSI-L: 0x401 */ |
| 89 | #define UDMA_RCHAN_RT_PEER_BCNT_REG \ |
| 90 | UDMA_RCHAN_RT_PEERn_REG(4) /* PSI-L: 0x404 */ |
| 91 | #define UDMA_RCHAN_RT_PEER_RT_EN_REG \ |
| 92 | UDMA_RCHAN_RT_PEERn_REG(8) /* PSI-L: 0x408 */ |
| 93 | |
| 94 | #define UDMA_RCHAN_RT_PCNT_REG 0x400 |
| 95 | #define UDMA_RCHAN_RT_BCNT_REG 0x408 |
| 96 | #define UDMA_RCHAN_RT_SBCNT_REG 0x410 |
| 97 | |
| 98 | /* UDMA_TCHAN_TCFG_REG/UDMA_RCHAN_RCFG_REG */ |
| 99 | #define UDMA_CHAN_CFG_PAUSE_ON_ERR BIT(31) |
| 100 | #define UDMA_TCHAN_CFG_FILT_EINFO BIT(30) |
| 101 | #define UDMA_TCHAN_CFG_FILT_PSWORDS BIT(29) |
| 102 | #define UDMA_CHAN_CFG_ATYPE_MASK GENMASK(25, 24) |
| 103 | #define UDMA_CHAN_CFG_ATYPE_SHIFT 24 |
| 104 | #define UDMA_CHAN_CFG_CHAN_TYPE_MASK GENMASK(19, 16) |
| 105 | #define UDMA_CHAN_CFG_CHAN_TYPE_SHIFT 16 |
| 106 | /* |
| 107 | * PBVR - using pass by value rings |
| 108 | * PBRR - using pass by reference rings |
| 109 | * 3RDP - Third Party DMA |
| 110 | * BC - Block Copy |
| 111 | * SB - single buffer packet mode enabled |
| 112 | */ |
| 113 | #define UDMA_CHAN_CFG_CHAN_TYPE_PACKET_PBRR \ |
| 114 | (2 << UDMA_CHAN_CFG_CHAN_TYPE_SHIFT) |
| 115 | #define UDMA_CHAN_CFG_CHAN_TYPE_PACKET_SB_PBRR \ |
| 116 | (3 << UDMA_CHAN_CFG_CHAN_TYPE_SHIFT) |
| 117 | #define UDMA_CHAN_CFG_CHAN_TYPE_3RDP_PBRR \ |
| 118 | (10 << UDMA_CHAN_CFG_CHAN_TYPE_SHIFT) |
| 119 | #define UDMA_CHAN_CFG_CHAN_TYPE_3RDP_PBVR \ |
| 120 | (11 << UDMA_CHAN_CFG_CHAN_TYPE_SHIFT) |
| 121 | #define UDMA_CHAN_CFG_CHAN_TYPE_3RDP_BC_PBRR \ |
| 122 | (12 << UDMA_CHAN_CFG_CHAN_TYPE_SHIFT) |
| 123 | #define UDMA_RCHAN_CFG_IGNORE_SHORT BIT(15) |
| 124 | #define UDMA_RCHAN_CFG_IGNORE_LONG BIT(14) |
| 125 | #define UDMA_TCHAN_CFG_SUPR_TDPKT BIT(8) |
| 126 | #define UDMA_CHAN_CFG_FETCH_SIZE_MASK GENMASK(6, 0) |
| 127 | #define UDMA_CHAN_CFG_FETCH_SIZE_SHIFT 0 |
| 128 | |
| 129 | /* UDMA_TCHAN_RT_CTL_REG/UDMA_RCHAN_RT_CTL_REG */ |
| 130 | #define UDMA_CHAN_RT_CTL_EN BIT(31) |
| 131 | #define UDMA_CHAN_RT_CTL_TDOWN BIT(30) |
| 132 | #define UDMA_CHAN_RT_CTL_PAUSE BIT(29) |
| 133 | #define UDMA_CHAN_RT_CTL_FTDOWN BIT(28) |
| 134 | #define UDMA_CHAN_RT_CTL_ERROR BIT(0) |
| 135 | |
| 136 | /* UDMA_TCHAN_RT_PEER_RT_EN_REG/UDMA_RCHAN_RT_PEER_RT_EN_REG (PSI-L: 0x408) */ |
| 137 | #define UDMA_PEER_RT_EN_ENABLE BIT(31) |
| 138 | #define UDMA_PEER_RT_EN_TEARDOWN BIT(30) |
| 139 | #define UDMA_PEER_RT_EN_PAUSE BIT(29) |
| 140 | #define UDMA_PEER_RT_EN_FLUSH BIT(28) |
| 141 | #define UDMA_PEER_RT_EN_IDLE BIT(1) |
| 142 | |
| 143 | /* RX Flow reg RFA */ |
| 144 | #define UDMA_RFLOW_RFA_EINFO BIT(30) |
| 145 | #define UDMA_RFLOW_RFA_PSINFO BIT(29) |
| 146 | #define UDMA_RFLOW_RFA_ERR_HANDLING BIT(28) |
| 147 | #define UDMA_RFLOW_RFA_DESC_TYPE_MASK GENMASK(27, 26) |
| 148 | #define UDMA_RFLOW_RFA_DESC_TYPE_SHIFT 26 |
| 149 | #define UDMA_RFLOW_RFA_PS_LOC BIT(25) |
| 150 | #define UDMA_RFLOW_RFA_SOP_OFF_MASK GENMASK(24, 16) |
| 151 | #define UDMA_RFLOW_RFA_SOP_OFF_SHIFT 16 |
| 152 | #define UDMA_RFLOW_RFA_DEST_QNUM_MASK GENMASK(15, 0) |
| 153 | #define UDMA_RFLOW_RFA_DEST_QNUM_SHIFT 0 |
| 154 | |
| 155 | /* RX Flow reg RFC */ |
| 156 | #define UDMA_RFLOW_RFC_SRC_TAG_HI_SEL_SHIFT 28 |
| 157 | #define UDMA_RFLOW_RFC_SRC_TAG_LO_SEL_SHIFT 24 |
| 158 | #define UDMA_RFLOW_RFC_DST_TAG_HI_SEL_SHIFT 20 |
| 159 | #define UDMA_RFLOW_RFC_DST_TAG_LO_SE_SHIFT 16 |
| 160 | |
| 161 | /* |
| 162 | * UDMA_TCHAN_RT_PEER_STATIC_TR_XY_REG / |
| 163 | * UDMA_RCHAN_RT_PEER_STATIC_TR_XY_REG |
| 164 | */ |
| 165 | #define PDMA_STATIC_TR_X_MASK GENMASK(26, 24) |
| 166 | #define PDMA_STATIC_TR_X_SHIFT (24) |
| 167 | #define PDMA_STATIC_TR_Y_MASK GENMASK(11, 0) |
| 168 | #define PDMA_STATIC_TR_Y_SHIFT (0) |
| 169 | |
| 170 | #define PDMA_STATIC_TR_Y(x) \ |
| 171 | (((x) << PDMA_STATIC_TR_Y_SHIFT) & PDMA_STATIC_TR_Y_MASK) |
| 172 | #define PDMA_STATIC_TR_X(x) \ |
| 173 | (((x) << PDMA_STATIC_TR_X_SHIFT) & PDMA_STATIC_TR_X_MASK) |
| 174 | |
| 175 | /* |
| 176 | * UDMA_TCHAN_RT_PEER_STATIC_TR_Z_REG / |
| 177 | * UDMA_RCHAN_RT_PEER_STATIC_TR_Z_REG |
| 178 | */ |
| 179 | #define PDMA_STATIC_TR_Z_MASK GENMASK(11, 0) |
| 180 | #define PDMA_STATIC_TR_Z_SHIFT (0) |
| 181 | #define PDMA_STATIC_TR_Z(x) \ |
| 182 | (((x) << PDMA_STATIC_TR_Z_SHIFT) & PDMA_STATIC_TR_Z_MASK) |
| 183 | |
| 184 | #endif /* K3_NAVSS_UDMA_HWDEF_H_ */ |