| Svyatoslav Ryhel | 3212879 | 2023-02-14 19:35:34 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
| 2 | /* |
| 3 | * (C) Copyright 2010-2013 |
| 4 | * NVIDIA Corporation <www.nvidia.com> |
| 5 | * |
| 6 | * (C) Copyright 2021 |
| 7 | * Svyatoslav Ryhel <clamor95@gmail.com> |
| 8 | */ |
| 9 | |
| Svyatoslav Ryhel | 3212879 | 2023-02-14 19:35:34 +0200 | [diff] [blame] | 10 | #include <asm/arch-tegra/tegra_i2c.h> |
| 11 | #include <linux/delay.h> |
| 12 | |
| 13 | /* I2C addr is in 8 bit */ |
| 14 | #define TPS65911_I2C_ADDR 0x5A |
| 15 | #define TPS65911_VDDCTRL_OP_REG 0x28 |
| 16 | #define TPS65911_VDDCTRL_SR_REG 0x27 |
| 17 | #define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG) |
| 18 | #define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG) |
| 19 | |
| 20 | void pmic_enable_cpu_vdd(void) |
| 21 | { |
| 22 | /* |
| 23 | * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus. |
| 24 | * First set VDD to 1.0125V, then enable the VDD regulator. |
| 25 | */ |
| 26 | udelay(1000); |
| 27 | tegra_i2c_ll_write(TPS65911_I2C_ADDR, |
| 28 | TPS65911_VDDCTRL_OP_DATA); |
| 29 | udelay(1000); |
| 30 | tegra_i2c_ll_write(TPS65911_I2C_ADDR, |
| 31 | TPS65911_VDDCTRL_SR_DATA); |
| 32 | udelay(10 * 1000); |
| 33 | } |