blob: 43f856bf732476eaaffedccf97066634d478bb06 [file] [log] [blame]
Peng Fanb15705a2021-08-07 16:00:35 +08001// SPDX-License-Identifier: GPL-2.0+
2/*
Peng Fanadbbc752021-08-07 16:01:04 +08003 * Copyright 2020-2021 NXP
4 */
5
Peng Fanadbbc752021-08-07 16:01:04 +08006#include <asm/io.h>
7#include <asm/arch/imx-regs.h>
8#include <asm/arch/iomux.h>
9
10static void *base = (void *)IOMUXC_BASE_ADDR;
11static void *base_mports = (void *)(0x280A1000);
12
13/*
14 * configures a single pad in the iomuxer
Peng Fanb15705a2021-08-07 16:00:35 +080015 */
Peng Fanadbbc752021-08-07 16:01:04 +080016void imx8ulp_iomux_setup_pad(iomux_cfg_t pad)
17{
18 u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
19 u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
20 u32 sel_input_ofs =
21 (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
22 u32 sel_input =
23 (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
24 u32 pad_ctrl_ofs = mux_ctrl_ofs;
25 u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
26
27 if (mux_mode & IOMUX_CONFIG_MPORTS) {
28 mux_mode &= ~IOMUX_CONFIG_MPORTS;
29 base = base_mports;
30 } else {
31 base = (void *)IOMUXC_BASE_ADDR;
32 }
33
34 __raw_writel(((mux_mode << IOMUXC_PCR_MUX_ALT_SHIFT) &
35 IOMUXC_PCR_MUX_ALT_MASK), base + mux_ctrl_ofs);
36
37 if (sel_input_ofs)
38 __raw_writel((sel_input << IOMUXC_PSMI_IMUX_ALT_SHIFT), base + sel_input_ofs);
39
40 if (!(pad_ctrl & NO_PAD_CTRL))
41 __raw_writel(((mux_mode << IOMUXC_PCR_MUX_ALT_SHIFT) &
42 IOMUXC_PCR_MUX_ALT_MASK) |
43 (pad_ctrl & (~IOMUXC_PCR_MUX_ALT_MASK)),
44 base + pad_ctrl_ofs);
45}
46
47/* configures a list of pads within declared with IOMUX_PADS macro */
48void imx8ulp_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list, u32 count)
49{
50 iomux_cfg_t const *p = pad_list;
51 int i;
52
53 for (i = 0; i < count; i++) {
54 imx8ulp_iomux_setup_pad(*p);
55 p++;
56 }
57}