blob: 7cfdc46d349ede08fd53882f6d34a3464f48f168 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Peng Fan88057bc2018-01-10 13:20:22 +08002/*
3 * Copyright 2017 NXP
4 *
5 * Peng Fan <peng.fan@nxp.com>
Peng Fan88057bc2018-01-10 13:20:22 +08006 */
7
Peng Fan88057bc2018-01-10 13:20:22 +08008#include <asm/arch/clock.h>
9#include <asm/arch/imx-regs.h>
10#include <asm/io.h>
11#include <errno.h>
12
Peng Fan88057bc2018-01-10 13:20:22 +080013static struct ccm_reg *ccm_reg = (struct ccm_reg *)CCM_BASE_ADDR;
14
Peng Fan99878462019-08-27 06:25:51 +000015#ifdef CONFIG_IMX8MQ
Peng Fan88057bc2018-01-10 13:20:22 +080016static struct clk_root_map root_array[] = {
17 {ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0,
18 {OSC_25M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
19 SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
20 SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK}
21 },
22 {ARM_M4_CLK_ROOT, CORE_CLOCK_SLICE, 1,
23 {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_250M_CLK,
24 SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
25 AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
26 },
27 {VPU_A53_CLK_ROOT, CORE_CLOCK_SLICE, 2,
28 {OSC_25M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
29 SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
30 SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, VPU_PLL_CLK}
31 },
32 {GPU_CORE_CLK_ROOT, CORE_CLOCK_SLICE, 3,
33 {OSC_25M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
34 SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
35 AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
36 },
37 {GPU_SHADER_CLK_ROOT, CORE_CLOCK_SLICE, 4,
38 {OSC_25M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
39 SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
40 AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
41 },
42 {MAIN_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 0,
43 {OSC_25M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_800M_CLK,
44 SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_1000M_CLK,
45 AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_100M_CLK}
46 },
47 {ENET_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 1,
48 {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
49 SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
50 AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
51 },
52 {NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2,
53 {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
54 SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK,
55 SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL1_CLK}
56 },
57 {VPU_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 3,
58 {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, VPU_PLL_CLK,
59 AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
60 SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_100M_CLK}
61 },
62 {DISPLAY_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 4,
63 {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
64 SYSTEM_PLL3_CLK, SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK,
65 EXT_CLK_1, EXT_CLK_4}
66 },
67 {DISPLAY_APB_CLK_ROOT, BUS_CLOCK_SLICE, 5,
68 {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
69 SYSTEM_PLL3_CLK, SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK,
70 EXT_CLK_1, EXT_CLK_3}
71 },
72 {DISPLAY_RTRM_CLK_ROOT, BUS_CLOCK_SLICE, 6,
73 {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_200M_CLK,
74 SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
75 EXT_CLK_2, EXT_CLK_3}
76 },
77 {USB_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 7,
78 {OSC_25M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
79 SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
80 EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
81 },
82 {GPU_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 8,
83 {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
84 SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
85 AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
86 },
87 {GPU_AHB_CLK_ROOT, BUS_CLOCK_SLICE, 9,
88 {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
89 SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
90 AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
91 },
92 {NOC_CLK_ROOT, BUS_CLOCK_SLICE, 10,
93 {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK,
94 SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK,
95 AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
96 },
97 {NOC_APB_CLK_ROOT, BUS_CLOCK_SLICE, 11,
98 {OSC_25M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL3_CLK,
99 SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_200M_CLK,
100 SYSTEM_PLL1_800M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
101 },
102 {AHB_CLK_ROOT, AHB_CLOCK_SLICE, 0,
103 {OSC_25M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_800M_CLK,
104 SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_125M_CLK,
105 SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
106 },
107 {IPG_CLK_ROOT, IPG_CLOCK_SLICE, 0,
108 {}
109 },
110 {AUDIO_AHB_CLK_ROOT, AHB_CLOCK_SLICE, 1,
111 {OSC_25M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
112 SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_166M_CLK,
113 SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
114 },
115 {MIPI_DSI_ESC_RX_CLK_ROOT, AHB_CLOCK_SLICE, 2,
116 {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_40M_CLK,
117 SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
118 SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL1_CLK },
119 },
120 {DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0,
121 {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_100M_CLK,
122 SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_250M_CLK,
123 SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL1_266M_CLK}
124 },
125 {DRAM_APB_CLK_ROOT, IP_CLOCK_SLICE, 1,
126 {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
127 SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
128 SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
129 },
130 {VPU_G1_CLK_ROOT, IP_CLOCK_SLICE, 2,
131 {OSC_25M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
132 SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK,
133 SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
134 },
135 {VPU_G2_CLK_ROOT, IP_CLOCK_SLICE, 3,
136 {OSC_25M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
137 SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK,
138 SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
139 },
140 {DISPLAY_DTRC_CLK_ROOT, IP_CLOCK_SLICE, 4,
141 {OSC_25M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
142 SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK,
143 SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK}
144 },
145 {DISPLAY_DC8000_CLK_ROOT, IP_CLOCK_SLICE, 5,
146 {OSC_25M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
147 SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK,
148 SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK}
149 },
150 {PCIE1_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 6,
151 {OSC_25M_CLK, SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
152 SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
153 SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL3_CLK}
154 },
155 {PCIE1_PHY_CLK_ROOT, IP_CLOCK_SLICE, 7,
156 {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_500M_CLK,
157 EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
158 SYSTEM_PLL1_400M_CLK}
159 },
160 {PCIE1_AUX_CLK_ROOT, IP_CLOCK_SLICE, 8,
161 {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK,
162 SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
163 SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK}
164 },
165 {DC_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 9,
166 {OSC_25M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
167 AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
168 SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
169 },
170 {LCDIF_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 10,
171 {OSC_25M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
172 AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
173 SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
174 },
175 {SAI1_CLK_ROOT, IP_CLOCK_SLICE, 11,
176 {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
177 VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
178 OSC_27M_CLK, EXT_CLK_1, EXT_CLK_2}
179 },
180 {SAI2_CLK_ROOT, IP_CLOCK_SLICE, 12,
181 {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
182 VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
183 OSC_27M_CLK, EXT_CLK_2, EXT_CLK_3}
184 },
185 {SAI3_CLK_ROOT, IP_CLOCK_SLICE, 13,
186 {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
187 VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
188 OSC_27M_CLK, EXT_CLK_3, EXT_CLK_4}
189 },
190 {SAI4_CLK_ROOT, IP_CLOCK_SLICE, 14,
191 {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
192 VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
193 OSC_27M_CLK, EXT_CLK_1, EXT_CLK_2}
194 },
195 {SAI5_CLK_ROOT, IP_CLOCK_SLICE, 15,
196 {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
197 VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
198 OSC_27M_CLK, EXT_CLK_2, EXT_CLK_3}
199 },
200 {SAI6_CLK_ROOT, IP_CLOCK_SLICE, 16,
201 {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
202 VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
203 OSC_27M_CLK, EXT_CLK_3, EXT_CLK_4}
204 },
205 {SPDIF1_CLK_ROOT, IP_CLOCK_SLICE, 17,
206 {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
207 VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
208 OSC_27M_CLK, EXT_CLK_2, EXT_CLK_3}
209 },
210 {SPDIF2_CLK_ROOT, IP_CLOCK_SLICE, 18,
211 {OSC_25M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
212 VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
213 OSC_27M_CLK, EXT_CLK_3, EXT_CLK_4}
214 },
215 {ENET_REF_CLK_ROOT, IP_CLOCK_SLICE, 19,
216 {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK,
217 SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
218 AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4}
219 },
220 {ENET_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 20,
221 {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
222 EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
223 VIDEO_PLL_CLK}
224 },
225 {ENET_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 21,
226 {OSC_25M_CLK, SYSTEM_PLL2_50M_CLK, SYSTEM_PLL2_125M_CLK,
227 SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_500M_CLK,
228 AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
229 },
230 {NAND_CLK_ROOT, IP_CLOCK_SLICE, 22,
231 {OSC_25M_CLK, SYSTEM_PLL2_500M_CLK, AUDIO_PLL1_CLK,
232 SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK,
233 SYSTEM_PLL2_250M_CLK, VIDEO_PLL_CLK}
234 },
235 {QSPI_CLK_ROOT, IP_CLOCK_SLICE, 23,
236 {OSC_25M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
237 SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
238 SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
239 },
240 {USDHC1_CLK_ROOT, IP_CLOCK_SLICE, 24,
241 {OSC_25M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
242 SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
243 SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
244 },
245 {USDHC2_CLK_ROOT, IP_CLOCK_SLICE, 25,
246 {OSC_25M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
247 SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
248 SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
249 },
250 {I2C1_CLK_ROOT, IP_CLOCK_SLICE, 26,
251 {OSC_25M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
252 SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
253 AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
254 },
255 {I2C2_CLK_ROOT, IP_CLOCK_SLICE, 27,
256 {OSC_25M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
257 SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
258 AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
259 },
260 {I2C3_CLK_ROOT, IP_CLOCK_SLICE, 28,
261 {OSC_25M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
262 SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
263 AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
264 },
265 {I2C4_CLK_ROOT, IP_CLOCK_SLICE, 29,
266 {OSC_25M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
267 SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
268 AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
269 },
270 {UART1_CLK_ROOT, IP_CLOCK_SLICE, 30,
271 {OSC_25M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
272 SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
273 EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
274 },
275 {UART2_CLK_ROOT, IP_CLOCK_SLICE, 31,
276 {OSC_25M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
277 SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
278 EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
279 },
280 {UART3_CLK_ROOT, IP_CLOCK_SLICE, 32,
281 {OSC_25M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
282 SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
283 EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
284 },
285 {UART4_CLK_ROOT, IP_CLOCK_SLICE, 33,
286 {OSC_25M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
287 SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
288 EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
289 },
290 {USB_CORE_REF_CLK_ROOT, IP_CLOCK_SLICE, 34,
291 {OSC_25M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
292 SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
293 EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
294 },
295 {USB_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 35,
296 {OSC_25M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
297 SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
298 EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
299 },
300 {GIC_CLK_ROOT, IP_CLOCK_SLICE, 36,
301 {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
302 SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_800M_CLK,
303 EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
304 },
305 {ECSPI1_CLK_ROOT, IP_CLOCK_SLICE, 37,
306 {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
307 SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
308 SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
309 },
310 {ECSPI2_CLK_ROOT, IP_CLOCK_SLICE, 38,
311 {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
312 SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
313 SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
314 },
315 {PWM1_CLK_ROOT, IP_CLOCK_SLICE, 39,
316 {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
317 SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
318 SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
319 },
320 {PWM2_CLK_ROOT, IP_CLOCK_SLICE, 40,
321 {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
322 SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
323 SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
324 },
325 {PWM3_CLK_ROOT, IP_CLOCK_SLICE, 41,
326 {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
327 SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
328 SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
329 },
330 {PWM4_CLK_ROOT, IP_CLOCK_SLICE, 42,
331 {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
332 SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
333 SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
334 },
335 {GPT1_CLK_ROOT, IP_CLOCK_SLICE, 43,
336 {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
337 SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
338 SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
339 },
340 {GPT2_CLK_ROOT, IP_CLOCK_SLICE, 44,
341 {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
342 SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
343 SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
344 },
345 {GPT3_CLK_ROOT, IP_CLOCK_SLICE, 45,
346 {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
347 SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
348 SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
349 },
350 {GPT4_CLK_ROOT, IP_CLOCK_SLICE, 46,
351 {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
352 SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
353 SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
354 },
355 {GPT5_CLK_ROOT, IP_CLOCK_SLICE, 47,
356 {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
357 SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
358 SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
359 },
360 {GPT6_CLK_ROOT, IP_CLOCK_SLICE, 48,
361 {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
362 SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
363 SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
364 },
365 {TRACE_CLK_ROOT, IP_CLOCK_SLICE, 49,
366 {OSC_25M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
367 VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
368 SYSTEM_PLL3_CLK, EXT_CLK_1, EXT_CLK_3}
369 },
370 {WDOG_CLK_ROOT, IP_CLOCK_SLICE, 50,
371 {OSC_25M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
372 VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
373 SYSTEM_PLL3_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_166M_CLK}
374 },
375 {WRCLK_CLK_ROOT, IP_CLOCK_SLICE, 51,
376 {OSC_25M_CLK, SYSTEM_PLL1_40M_CLK, VPU_PLL_CLK,
377 SYSTEM_PLL3_CLK, SYSTEM_PLL2_200M_CLK,
378 SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_100M_CLK}
379 },
380 {IPP_DO_CLKO1, IP_CLOCK_SLICE, 52,
381 {OSC_25M_CLK, SYSTEM_PLL1_800M_CLK, OSC_27M_CLK,
382 SYSTEM_PLL1_200M_CLK, AUDIO_PLL2_CLK,
383 SYSTEM_PLL2_500M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_80M_CLK}
384 },
385 {IPP_DO_CLKO2, IP_CLOCK_SLICE, 53,
386 {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_400M_CLK,
387 SYSTEM_PLL2_166M_CLK, SYSTEM_PLL3_CLK,
388 AUDIO_PLL1_CLK, VIDEO_PLL_CLK, OSC_32K_CLK}
389 },
390 {MIPI_DSI_CORE_CLK_ROOT, IP_CLOCK_SLICE, 54,
391 {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
392 SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
393 SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
394 },
395 {MIPI_DSI_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 55,
396 {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK,
397 SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
398 EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
399 },
400 {MIPI_DSI_DBI_CLK_ROOT, IP_CLOCK_SLICE, 56,
401 {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_100M_CLK,
402 SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
403 SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
404 },
405 {OLD_MIPI_DSI_ESC_CLK_ROOT, IP_CLOCK_SLICE, 57,
406 {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
407 SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
408 SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
409 },
410 {MIPI_CSI1_CORE_CLK_ROOT, IP_CLOCK_SLICE, 58,
411 {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
412 SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
413 SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
414 },
415 {MIPI_CSI1_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 59,
416 {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK,
417 SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
418 EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
419 },
420 {MIPI_CSI1_ESC_CLK_ROOT, IP_CLOCK_SLICE, 60,
421 {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
422 SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
423 SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
424 },
425 {MIPI_CSI2_CORE_CLK_ROOT, IP_CLOCK_SLICE, 61,
426 {OSC_25M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
427 SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
428 SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
429 },
430 {MIPI_CSI2_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 62,
431 {OSC_25M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK,
432 SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
433 EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
434 },
435 {MIPI_CSI2_ESC_CLK_ROOT, IP_CLOCK_SLICE, 63,
436 {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
437 SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
438 SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
439 },
440 {PCIE2_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 64,
441 {OSC_25M_CLK, SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
442 SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
443 SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL3_CLK}
444 },
445 {PCIE2_PHY_CLK_ROOT, IP_CLOCK_SLICE, 65,
446 {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_500M_CLK,
447 EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
448 EXT_CLK_4, SYSTEM_PLL1_400M_CLK}
449 },
450 {PCIE2_AUX_CLK_ROOT, IP_CLOCK_SLICE, 66,
451 {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK,
452 SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK,
453 SYSTEM_PLL1_80M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK}
454 },
455 {ECSPI3_CLK_ROOT, IP_CLOCK_SLICE, 67,
456 {OSC_25M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
457 SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
458 SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
459 },
460 {OLD_MIPI_DSI_ESC_RX_ROOT, IP_CLOCK_SLICE, 68,
461 {OSC_25M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
462 SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
463 SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK},
464 },
465 {DISPLAY_HDMI_CLK_ROOT, IP_CLOCK_SLICE, 69,
466 {OSC_25M_CLK, SYSTEM_PLL1_200M_CLK, SYSTEM_PLL2_200M_CLK,
467 VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
468 SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
469 },
470 {DRAM_SEL_CFG, DRAM_SEL_CLOCK_SLICE, 0,
471 {DRAM_PLL1_CLK}
472 },
473 {CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0,
Peng Fan3545c8a2020-04-22 10:55:56 +0800474 {ARM_A53_ALT_CLK, ARM_PLL_CLK}
Peng Fan88057bc2018-01-10 13:20:22 +0800475 },
476};
Peng Fan3545c8a2020-04-22 10:55:56 +0800477#elif defined(CONFIG_IMX8MM)
Peng Fan99878462019-08-27 06:25:51 +0000478static struct clk_root_map root_array[] = {
Frieder Schrempf46981642020-02-05 11:45:28 +0000479 {ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0,
480 {OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
481 SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
482 SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK}
483 },
Peng Fan3545c8a2020-04-22 10:55:56 +0800484 {ARM_M4_CLK_ROOT, CORE_CLOCK_SLICE, 1,
485 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_250M_CLK,
486 SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
487 AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
488 },
489 {VPU_A53_CLK_ROOT, CORE_CLOCK_SLICE, 2,
490 {OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
491 SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
492 SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, VPU_PLL_CLK}
493 },
494 {GPU3D_CLK_ROOT, CORE_CLOCK_SLICE, 3,
495 {OSC_24M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
496 SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
497 AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
498 },
499 {GPU2D_CLK_ROOT, CORE_CLOCK_SLICE, 4,
500 {OSC_24M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
501 SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
502 AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
503 },
Marek Vasut363725d2020-04-24 21:37:26 +0200504 {MAIN_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 0,
505 {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_800M_CLK,
506 SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_1000M_CLK,
507 AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_100M_CLK}
508 },
509 {ENET_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 1,
510 {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
511 SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
512 AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
513 },
Peng Fan99878462019-08-27 06:25:51 +0000514 {NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2,
515 {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
516 SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK,
517 SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL1_CLK}
518 },
Peng Fan3545c8a2020-04-22 10:55:56 +0800519 {VPU_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 3,
520 {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, VPU_PLL_CLK,
521 AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
522 SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_100M_CLK}
523 },
524 {DISPLAY_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 4,
525 {OSC_24M_CLK, SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
526 SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, AUDIO_PLL2_CLK,
527 EXT_CLK_1, EXT_CLK_4}
528 },
529 {DISPLAY_APB_CLK_ROOT, BUS_CLOCK_SLICE, 5,
530 {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
531 SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, AUDIO_PLL2_CLK,
532 EXT_CLK_1, EXT_CLK_3}
533 },
534 {DISPLAY_RTRM_CLK_ROOT, BUS_CLOCK_SLICE, 6,
535 {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_200M_CLK,
536 SYSTEM_PLL2_1000M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
537 EXT_CLK_2, EXT_CLK_3}
538 },
539 {USB_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 7,
540 {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
541 SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
542 EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
543 },
544 {GPU_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 8,
545 {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
546 SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
547 AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
548 },
549 {GPU_AHB_CLK_ROOT, BUS_CLOCK_SLICE, 9,
550 {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
551 SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
552 AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
553 },
Peng Fan99878462019-08-27 06:25:51 +0000554 {NOC_CLK_ROOT, BUS_CLOCK_SLICE, 10,
555 {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK,
556 SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK,
557 AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
558 },
559 {NOC_APB_CLK_ROOT, BUS_CLOCK_SLICE, 11,
560 {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL3_CLK,
561 SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_200M_CLK,
562 SYSTEM_PLL1_800M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
563 },
Peng Fan3545c8a2020-04-22 10:55:56 +0800564 {AHB_CLK_ROOT, AHB_CLOCK_SLICE, 0,
565 {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_800M_CLK,
566 SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_125M_CLK,
567 SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
568 },
569 {AUDIO_AHB_CLK_ROOT, AHB_CLOCK_SLICE, 1,
570 {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
571 SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_166M_CLK,
572 SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
573 },
574 {MIPI_DSI_ESC_RX_CLK_ROOT, AHB_CLOCK_SLICE, 2,
575 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
576 SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
577 SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
578 },
Peng Fan99878462019-08-27 06:25:51 +0000579 {DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0,
580 {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_100M_CLK,
581 SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_1000M_CLK,
582 SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL1_266M_CLK}
583 },
584 {DRAM_APB_CLK_ROOT, IP_CLOCK_SLICE, 1,
585 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
586 SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
587 SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
588 },
Peng Fan3545c8a2020-04-22 10:55:56 +0800589 {VPU_G1_CLK_ROOT, IP_CLOCK_SLICE, 2,
590 {OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
591 SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK,
592 SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
593 },
594 {VPU_G2_CLK_ROOT, IP_CLOCK_SLICE, 3,
595 {OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
596 SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK,
597 SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
598 },
599 {DISPLAY_DTRC_CLK_ROOT, IP_CLOCK_SLICE, 4,
600 {OSC_24M_CLK, VIDEO_PLL2_CLK, SYSTEM_PLL1_800M_CLK,
601 SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK,
602 VIDEO_PLL_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK}
603 },
604 {DISPLAY_DC8000_CLK_ROOT, IP_CLOCK_SLICE, 5,
605 {OSC_24M_CLK, VIDEO_PLL2_CLK, SYSTEM_PLL1_800M_CLK,
606 SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK,
607 VIDEO_PLL_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK}
608 },
609 {PCIE_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 6,
610 {OSC_24M_CLK, SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
611 SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
612 SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL3_CLK}
613 },
614 {PCIE_PHY_CLK_ROOT, IP_CLOCK_SLICE, 7,
615 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_500M_CLK,
616 EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
617 SYSTEM_PLL1_400M_CLK}
618 },
619 {PCIE_AUX_CLK_ROOT, IP_CLOCK_SLICE, 8,
620 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK,
621 SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
622 SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK}
623 },
624 {DC_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 9,
625 {OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
626 AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
627 SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
628 },
629 {LCDIF_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 10,
630 {OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
631 AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
632 SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
633 },
634 {SAI1_CLK_ROOT, IP_CLOCK_SLICE, 11,
635 {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
636 VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
637 OSC_HDMI_CLK, EXT_CLK_1, EXT_CLK_2}
638 },
639 {SAI2_CLK_ROOT, IP_CLOCK_SLICE, 12,
640 {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
641 VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
642 OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
643 },
644 {SAI3_CLK_ROOT, IP_CLOCK_SLICE, 13,
645 {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
646 VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
647 OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
648 },
649 {SAI4_CLK_ROOT, IP_CLOCK_SLICE, 14,
650 {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
651 VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
652 OSC_HDMI_CLK, EXT_CLK_1, EXT_CLK_2}
653 },
654 {SAI5_CLK_ROOT, IP_CLOCK_SLICE, 15,
655 {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
656 VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
657 OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
658 },
659 {SAI6_CLK_ROOT, IP_CLOCK_SLICE, 16,
660 {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
661 VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
662 OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
663 },
664 {SPDIF1_CLK_ROOT, IP_CLOCK_SLICE, 17,
665 {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
666 VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
667 OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
668 },
669 {SPDIF2_CLK_ROOT, IP_CLOCK_SLICE, 18,
670 {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
671 VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
672 OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
673 },
Marek Vasut363725d2020-04-24 21:37:26 +0200674 {ENET_REF_CLK_ROOT, IP_CLOCK_SLICE, 19,
675 {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK,
676 SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
677 AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4}
678 },
679 {ENET_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 20,
680 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
681 EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
682 VIDEO_PLL_CLK}
683 },
684 {ENET_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 21,
685 {OSC_24M_CLK, SYSTEM_PLL2_50M_CLK, SYSTEM_PLL2_125M_CLK,
686 SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_500M_CLK,
687 AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
688 },
Peng Fan3545c8a2020-04-22 10:55:56 +0800689 {NAND_CLK_ROOT, IP_CLOCK_SLICE, 22,
690 {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, AUDIO_PLL1_CLK,
691 SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK,
692 SYSTEM_PLL2_250M_CLK, VIDEO_PLL_CLK}
693 },
694 {QSPI_CLK_ROOT, IP_CLOCK_SLICE, 23,
695 {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_333M_CLK,
696 SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
697 SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
698 },
699 {USDHC1_CLK_ROOT, IP_CLOCK_SLICE, 24,
700 {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
701 SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
702 SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
703 },
704 {USDHC2_CLK_ROOT, IP_CLOCK_SLICE, 25,
705 {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
706 SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
707 SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
708 },
709 {I2C1_CLK_ROOT, IP_CLOCK_SLICE, 26,
710 {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
711 SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
712 AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
713 },
714 {I2C2_CLK_ROOT, IP_CLOCK_SLICE, 27,
715 {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
716 SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
717 AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
718 },
719 {I2C3_CLK_ROOT, IP_CLOCK_SLICE, 28,
720 {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
721 SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
722 AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
723 },
724 {I2C4_CLK_ROOT, IP_CLOCK_SLICE, 29,
725 {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
726 SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
727 AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
728 },
Peng Fan99878462019-08-27 06:25:51 +0000729 {UART1_CLK_ROOT, IP_CLOCK_SLICE, 30,
730 {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
731 SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
732 EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
733 },
734 {UART2_CLK_ROOT, IP_CLOCK_SLICE, 31,
735 {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
736 SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
737 EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
738 },
739 {UART3_CLK_ROOT, IP_CLOCK_SLICE, 32,
740 {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
741 SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
742 EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
743 },
744 {UART4_CLK_ROOT, IP_CLOCK_SLICE, 33,
745 {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
746 SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
747 EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
748 },
Peng Fan3545c8a2020-04-22 10:55:56 +0800749 {USB_CORE_REF_CLK_ROOT, IP_CLOCK_SLICE, 34,
750 {OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
751 SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
752 EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
753 },
754 {USB_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 35,
755 {OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
756 SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
757 EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
758 },
Peng Fan99878462019-08-27 06:25:51 +0000759 {GIC_CLK_ROOT, IP_CLOCK_SLICE, 36,
760 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
761 SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_800M_CLK,
762 EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
763 },
Peng Fan3545c8a2020-04-22 10:55:56 +0800764 {ECSPI1_CLK_ROOT, IP_CLOCK_SLICE, 37,
765 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
766 SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
767 SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
768 },
769 {ECSPI2_CLK_ROOT, IP_CLOCK_SLICE, 38,
770 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
771 SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
772 SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
773 },
774 {PWM1_CLK_ROOT, IP_CLOCK_SLICE, 39,
775 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
776 SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
777 SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
778 },
779 {PWM2_CLK_ROOT, IP_CLOCK_SLICE, 40,
780 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
781 SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
782 SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
783 },
784 {PWM3_CLK_ROOT, IP_CLOCK_SLICE, 41,
785 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
786 SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
787 SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
788 },
789 {PWM4_CLK_ROOT, IP_CLOCK_SLICE, 42,
790 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
791 SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
792 SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
793 },
794 {GPT1_CLK_ROOT, IP_CLOCK_SLICE, 43,
795 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
796 SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
797 SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
798 },
799 {GPT2_CLK_ROOT, IP_CLOCK_SLICE, 44,
800 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
801 SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
802 SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
803 },
804 {GPT3_CLK_ROOT, IP_CLOCK_SLICE, 45,
805 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
806 SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
807 SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
808 },
809 {GPT4_CLK_ROOT, IP_CLOCK_SLICE, 46,
810 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
811 SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
812 SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
813 },
814 {GPT5_CLK_ROOT, IP_CLOCK_SLICE, 47,
815 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
816 SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
817 SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
818 },
819 {GPT6_CLK_ROOT, IP_CLOCK_SLICE, 48,
820 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
821 SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
822 SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
823 },
824 {TRACE_CLK_ROOT, IP_CLOCK_SLICE, 49,
825 {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
826 VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
827 SYSTEM_PLL3_CLK, EXT_CLK_1, EXT_CLK_3}
828 },
Peng Fan99878462019-08-27 06:25:51 +0000829 {WDOG_CLK_ROOT, IP_CLOCK_SLICE, 50,
830 {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
831 VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
832 SYSTEM_PLL3_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_166M_CLK}
833 },
Peng Fan3545c8a2020-04-22 10:55:56 +0800834 {WRCLK_CLK_ROOT, IP_CLOCK_SLICE, 51,
835 {OSC_24M_CLK, SYSTEM_PLL1_40M_CLK, VPU_PLL_CLK,
836 SYSTEM_PLL3_CLK, SYSTEM_PLL2_200M_CLK,
837 SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_100M_CLK}
838 },
839 {IPP_DO_CLKO1, IP_CLOCK_SLICE, 52,
840 {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, OSC_HDMI_CLK,
841 SYSTEM_PLL1_200M_CLK, AUDIO_PLL2_CLK,
842 SYSTEM_PLL2_500M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_80M_CLK}
843 },
844 {IPP_DO_CLKO2, IP_CLOCK_SLICE, 53,
845 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_400M_CLK,
846 SYSTEM_PLL2_166M_CLK, SYSTEM_PLL3_CLK,
847 AUDIO_PLL1_CLK, VIDEO_PLL_CLK, OSC_32K_CLK}
848 },
849 {MIPI_DSI_CORE_CLK_ROOT, IP_CLOCK_SLICE, 54,
850 {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
851 SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
852 SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
853 },
854 {MIPI_DSI_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 55,
855 {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK,
856 SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
857 EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
858 },
859 {MIPI_DSI_DBI_CLK_ROOT, IP_CLOCK_SLICE, 56,
860 {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_100M_CLK,
861 SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
862 SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
863 },
864 {USDHC3_CLK_ROOT, IP_CLOCK_SLICE, 57,
865 {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
866 SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
867 SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
868 },
869 {MIPI_CSI1_CORE_CLK_ROOT, IP_CLOCK_SLICE, 58,
870 {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
871 SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
872 SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
873 },
874 {MIPI_CSI1_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 59,
875 {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK,
876 SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
877 EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
878 },
879 {MIPI_CSI1_ESC_CLK_ROOT, IP_CLOCK_SLICE, 60,
880 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
881 SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
882 SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
883 },
884 {MIPI_CSI2_CORE_CLK_ROOT, IP_CLOCK_SLICE, 61,
885 {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
886 SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
887 SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
888 },
889 {MIPI_CSI2_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 62,
890 {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK,
891 SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
892 EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
893 },
894 {MIPI_CSI2_ESC_CLK_ROOT, IP_CLOCK_SLICE, 63,
895 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
896 SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
897 SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
898 },
899 {PCIE2_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 64,
900 {OSC_24M_CLK, SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
901 SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
902 SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL3_CLK}
903 },
904 {PCIE2_PHY_CLK_ROOT, IP_CLOCK_SLICE, 65,
905 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_500M_CLK,
906 EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
907 EXT_CLK_4, SYSTEM_PLL1_400M_CLK}
908 },
909 {PCIE2_AUX_CLK_ROOT, IP_CLOCK_SLICE, 66,
910 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK,
911 SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK,
912 SYSTEM_PLL1_80M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK}
913 },
914 {ECSPI3_CLK_ROOT, IP_CLOCK_SLICE, 67,
915 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
916 SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
917 SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
918 },
919 {PDM_CLK_ROOT, IP_CLOCK_SLICE, 68,
920 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
921 SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
922 SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK},
923 },
924 {VPU_H1_CLK_ROOT, IP_CLOCK_SLICE, 69,
925 {OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
926 SYSTEM_PLL2_1000M_CLK, AUDIO_PLL2_CLK,
927 SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
928 },
Peng Fan99878462019-08-27 06:25:51 +0000929 {DRAM_SEL_CFG, DRAM_SEL_CLOCK_SLICE, 0,
930 {DRAM_PLL1_CLK}
931 },
Peng Fan3545c8a2020-04-22 10:55:56 +0800932 {CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0,
933 {ARM_A53_ALT_CLK, ARM_PLL_CLK}
934 },
Peng Fan99878462019-08-27 06:25:51 +0000935};
Peng Fan3545c8a2020-04-22 10:55:56 +0800936#elif defined(CONFIG_IMX8MN)
937static struct clk_root_map root_array[] = {
938 {ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0,
939 {OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
940 SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
941 SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK}
942 },
943 {ARM_M7_CLK_ROOT, CORE_CLOCK_SLICE, 1,
944 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_250M_CLK,
945 VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
946 AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
947 },
948 {GPU_CORE_CLK_ROOT, CORE_CLOCK_SLICE, 3,
949 {OSC_24M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
950 SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
951 AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
952 },
953 {GPU_SHADER_CLK_ROOT, CORE_CLOCK_SLICE, 4,
954 {OSC_24M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
955 SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
956 AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
957 },
958 {MAIN_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 0,
959 {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_800M_CLK,
960 SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_1000M_CLK,
961 AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_100M_CLK}
962 },
963 {ENET_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 1,
964 {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
965 SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
966 AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
967 },
968 {NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2,
969 {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
970 SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK,
971 SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL1_CLK}
972 },
973 {DISPLAY_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 4,
974 {OSC_24M_CLK, SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
975 SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, AUDIO_PLL2_CLK,
976 EXT_CLK_1, EXT_CLK_4}
977 },
978 {DISPLAY_APB_CLK_ROOT, BUS_CLOCK_SLICE, 5,
979 {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
980 SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, AUDIO_PLL2_CLK,
981 EXT_CLK_1, EXT_CLK_3}
982 },
983 {USB_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 7,
984 {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
985 SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
986 EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
987 },
988 {GPU_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 8,
989 {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
990 SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
991 AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
992 },
993 {GPU_AHB_CLK_ROOT, BUS_CLOCK_SLICE, 9,
994 {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
995 SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
996 AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
997 },
998 {NOC_CLK_ROOT, BUS_CLOCK_SLICE, 10,
999 {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK,
1000 SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK,
1001 AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
1002 },
1003 {AHB_CLK_ROOT, AHB_CLOCK_SLICE, 0,
1004 {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_800M_CLK,
1005 SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_125M_CLK,
1006 SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
1007 },
1008 {AUDIO_AHB_CLK_ROOT, AHB_CLOCK_SLICE, 1,
1009 {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
1010 SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_166M_CLK,
1011 SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
1012 },
1013 {DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0,
1014 {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_100M_CLK,
1015 SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_1000M_CLK,
1016 SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL1_266M_CLK}
1017 },
1018 {DRAM_APB_CLK_ROOT, IP_CLOCK_SLICE, 1,
1019 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
1020 SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
1021 SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
1022 },
1023 {DISPLAY_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 10,
1024 {OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
1025 AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
1026 SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
1027 },
1028 {SAI2_CLK_ROOT, IP_CLOCK_SLICE, 12,
1029 {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
1030 VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
1031 OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
1032 },
1033 {SAI3_CLK_ROOT, IP_CLOCK_SLICE, 13,
1034 {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
1035 VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
1036 OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
1037 },
1038 {SAI5_CLK_ROOT, IP_CLOCK_SLICE, 15,
1039 {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
1040 VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
1041 OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
1042 },
1043 {SAI6_CLK_ROOT, IP_CLOCK_SLICE, 16,
1044 {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
1045 VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
1046 OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
1047 },
1048 {SPDIF1_CLK_ROOT, IP_CLOCK_SLICE, 17,
1049 {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
1050 VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
1051 OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
1052 },
1053 {ENET_REF_CLK_ROOT, IP_CLOCK_SLICE, 19,
1054 {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK,
1055 SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
1056 AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4}
1057 },
1058 {ENET_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 20,
1059 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
1060 EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
1061 VIDEO_PLL_CLK}
1062 },
1063 {ENET_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 21,
1064 {OSC_24M_CLK, SYSTEM_PLL2_50M_CLK, SYSTEM_PLL2_125M_CLK,
1065 SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_500M_CLK,
1066 AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
1067 },
1068 {NAND_CLK_ROOT, IP_CLOCK_SLICE, 22,
1069 {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, AUDIO_PLL1_CLK,
1070 SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK,
1071 SYSTEM_PLL2_250M_CLK, VIDEO_PLL_CLK}
1072 },
1073 {QSPI_CLK_ROOT, IP_CLOCK_SLICE, 23,
1074 {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_333M_CLK,
1075 SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
1076 SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
1077 },
1078 {USDHC1_CLK_ROOT, IP_CLOCK_SLICE, 24,
1079 {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
1080 SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
1081 SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
1082 },
1083 {USDHC2_CLK_ROOT, IP_CLOCK_SLICE, 25,
1084 {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
1085 SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
1086 SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
1087 },
1088 {I2C1_CLK_ROOT, IP_CLOCK_SLICE, 26,
1089 {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
1090 SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
1091 AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
1092 },
1093 {I2C2_CLK_ROOT, IP_CLOCK_SLICE, 27,
1094 {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
1095 SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
1096 AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
1097 },
1098 {I2C3_CLK_ROOT, IP_CLOCK_SLICE, 28,
1099 {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
1100 SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
1101 AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
1102 },
1103 {I2C4_CLK_ROOT, IP_CLOCK_SLICE, 29,
1104 {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
1105 SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
1106 AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
1107 },
1108 {UART1_CLK_ROOT, IP_CLOCK_SLICE, 30,
1109 {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
1110 SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
1111 EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
1112 },
1113 {UART2_CLK_ROOT, IP_CLOCK_SLICE, 31,
1114 {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
1115 SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
1116 EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
1117 },
1118 {UART3_CLK_ROOT, IP_CLOCK_SLICE, 32,
1119 {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
1120 SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
1121 EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
1122 },
1123 {UART4_CLK_ROOT, IP_CLOCK_SLICE, 33,
1124 {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
1125 SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
1126 EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
1127 },
1128 {USB_CORE_REF_CLK_ROOT, IP_CLOCK_SLICE, 34,
1129 {OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
1130 SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
1131 EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
1132 },
1133 {USB_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 35,
1134 {OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
1135 SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
1136 EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
1137 },
1138 {GIC_CLK_ROOT, IP_CLOCK_SLICE, 36,
1139 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
1140 SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_800M_CLK,
1141 EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
1142 },
1143 {ECSPI1_CLK_ROOT, IP_CLOCK_SLICE, 37,
1144 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
1145 SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
1146 SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
1147 },
1148 {ECSPI2_CLK_ROOT, IP_CLOCK_SLICE, 38,
1149 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
1150 SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
1151 SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
1152 },
1153 {PWM1_CLK_ROOT, IP_CLOCK_SLICE, 39,
1154 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
1155 SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
1156 SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
1157 },
1158 {PWM2_CLK_ROOT, IP_CLOCK_SLICE, 40,
1159 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
1160 SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
1161 SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
1162 },
1163 {PWM3_CLK_ROOT, IP_CLOCK_SLICE, 41,
1164 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
1165 SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
1166 SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
1167 },
1168 {PWM4_CLK_ROOT, IP_CLOCK_SLICE, 42,
1169 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
1170 SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
1171 SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
1172 },
1173 {GPT1_CLK_ROOT, IP_CLOCK_SLICE, 43,
1174 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
1175 SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
1176 SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
1177 },
1178 {GPT2_CLK_ROOT, IP_CLOCK_SLICE, 44,
1179 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
1180 SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
1181 SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
1182 },
1183 {GPT3_CLK_ROOT, IP_CLOCK_SLICE, 45,
1184 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
1185 SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
1186 SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
1187 },
1188 {GPT4_CLK_ROOT, IP_CLOCK_SLICE, 46,
1189 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
1190 SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
1191 SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
1192 },
1193 {GPT5_CLK_ROOT, IP_CLOCK_SLICE, 47,
1194 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
1195 SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
1196 SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
1197 },
1198 {GPT6_CLK_ROOT, IP_CLOCK_SLICE, 48,
1199 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
1200 SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
1201 SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
1202 },
1203 {TRACE_CLK_ROOT, IP_CLOCK_SLICE, 49,
1204 {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
1205 VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
1206 SYSTEM_PLL3_CLK, EXT_CLK_1, EXT_CLK_3}
1207 },
1208 {WDOG_CLK_ROOT, IP_CLOCK_SLICE, 50,
1209 {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
1210 VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
1211 SYSTEM_PLL3_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_166M_CLK}
1212 },
1213 {WRCLK_CLK_ROOT, IP_CLOCK_SLICE, 51,
1214 {OSC_24M_CLK, SYSTEM_PLL1_40M_CLK, VPU_PLL_CLK,
1215 SYSTEM_PLL3_CLK, SYSTEM_PLL2_200M_CLK,
1216 SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_100M_CLK}
1217 },
1218 {IPP_DO_CLKO1, IP_CLOCK_SLICE, 52,
1219 {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, OSC_HDMI_CLK,
1220 SYSTEM_PLL1_200M_CLK, AUDIO_PLL2_CLK,
1221 SYSTEM_PLL2_500M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_80M_CLK}
1222 },
1223 {IPP_DO_CLKO2, IP_CLOCK_SLICE, 53,
1224 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_400M_CLK,
1225 SYSTEM_PLL2_166M_CLK, SYSTEM_PLL3_CLK,
1226 AUDIO_PLL1_CLK, VIDEO_PLL_CLK, OSC_32K_CLK}
1227 },
1228 {MIPI_DSI_CORE_CLK_ROOT, IP_CLOCK_SLICE, 54,
1229 {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
1230 SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
1231 SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
1232 },
1233 {DISPLAY_DSI_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 55,
1234 {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK,
1235 SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
1236 EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
1237 },
1238 {MIPI_DSI_DBI_CLK_ROOT, IP_CLOCK_SLICE, 56,
1239 {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_100M_CLK,
1240 SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
1241 SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
1242 },
1243 {USDHC3_CLK_ROOT, IP_CLOCK_SLICE, 57,
1244 {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
1245 SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
1246 SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
1247 },
1248 {DISPLAY_CAMERA_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 58,
1249 {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
1250 SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
1251 SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
1252 },
1253 {MIPI_CSI1_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 59,
1254 {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK,
1255 SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
1256 EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
1257 },
1258 {MIPI_CSI2_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 62,
1259 {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK,
1260 SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
1261 EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
1262 },
1263 {MIPI_CSI2_ESC_CLK_ROOT, IP_CLOCK_SLICE, 63,
1264 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
1265 SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
1266 SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
1267 },
1268 {ECSPI3_CLK_ROOT, IP_CLOCK_SLICE, 67,
1269 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
1270 SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
1271 SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
1272 },
1273 {PDM_CLK_ROOT, IP_CLOCK_SLICE, 68,
1274 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
1275 SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
1276 SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK},
1277 },
1278 {SAI7_CLK_ROOT, IP_CLOCK_SLICE, 70,
1279 {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
1280 VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
1281 OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
1282 },
1283 {DRAM_SEL_CFG, DRAM_SEL_CLOCK_SLICE, 0,
1284 {DRAM_PLL1_CLK}
1285 },
1286 {CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0,
1287 {ARM_A53_ALT_CLK, ARM_PLL_CLK}
1288 },
1289};
Peng Fanb7ca2932019-12-27 11:39:15 +08001290#elif defined(CONFIG_IMX8MP)
1291static struct clk_root_map root_array[] = {
1292 {ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0,
1293 {OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
1294 SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
1295 SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK}
1296 },
1297 {ARM_M7_CLK_ROOT, CORE_CLOCK_SLICE, 1,
1298 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_250M_CLK,
1299 VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
1300 AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
1301 },
1302 {ML_CLK_ROOT, CORE_CLOCK_SLICE, 2,
1303 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_250M_CLK,
1304 VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
1305 AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
1306 },
1307 {HSIO_AXI_CLK_ROOT, CORE_CLOCK_SLICE, 7,
1308 {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
1309 SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK, EXT_CLK_2,
1310 EXT_CLK_4, AUDIO_PLL2_CLK}
1311 },
1312 {MAIN_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 0,
1313 {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_800M_CLK,
1314 SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_1000M_CLK, AUDIO_PLL1_CLK,
1315 VIDEO_PLL_CLK, SYSTEM_PLL1_100M_CLK}
1316 },
1317 {ENET_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 1,
1318 {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
1319 SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK, AUDIO_PLL1_CLK,
1320 VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
1321 },
1322 {NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2,
1323 {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
1324 SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK,
1325 SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL1_CLK}
1326 },
Peng Fan3545c8a2020-04-22 10:55:56 +08001327 {MEDIA_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 4,
1328 {OSC_24M_CLK, SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
1329 SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK,
1330 AUDIO_PLL2_CLK, EXT_CLK_1, SYSTEM_PLL2_500M_CLK}
1331 },
1332 {MEDIA_APB_CLK_ROOT, BUS_CLOCK_SLICE, 5,
1333 {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
1334 SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK,
1335 AUDIO_PLL2_CLK, EXT_CLK_1, SYSTEM_PLL1_133M_CLK}
1336 },
1337 {HDMI_APB_CLK_ROOT, BUS_CLOCK_SLICE, 6,
1338 {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
1339 SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK,
1340 AUDIO_PLL2_CLK, EXT_CLK_1, SYSTEM_PLL1_133M_CLK}
1341 },
1342 {HDMI_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 7,
1343 {OSC_24M_CLK, SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
1344 SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK,
1345 AUDIO_PLL2_CLK, EXT_CLK_1, SYSTEM_PLL2_500M_CLK}
1346 },
Peng Fanb7ca2932019-12-27 11:39:15 +08001347 {NOC_CLK_ROOT, BUS_CLOCK_SLICE, 10,
1348 {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK,
1349 SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK,
1350 AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
1351 },
1352 {NOC_IO_CLK_ROOT, BUS_CLOCK_SLICE, 11,
1353 {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK,
1354 SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK,
1355 AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
1356 },
1357 {ML_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 12,
1358 {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
1359 SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
1360 AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
1361 },
1362 {ML_AHB_CLK_ROOT, BUS_CLOCK_SLICE, 13,
1363 {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
1364 SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
1365 AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
1366 },
1367 {AHB_CLK_ROOT, AHB_CLOCK_SLICE, 0,
1368 {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_800M_CLK,
1369 SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_125M_CLK,
1370 SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
1371 },
Peng Fan3545c8a2020-04-22 10:55:56 +08001372 {MEDIA_DISP2_CLK_ROOT, AHB_CLOCK_SLICE, 3,
1373 {OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
1374 AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
1375 SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
1376 },
Peng Fanb7ca2932019-12-27 11:39:15 +08001377 {DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0,
1378 {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_100M_CLK,
1379 SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_1000M_CLK,
1380 SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL1_266M_CLK}
1381 },
1382 {DRAM_APB_CLK_ROOT, IP_CLOCK_SLICE, 1,
1383 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
1384 SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
1385 SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
1386 },
Peng Fanb7ca2932019-12-27 11:39:15 +08001387 {I2C5_CLK_ROOT, IP_CLOCK_SLICE, 9,
1388 {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
1389 SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
1390 SYSTEM_PLL1_133M_CLK}
1391 },
1392 {I2C6_CLK_ROOT, IP_CLOCK_SLICE, 10,
1393 {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
1394 SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
1395 SYSTEM_PLL1_133M_CLK}
1396 },
1397 {ENET_QOS_CLK_ROOT, IP_CLOCK_SLICE, 17,
1398 {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK,
1399 SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
1400 AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4}
1401 },
1402 {ENET_QOS_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 18,
1403 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1,
1404 EXT_CLK_2, EXT_CLK_3, EXT_CLK_4, VIDEO_PLL_CLK}
1405 },
1406 {ENET_REF_CLK_ROOT, IP_CLOCK_SLICE, 19,
1407 {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK,
1408 SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
1409 AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4}
1410 },
1411 {ENET_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 20,
1412 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1,
1413 EXT_CLK_2, EXT_CLK_3, EXT_CLK_4, VIDEO_PLL_CLK}
1414 },
1415 {ENET_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 21,
1416 {OSC_24M_CLK, SYSTEM_PLL2_50M_CLK, SYSTEM_PLL2_125M_CLK,
1417 SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_500M_CLK, AUDIO_PLL1_CLK,
1418 VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
1419 },
1420 {NAND_CLK_ROOT, IP_CLOCK_SLICE, 22,
1421 {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, AUDIO_PLL1_CLK,
1422 SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK,
1423 SYSTEM_PLL2_250M_CLK, VIDEO_PLL_CLK}
1424 },
1425 {QSPI_CLK_ROOT, IP_CLOCK_SLICE, 23,
1426 {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_333M_CLK,
1427 SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
1428 SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
1429 },
1430 {USDHC1_CLK_ROOT, IP_CLOCK_SLICE, 24,
1431 {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
1432 SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
1433 SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
1434 },
1435 {USDHC2_CLK_ROOT, IP_CLOCK_SLICE, 25,
1436 {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
1437 SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
1438 SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
1439 },
1440 {I2C1_CLK_ROOT, IP_CLOCK_SLICE, 26,
1441 {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
1442 SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
1443 AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
1444 },
1445 {I2C2_CLK_ROOT, IP_CLOCK_SLICE, 27,
1446 {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
1447 SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
1448 AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
1449 },
1450 {I2C3_CLK_ROOT, IP_CLOCK_SLICE, 28,
1451 {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
1452 SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
1453 AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
1454 },
1455 {I2C4_CLK_ROOT, IP_CLOCK_SLICE, 29,
1456 {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
1457 SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
1458 AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
1459 },
1460 {UART1_CLK_ROOT, IP_CLOCK_SLICE, 30,
1461 {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
1462 SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
1463 EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
1464 },
1465 {UART2_CLK_ROOT, IP_CLOCK_SLICE, 31,
1466 {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
1467 SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
1468 EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
1469 },
1470 {UART3_CLK_ROOT, IP_CLOCK_SLICE, 32,
1471 {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
1472 SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
1473 EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
1474 },
1475 {UART4_CLK_ROOT, IP_CLOCK_SLICE, 33,
1476 {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
1477 SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
1478 EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
1479 },
1480 {USB_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 35,
1481 {OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
1482 SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
1483 EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
1484 },
1485 {GIC_CLK_ROOT, IP_CLOCK_SLICE, 36,
1486 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
1487 SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_800M_CLK,
1488 EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
1489 },
1490 {ECSPI1_CLK_ROOT, IP_CLOCK_SLICE, 37,
1491 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
1492 SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
1493 SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
1494 },
1495 {ECSPI2_CLK_ROOT, IP_CLOCK_SLICE, 38,
1496 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
1497 SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
1498 SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
1499 },
1500 {PWM1_CLK_ROOT, IP_CLOCK_SLICE, 39,
1501 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
1502 SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
1503 SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
1504 },
1505 {PWM2_CLK_ROOT, IP_CLOCK_SLICE, 40,
1506 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
1507 SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
1508 SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
1509 },
1510 {PWM3_CLK_ROOT, IP_CLOCK_SLICE, 41,
1511 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
1512 SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
1513 SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
1514 },
1515 {PWM4_CLK_ROOT, IP_CLOCK_SLICE, 42,
1516 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
1517 SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
1518 SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
1519 },
1520 {GPT1_CLK_ROOT, IP_CLOCK_SLICE, 43,
1521 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
1522 SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
1523 SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
1524 },
1525 {GPT2_CLK_ROOT, IP_CLOCK_SLICE, 44,
1526 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
1527 SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
1528 SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
1529 },
1530 {GPT3_CLK_ROOT, IP_CLOCK_SLICE, 45,
1531 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
1532 SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
1533 SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
1534 },
1535 {GPT4_CLK_ROOT, IP_CLOCK_SLICE, 46,
1536 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
1537 SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
1538 SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
1539 },
1540 {GPT5_CLK_ROOT, IP_CLOCK_SLICE, 47,
1541 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
1542 SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
1543 SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
1544 },
1545 {GPT6_CLK_ROOT, IP_CLOCK_SLICE, 48,
1546 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
1547 SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
1548 SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
1549 },
1550 {TRACE_CLK_ROOT, IP_CLOCK_SLICE, 49,
1551 {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
1552 VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
1553 SYSTEM_PLL3_CLK, EXT_CLK_1, EXT_CLK_3}
1554 },
1555 {WDOG_CLK_ROOT, IP_CLOCK_SLICE, 50,
1556 {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
1557 VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
1558 SYSTEM_PLL3_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_166M_CLK}
1559 },
1560 {WRCLK_CLK_ROOT, IP_CLOCK_SLICE, 51,
1561 {OSC_24M_CLK, SYSTEM_PLL1_40M_CLK, VPU_PLL_CLK,
1562 SYSTEM_PLL3_CLK, SYSTEM_PLL2_200M_CLK,
1563 SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_100M_CLK}
1564 },
Peng Fan3545c8a2020-04-22 10:55:56 +08001565 {HDMI_REF_266M_CLK_ROOT, IP_CLOCK_SLICE, 56,
1566 {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL3_CLK,
1567 SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_266M_CLK,
1568 SYSTEM_PLL2_200M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
1569 },
Peng Fanb7ca2932019-12-27 11:39:15 +08001570 {USDHC3_CLK_ROOT, IP_CLOCK_SLICE, 57,
1571 {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
1572 SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
1573 SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
1574 },
Peng Fan3545c8a2020-04-22 10:55:56 +08001575 {MEDIA_MIPI_PHY1_REF_CLK_ROOT, IP_CLOCK_SLICE, 59,
1576 {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK,
1577 SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
1578 EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
1579 },
1580 {MEDIA_DISP1_PIX_CLK_ROOT, IP_CLOCK_SLICE, 60,
1581 {OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
1582 AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
1583 SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
1584 },
1585 {MEDIA_LDB_CLK_ROOT, IP_CLOCK_SLICE, 62,
1586 {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK,
1587 SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
1588 EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
1589 },
1590 {MEMREPAIR_CLK_ROOT, IP_CLOCK_SLICE, 63,
1591 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
1592 SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
1593 SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
1594 },
Peng Fanb7ca2932019-12-27 11:39:15 +08001595 {ECSPI3_CLK_ROOT, IP_CLOCK_SLICE, 67,
1596 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
1597 SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
1598 SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
1599 },
1600 {DRAM_SEL_CFG, DRAM_SEL_CLOCK_SLICE, 0,
1601 {DRAM_PLL1_CLK}
1602 },
1603 {CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0,
Peng Fan3545c8a2020-04-22 10:55:56 +08001604 {ARM_A53_ALT_CLK, ARM_PLL_CLK}
Peng Fanb7ca2932019-12-27 11:39:15 +08001605 },
1606};
Peng Fan99878462019-08-27 06:25:51 +00001607#endif
Peng Fan88057bc2018-01-10 13:20:22 +08001608
1609static int select(enum clk_root_index clock_id)
1610{
1611 int i, size;
1612 struct clk_root_map *p = root_array;
1613
1614 size = ARRAY_SIZE(root_array);
1615
1616 for (i = 0; i < size; i++, p++) {
1617 if (clock_id == p->entry)
1618 return i;
1619 }
1620
1621 return -EINVAL;
1622}
1623
1624static void __iomem *get_clk_root_target(enum clk_slice_type slice_type,
1625 u32 slice_index)
1626{
1627 void __iomem *clk_root_target;
1628
1629 switch (slice_type) {
1630 case CORE_CLOCK_SLICE:
1631 clk_root_target =
1632 (void __iomem *)&ccm_reg->core_root[slice_index];
1633 break;
1634 case BUS_CLOCK_SLICE:
1635 clk_root_target =
1636 (void __iomem *)&ccm_reg->bus_root[slice_index];
1637 break;
1638 case IP_CLOCK_SLICE:
1639 clk_root_target =
1640 (void __iomem *)&ccm_reg->ip_root[slice_index];
1641 break;
1642 case AHB_CLOCK_SLICE:
1643 clk_root_target =
1644 (void __iomem *)&ccm_reg->ahb_ipg_root[slice_index * 2];
1645 break;
1646 case IPG_CLOCK_SLICE:
1647 clk_root_target =
1648 (void __iomem *)&ccm_reg->ahb_ipg_root[slice_index * 2 + 1];
1649 break;
1650 case CORE_SEL_CLOCK_SLICE:
1651 clk_root_target = (void __iomem *)&ccm_reg->core_sel;
1652 break;
1653 case DRAM_SEL_CLOCK_SLICE:
1654 clk_root_target = (void __iomem *)&ccm_reg->dram_sel;
1655 break;
1656 default:
1657 return NULL;
1658 }
1659
1660 return clk_root_target;
1661}
1662
1663int clock_get_target_val(enum clk_root_index clock_id, u32 *val)
1664{
1665 int root_entry;
1666 struct clk_root_map *p;
1667 void __iomem *clk_root_target;
1668
1669 if (clock_id >= CLK_ROOT_MAX)
1670 return -EINVAL;
1671
1672 root_entry = select(clock_id);
1673 if (root_entry < 0)
1674 return -EINVAL;
1675
1676 p = &root_array[root_entry];
1677 clk_root_target = get_clk_root_target(p->slice_type, p->slice_index);
1678 if (!clk_root_target)
1679 return -EINVAL;
1680
1681 *val = readl(clk_root_target);
1682
1683 return 0;
1684}
1685
1686int clock_set_target_val(enum clk_root_index clock_id, u32 val)
1687{
1688 int root_entry;
1689 struct clk_root_map *p;
1690 void __iomem *clk_root_target;
1691
1692 if (clock_id >= CLK_ROOT_MAX)
1693 return -EINVAL;
1694
1695 root_entry = select(clock_id);
1696 if (root_entry < 0)
1697 return -EINVAL;
1698
1699 p = &root_array[root_entry];
1700 clk_root_target = get_clk_root_target(p->slice_type, p->slice_index);
1701 if (!clk_root_target)
1702 return -EINVAL;
1703
1704 writel(val, clk_root_target);
1705
1706 return 0;
1707}
1708
1709int clock_root_enabled(enum clk_root_index clock_id)
1710{
1711 void __iomem *clk_root_target;
1712 u32 slice_index, slice_type;
1713 u32 val;
1714 int root_entry;
1715
1716 if (clock_id >= CLK_ROOT_MAX)
1717 return -EINVAL;
1718
1719 root_entry = select(clock_id);
1720 if (root_entry < 0)
1721 return -EINVAL;
1722
1723 slice_type = root_array[root_entry].slice_type;
1724 slice_index = root_array[root_entry].slice_index;
1725
1726 if ((slice_type == IPG_CLOCK_SLICE) ||
1727 (slice_type == DRAM_SEL_CLOCK_SLICE) ||
1728 (slice_type == CORE_SEL_CLOCK_SLICE)) {
1729 /*
1730 * Not supported, from CCM doc
1731 * TODO
1732 */
1733 return 0;
1734 }
1735
1736 clk_root_target = get_clk_root_target(slice_type, slice_index);
1737 if (!clk_root_target)
1738 return -EINVAL;
1739
1740 val = readl(clk_root_target);
1741
1742 return (val & CLK_ROOT_ON) ? 1 : 0;
1743}
1744
1745/* CCGR CLK gate operation */
1746int clock_enable(enum clk_ccgr_index index, bool enable)
1747{
1748 void __iomem *ccgr;
1749
1750 if (index >= CCGR_MAX)
1751 return -EINVAL;
1752
1753 if (enable)
1754 ccgr = (void __iomem *)&ccm_reg->ccgr_array[index].ccgr_set;
1755 else
1756 ccgr = (void __iomem *)&ccm_reg->ccgr_array[index].ccgr_clr;
1757
1758 writel(CCGR_CLK_ON_MASK, ccgr);
1759
1760 return 0;
1761}
1762
1763int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div)
1764{
1765 u32 val;
1766 int root_entry;
1767 struct clk_root_map *p;
1768 void __iomem *clk_root_target;
1769
1770 if (clock_id >= CLK_ROOT_MAX)
1771 return -EINVAL;
1772
1773 root_entry = select(clock_id);
1774 if (root_entry < 0)
1775 return -EINVAL;
1776
1777 p = &root_array[root_entry];
1778
1779 if ((p->slice_type == CORE_CLOCK_SLICE) ||
1780 (p->slice_type == IPG_CLOCK_SLICE) ||
1781 (p->slice_type == CORE_SEL_CLOCK_SLICE) ||
1782 (p->slice_type == DRAM_SEL_CLOCK_SLICE)) {
1783 *pre_div = 0;
1784 return 0;
1785 }
1786
1787 clk_root_target = get_clk_root_target(p->slice_type, p->slice_index);
1788 if (!clk_root_target)
1789 return -EINVAL;
1790
1791 val = readl(clk_root_target);
1792 val &= CLK_ROOT_PRE_DIV_MASK;
1793 val >>= CLK_ROOT_PRE_DIV_SHIFT;
1794
1795 *pre_div = val;
1796
1797 return 0;
1798}
1799
1800int clock_get_postdiv(enum clk_root_index clock_id,
1801 enum root_post_div *post_div)
1802{
1803 u32 val, mask;
1804 int root_entry;
1805 struct clk_root_map *p;
1806 void __iomem *clk_root_target;
1807
1808 if (clock_id >= CLK_ROOT_MAX)
1809 return -EINVAL;
1810
1811 root_entry = select(clock_id);
1812 if (root_entry < 0)
1813 return -EINVAL;
1814
1815 p = &root_array[root_entry];
1816
1817 if ((p->slice_type == CORE_SEL_CLOCK_SLICE) ||
1818 (p->slice_type == DRAM_SEL_CLOCK_SLICE)) {
1819 *post_div = 0;
1820 return 0;
1821 }
1822
1823 clk_root_target = get_clk_root_target(p->slice_type, p->slice_index);
1824 if (!clk_root_target)
1825 return -EINVAL;
1826
1827 if (p->slice_type == IPG_CLOCK_SLICE)
1828 mask = CLK_ROOT_IPG_POST_DIV_MASK;
1829 else if (p->slice_type == CORE_CLOCK_SLICE)
1830 mask = CLK_ROOT_CORE_POST_DIV_MASK;
1831 else
1832 mask = CLK_ROOT_POST_DIV_MASK;
1833
1834 val = readl(clk_root_target);
1835 val &= mask;
1836 val >>= CLK_ROOT_POST_DIV_SHIFT;
1837
1838 *post_div = val;
1839
1840 return 0;
1841}
1842
1843int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src)
1844{
1845 u32 val;
1846 int root_entry;
1847 struct clk_root_map *p;
1848 void __iomem *clk_root_target;
1849
1850 if (clock_id >= CLK_ROOT_MAX)
1851 return -EINVAL;
1852
1853 root_entry = select(clock_id);
1854 if (root_entry < 0)
1855 return -EINVAL;
1856
1857 p = &root_array[root_entry];
1858
1859 clk_root_target = get_clk_root_target(p->slice_type, p->slice_index);
1860 if (!clk_root_target)
1861 return -EINVAL;
1862
1863 val = readl(clk_root_target);
1864 val &= CLK_ROOT_SRC_MUX_MASK;
1865 val >>= CLK_ROOT_SRC_MUX_SHIFT;
1866
1867 *p_clock_src = p->src_mux[val];
1868
1869 return 0;
1870}