Mike Frysinger | eba7a04 | 2008-11-04 00:04:03 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Blackfin cache control code |
| 3 | * |
| 4 | * Copyright 2003-2008 Analog Devices Inc. |
| 5 | * |
| 6 | * Enter bugs at http://blackfin.uclinux.org/ |
| 7 | * |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 8 | * Licensed under the GPL-2 or later. |
| 9 | */ |
| 10 | |
| 11 | #include <asm/linkage.h> |
| 12 | #include <config.h> |
| 13 | #include <asm/blackfin.h> |
| 14 | |
| 15 | .text |
Mike Frysinger | eba7a04 | 2008-11-04 00:04:03 -0500 | [diff] [blame] | 16 | /* Since all L1 caches work the same way, we use the same method for flushing |
| 17 | * them. Only the actual flush instruction differs. We write this in asm as |
| 18 | * GCC can be hard to coax into writing nice hardware loops. |
| 19 | * |
| 20 | * Also, we assume the following register setup: |
| 21 | * R0 = start address |
| 22 | * R1 = end address |
| 23 | */ |
| 24 | .macro do_flush flushins:req optflushins optnopins label |
| 25 | |
| 26 | R2 = -L1_CACHE_BYTES; |
| 27 | |
| 28 | /* start = (start & -L1_CACHE_BYTES) */ |
| 29 | R0 = R0 & R2; |
| 30 | |
| 31 | /* end = ((end - 1) & -L1_CACHE_BYTES) + L1_CACHE_BYTES; */ |
| 32 | R1 += -1; |
| 33 | R1 = R1 & R2; |
| 34 | R1 += L1_CACHE_BYTES; |
| 35 | |
| 36 | /* count = (end - start) >> L1_CACHE_SHIFT */ |
| 37 | R2 = R1 - R0; |
| 38 | R2 >>= L1_CACHE_SHIFT; |
| 39 | P1 = R2; |
| 40 | |
| 41 | .ifnb \label |
| 42 | \label : |
| 43 | .endif |
| 44 | P0 = R0; |
| 45 | LSETUP (1f, 2f) LC1 = P1; |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 46 | 1: |
Mike Frysinger | eba7a04 | 2008-11-04 00:04:03 -0500 | [diff] [blame] | 47 | .ifnb \optflushins |
| 48 | \optflushins [P0]; |
| 49 | .endif |
| 50 | #if ANOMALY_05000443 |
| 51 | .ifb \optnopins |
| 52 | 2: |
| 53 | .endif |
| 54 | \flushins [P0++]; |
| 55 | .ifnb \optnopins |
| 56 | 2: \optnopins; |
| 57 | .endif |
| 58 | #else |
| 59 | 2: \flushins [P0++]; |
| 60 | #endif |
| 61 | |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 62 | RTS; |
Mike Frysinger | eba7a04 | 2008-11-04 00:04:03 -0500 | [diff] [blame] | 63 | .endm |
| 64 | |
| 65 | /* Invalidate all instruction cache lines assocoiated with this memory area */ |
| 66 | ENTRY(_blackfin_icache_flush_range) |
| 67 | do_flush IFLUSH, , nop |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 68 | ENDPROC(_blackfin_icache_flush_range) |
| 69 | |
Mike Frysinger | eba7a04 | 2008-11-04 00:04:03 -0500 | [diff] [blame] | 70 | /* Flush all cache lines assocoiated with this area of memory. */ |
| 71 | ENTRY(_blackfin_icache_dcache_flush_range) |
| 72 | do_flush FLUSH, IFLUSH |
| 73 | ENDPROC(_blackfin_icache_dcache_flush_range) |
Mike Frysinger | 94bae5c | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 74 | |
Mike Frysinger | eba7a04 | 2008-11-04 00:04:03 -0500 | [diff] [blame] | 75 | /* Throw away all D-cached data in specified region without any obligation to |
| 76 | * write them back. Since the Blackfin ISA does not have an "invalidate" |
| 77 | * instruction, we use flush/invalidate. Perhaps as a speed optimization we |
| 78 | * could bang on the DTEST MMRs ... |
| 79 | */ |
Mike Frysinger | 343e9f7 | 2008-10-06 03:35:44 -0400 | [diff] [blame] | 80 | ENTRY(_blackfin_dcache_flush_invalidate_range) |
Mike Frysinger | eba7a04 | 2008-11-04 00:04:03 -0500 | [diff] [blame] | 81 | do_flush FLUSHINV |
Mike Frysinger | 343e9f7 | 2008-10-06 03:35:44 -0400 | [diff] [blame] | 82 | ENDPROC(_blackfin_dcache_flush_invalidate_range) |
Mike Frysinger | eba7a04 | 2008-11-04 00:04:03 -0500 | [diff] [blame] | 83 | |
| 84 | /* Flush all data cache lines assocoiated with this memory area */ |
| 85 | ENTRY(_blackfin_dcache_flush_range) |
| 86 | do_flush FLUSH, , , .Ldfr |
| 87 | ENDPROC(_blackfin_dcache_flush_range) |