Michal Simek | 508e091 | 2023-09-27 11:53:36 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * dts file for Xilinx ZynqMP ZCU670 (67DR) |
| 4 | * |
| 5 | * (C) Copyright 2017 - 2022, Xilinx, Inc. |
| 6 | * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. |
| 7 | * |
| 8 | * Michal Simek <michal.simek@amd.com> |
| 9 | */ |
| 10 | |
| 11 | /dts-v1/; |
| 12 | |
| 13 | #include "zynqmp.dtsi" |
| 14 | #include "zynqmp-clk-ccf.dtsi" |
| 15 | #include <dt-bindings/input/input.h> |
| 16 | #include <dt-bindings/gpio/gpio.h> |
| 17 | #include <dt-bindings/pinctrl/pinctrl-zynqmp.h> |
| 18 | #include <dt-bindings/phy/phy.h> |
| 19 | |
| 20 | / { |
| 21 | model = "ZynqMP ZCU670 RevA"; |
| 22 | compatible = "xlnx,zynqmp-zcu670-revA", "xlnx,zynqmp-zcu670", |
| 23 | "xlnx,zynqmp"; |
| 24 | |
| 25 | aliases { |
| 26 | ethernet0 = &gem3; |
| 27 | i2c0 = &i2c0; |
| 28 | i2c1 = &i2c1; |
| 29 | mmc0 = &sdhci1; |
| 30 | nvmem0 = &eeprom; |
| 31 | rtc0 = &rtc; |
| 32 | serial0 = &uart0; |
| 33 | serial1 = &dcc; |
| 34 | spi0 = &qspi; |
| 35 | usb0 = &usb0; |
| 36 | }; |
| 37 | |
| 38 | chosen { |
| 39 | bootargs = "earlycon"; |
| 40 | stdout-path = "serial0:115200n8"; |
| 41 | }; |
| 42 | |
| 43 | memory@0 { |
| 44 | device_type = "memory"; |
| 45 | reg = <0 0 0 0x80000000>, <0x8 0x0 0x0 0x80000000>; |
| 46 | /* Another 4GB connected to PL */ |
| 47 | }; |
| 48 | |
| 49 | gpio-keys { |
| 50 | compatible = "gpio-keys"; |
| 51 | autorepeat; |
| 52 | sw1 { |
| 53 | label = "sw1"; |
| 54 | gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; |
| 55 | linux,code = <BTN_MISC>; |
| 56 | wakeup-source; |
| 57 | autorepeat; |
| 58 | }; |
| 59 | }; |
| 60 | |
| 61 | leds { |
| 62 | compatible = "gpio-leds"; |
| 63 | heartbeat-led { |
| 64 | label = "heartbeat"; /* DS1 */ |
| 65 | gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; |
| 66 | linux,default-trigger = "heartbeat"; |
| 67 | }; |
| 68 | }; |
| 69 | |
| 70 | ina226-vccint { |
| 71 | compatible = "iio-hwmon"; |
| 72 | io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; |
| 73 | }; |
| 74 | ina226-vccint-io-bram-ps { |
| 75 | compatible = "iio-hwmon"; |
| 76 | io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; |
| 77 | }; |
| 78 | ina226-vcc1v8 { |
| 79 | compatible = "iio-hwmon"; |
| 80 | io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; |
| 81 | }; |
| 82 | ina226-vcc1v2 { |
| 83 | compatible = "iio-hwmon"; |
| 84 | io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; |
| 85 | }; |
| 86 | ina226-vadj-fmc { |
| 87 | compatible = "iio-hwmon"; |
| 88 | io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; |
| 89 | }; |
| 90 | ina226-mgtavcc { |
| 91 | compatible = "iio-hwmon"; |
| 92 | io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; |
| 93 | }; |
| 94 | ina226-mgt1v2 { |
| 95 | compatible = "iio-hwmon"; |
| 96 | io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; |
| 97 | }; |
| 98 | ina226-mgt1v8 { |
| 99 | compatible = "iio-hwmon"; |
| 100 | io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; |
| 101 | }; |
| 102 | ina226-vccint-ams { |
| 103 | compatible = "iio-hwmon"; |
| 104 | io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; |
| 105 | }; |
| 106 | ina226-dac-avtt { |
| 107 | compatible = "iio-hwmon"; |
| 108 | io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; |
| 109 | }; |
| 110 | ina226-dac-avccaux { |
| 111 | compatible = "iio-hwmon"; |
| 112 | io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; |
| 113 | }; |
| 114 | ina226-adc-avcc { |
| 115 | compatible = "iio-hwmon"; |
| 116 | io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; |
| 117 | }; |
| 118 | ina226-adc-avccaux { |
| 119 | compatible = "iio-hwmon"; |
| 120 | io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; |
| 121 | }; |
| 122 | ina226-dac-avcc { |
| 123 | compatible = "iio-hwmon"; |
| 124 | io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; |
| 125 | }; |
| 126 | |
| 127 | /* 48MHz reference crystal */ |
| 128 | ref48: ref48M { |
| 129 | compatible = "fixed-clock"; |
| 130 | #clock-cells = <0>; |
| 131 | clock-frequency = <48000000>; |
| 132 | }; |
| 133 | |
Michal Simek | e315762 | 2024-01-08 10:24:45 +0100 | [diff] [blame^] | 134 | si5381_6: si5381-6 { /* refclk_usb3 - u43 */ |
Michal Simek | 508e091 | 2023-09-27 11:53:36 +0200 | [diff] [blame] | 135 | compatible = "fixed-clock"; |
| 136 | #clock-cells = <0>; |
| 137 | clock-frequency = <26000000>; |
| 138 | }; |
| 139 | }; |
| 140 | |
| 141 | &dcc { |
| 142 | status = "okay"; |
| 143 | }; |
| 144 | |
| 145 | &fpd_dma_chan1 { |
| 146 | status = "okay"; |
| 147 | }; |
| 148 | |
| 149 | &fpd_dma_chan2 { |
| 150 | status = "okay"; |
| 151 | }; |
| 152 | |
| 153 | &fpd_dma_chan3 { |
| 154 | status = "okay"; |
| 155 | }; |
| 156 | |
| 157 | &fpd_dma_chan4 { |
| 158 | status = "okay"; |
| 159 | }; |
| 160 | |
| 161 | &fpd_dma_chan5 { |
| 162 | status = "okay"; |
| 163 | }; |
| 164 | |
| 165 | &fpd_dma_chan6 { |
| 166 | status = "okay"; |
| 167 | }; |
| 168 | |
| 169 | &fpd_dma_chan7 { |
| 170 | status = "okay"; |
| 171 | }; |
| 172 | |
| 173 | &fpd_dma_chan8 { |
| 174 | status = "okay"; |
| 175 | }; |
| 176 | |
| 177 | &gem3 { |
| 178 | status = "okay"; |
| 179 | phy-handle = <&phy0>; |
| 180 | phy-mode = "rgmii-id"; |
| 181 | mdio: mdio { |
| 182 | #address-cells = <1>; |
| 183 | #size-cells = <0>; |
| 184 | phy0: ethernet-phy@c { |
| 185 | #phy-cells = <1>; |
| 186 | compatible = "ethernet-phy-id2000.a231"; |
| 187 | reg = <0xc>; |
| 188 | ti,rx-internal-delay = <0x8>; |
| 189 | ti,tx-internal-delay = <0xa>; |
| 190 | ti,fifo-depth = <0x1>; |
| 191 | ti,dp83867-rxctrl-strap-quirk; |
| 192 | reset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>; |
| 193 | }; |
| 194 | }; |
| 195 | }; |
| 196 | |
| 197 | &gpio { |
| 198 | status = "okay"; |
| 199 | gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ |
| 200 | "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */ |
| 201 | "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */ |
| 202 | "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */ |
| 203 | "", "", "BUTTON", "LED", "", /* 20 - 24 */ |
| 204 | "", "PMU_INPUT", "SFP3_TX_DISABLE", "SFP2_TX_DISABLE", "SFP1_TX_DISABLE", /* 25 - 29 */ |
| 205 | "SFP0_TX_DISABLE", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */ |
| 206 | "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */ |
| 207 | "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "SD_PWR_RST", "", /* 40 - 44 */ |
| 208 | "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */ |
| 209 | "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */ |
| 210 | "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */ |
| 211 | "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */ |
| 212 | "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */ |
| 213 | "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */ |
| 214 | "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ |
| 215 | "", "", /* 78 - 79 */ |
| 216 | "", "", "", "", "", /* 80 - 84 */ |
| 217 | "", "", "", "", "", /* 85 - 89 */ |
| 218 | "", "", "", "", "", /* 90 - 94 */ |
| 219 | "", "", "", "", "", /* 95 - 99 */ |
| 220 | "", "", "", "", "", /* 100 - 104 */ |
| 221 | "", "", "", "", "", /* 105 - 109 */ |
| 222 | "", "", "", "", "", /* 110 - 114 */ |
| 223 | "", "", "", "", "", /* 115 - 119 */ |
| 224 | "", "", "", "", "", /* 120 - 124 */ |
| 225 | "", "", "", "", "", /* 125 - 129 */ |
| 226 | "", "", "", "", "", /* 130 - 134 */ |
| 227 | "", "", "", "", "", /* 135 - 139 */ |
| 228 | "", "", "", "", "", /* 140 - 144 */ |
| 229 | "", "", "", "", "", /* 145 - 149 */ |
| 230 | "", "", "", "", "", /* 150 - 154 */ |
| 231 | "", "", "", "", "", /* 155 - 159 */ |
| 232 | "", "", "", "", "", /* 160 - 164 */ |
| 233 | "", "", "", "", "", /* 165 - 169 */ |
| 234 | "", "", "", ""; /* 170 - 173 */ |
| 235 | }; |
| 236 | |
| 237 | &i2c0 { |
| 238 | status = "okay"; |
| 239 | clock-frequency = <400000>; |
| 240 | pinctrl-names = "default", "gpio"; |
| 241 | pinctrl-0 = <&pinctrl_i2c0_default>; |
| 242 | pinctrl-1 = <&pinctrl_i2c0_gpio>; |
| 243 | scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| 244 | sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| 245 | |
| 246 | tca6416_u15: gpio@20 { /* u15 */ |
| 247 | compatible = "ti,tca6416"; |
| 248 | reg = <0x20>; |
| 249 | gpio-controller; /* interrupt not connected */ |
| 250 | #gpio-cells = <2>; |
| 251 | gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "DAC_AVTT_VOUT_SEL", /* 0 - 3 */ |
| 252 | "SI5381_INT_ALM", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */ |
| 253 | "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */ |
| 254 | "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */ |
| 255 | }; |
| 256 | |
| 257 | i2c-mux@75 { /* u17 */ |
| 258 | compatible = "nxp,pca9544"; |
| 259 | #address-cells = <1>; |
| 260 | #size-cells = <0>; |
| 261 | reg = <0x75>; |
| 262 | i2c@0 { |
| 263 | #address-cells = <1>; |
| 264 | #size-cells = <0>; |
| 265 | reg = <0>; |
| 266 | /* PS_PMBUS */ |
| 267 | /* PMBUS_ALERT done via pca9544 */ |
| 268 | vccint: ina226@40 { /* u65 */ |
| 269 | compatible = "ti,ina226"; |
| 270 | #io-channel-cells = <1>; |
| 271 | label = "ina226-vccint"; |
| 272 | reg = <0x40>; |
| 273 | shunt-resistor = <5000>; |
| 274 | }; |
| 275 | vccint_io_bram_ps: ina226@41 { /* u57 */ |
| 276 | compatible = "ti,ina226"; |
| 277 | #io-channel-cells = <1>; |
| 278 | label = "ina226-vccint-io-bram-ps"; |
| 279 | reg = <0x41>; |
| 280 | shunt-resistor = <5000>; |
| 281 | }; |
| 282 | vcc1v8: ina226@42 { /* u60 */ |
| 283 | compatible = "ti,ina226"; |
| 284 | #io-channel-cells = <1>; |
| 285 | label = "ina226-vcc1v8"; |
| 286 | reg = <0x42>; |
| 287 | shunt-resistor = <2000>; |
| 288 | }; |
| 289 | vcc1v2: ina226@43 { /* u58 */ |
| 290 | compatible = "ti,ina226"; |
| 291 | #io-channel-cells = <1>; |
| 292 | label = "ina226-vcc1v2"; |
| 293 | reg = <0x43>; |
| 294 | shunt-resistor = <5000>; |
| 295 | }; |
| 296 | vadj_fmc: ina226@45 { /* u62 */ |
| 297 | compatible = "ti,ina226"; |
| 298 | #io-channel-cells = <1>; |
| 299 | label = "ina226-vadj-fmc"; |
| 300 | reg = <0x45>; |
| 301 | shunt-resistor = <5000>; |
| 302 | }; |
| 303 | mgtavcc: ina226@46 { /* u67 */ |
| 304 | compatible = "ti,ina226"; |
| 305 | #io-channel-cells = <1>; |
| 306 | label = "ina226-mgtavcc"; |
| 307 | reg = <0x46>; |
| 308 | shunt-resistor = <2000>; |
| 309 | }; |
| 310 | mgt1v2: ina226@47 { /* u63 */ |
| 311 | compatible = "ti,ina226"; |
| 312 | #io-channel-cells = <1>; |
| 313 | label = "ina226-mgt1v2"; |
| 314 | reg = <0x47>; |
| 315 | shunt-resistor = <5000>; /* Not in schematics */ |
| 316 | }; |
| 317 | mgt1v8: ina226@48 { /* u64 */ |
| 318 | compatible = "ti,ina226"; |
| 319 | #io-channel-cells = <1>; |
| 320 | label = "ina226-mgt1v8"; |
| 321 | reg = <0x48>; |
| 322 | shunt-resistor = <5000>; |
| 323 | }; |
| 324 | vccint_ams: ina226@49 { /* u61 */ |
| 325 | compatible = "ti,ina226"; |
| 326 | #io-channel-cells = <1>; |
| 327 | label = "ina226-vccint-ams"; |
| 328 | reg = <0x49>; |
| 329 | shunt-resistor = <5000>; |
| 330 | }; |
| 331 | dac_avtt: ina226@4a { /* u59 */ |
| 332 | compatible = "ti,ina226"; |
| 333 | #io-channel-cells = <1>; |
| 334 | label = "ina226-dac-avtt"; |
| 335 | reg = <0x4a>; |
| 336 | shunt-resistor = <5000>; |
| 337 | }; |
| 338 | dac_avccaux: ina226@4b { /* u124 */ |
| 339 | compatible = "ti,ina226"; |
| 340 | #io-channel-cells = <1>; |
| 341 | label = "ina226-dac-avccaux"; |
| 342 | reg = <0x4b>; |
| 343 | shunt-resistor = <5000>; |
| 344 | }; |
| 345 | adc_avcc: ina226@4c { /* u75 */ |
| 346 | compatible = "ti,ina226"; |
| 347 | #io-channel-cells = <1>; |
| 348 | label = "ina226-adc-avcc"; |
| 349 | reg = <0x4c>; |
| 350 | shunt-resistor = <5000>; |
| 351 | }; |
| 352 | adc_avccaux: ina226@4d { /* u71 */ |
| 353 | compatible = "ti,ina226"; |
| 354 | #io-channel-cells = <1>; |
| 355 | label = "ina226-adc-avccaux"; |
| 356 | reg = <0x4d>; |
| 357 | shunt-resistor = <5000>; |
| 358 | }; |
| 359 | dac_avcc: ina226@4e { /* u77 */ |
| 360 | compatible = "ti,ina226"; |
| 361 | #io-channel-cells = <1>; |
| 362 | label = "ina226-dac-avcc"; |
| 363 | reg = <0x4e>; |
| 364 | shunt-resistor = <5000>; |
| 365 | }; |
| 366 | }; |
| 367 | i2c@1 { |
| 368 | #address-cells = <1>; |
| 369 | #size-cells = <0>; |
| 370 | reg = <1>; |
| 371 | /* NC */ |
| 372 | }; |
| 373 | i2c@2 { |
| 374 | #address-cells = <1>; |
| 375 | #size-cells = <0>; |
| 376 | reg = <2>; |
| 377 | /* u104 - ir35215 0x10/0x40 */ |
| 378 | /* u127 - ir38164 0x1b/0x4b */ |
| 379 | /* u112 - ir38164 0x13/0x43 */ |
| 380 | /* u123 - ir38164 0x1c/0x4c */ |
| 381 | |
| 382 | irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ |
| 383 | compatible = "infineon,irps5401"; |
| 384 | reg = <0x44>; /* i2c addr 0x14 */ |
| 385 | }; |
| 386 | irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ |
| 387 | compatible = "infineon,irps5401"; |
| 388 | reg = <0x45>; /* i2c addr 0x15 */ |
| 389 | }; |
| 390 | /* J21 header too */ |
| 391 | |
| 392 | }; |
| 393 | i2c@3 { |
| 394 | #address-cells = <1>; |
| 395 | #size-cells = <0>; |
| 396 | reg = <3>; |
| 397 | /* SYSMON */ |
| 398 | }; |
| 399 | }; |
| 400 | /* u38 MPS430 */ |
| 401 | }; |
| 402 | |
| 403 | &i2c1 { |
| 404 | status = "okay"; |
| 405 | clock-frequency = <400000>; |
| 406 | pinctrl-names = "default", "gpio"; |
| 407 | pinctrl-0 = <&pinctrl_i2c1_default>; |
| 408 | pinctrl-1 = <&pinctrl_i2c1_gpio>; |
| 409 | scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| 410 | sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| 411 | |
| 412 | i2c-mux@74 { |
| 413 | compatible = "nxp,pca9548"; /* u20 */ |
| 414 | #address-cells = <1>; |
| 415 | #size-cells = <0>; |
| 416 | reg = <0x74>; |
| 417 | /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ |
| 418 | i2c_eeprom: i2c@0 { |
| 419 | #address-cells = <1>; |
| 420 | #size-cells = <0>; |
| 421 | reg = <0>; |
| 422 | /* |
| 423 | * IIC_EEPROM 1kB memory which uses 256B blocks |
| 424 | * where every block has different address. |
| 425 | * 0 - 256B address 0x54 |
| 426 | * 256B - 512B address 0x55 |
| 427 | * 512B - 768B address 0x56 |
| 428 | * 768B - 1024B address 0x57 |
| 429 | */ |
| 430 | eeprom: eeprom@54 { /* u21 */ |
| 431 | compatible = "atmel,24c128"; |
| 432 | reg = <0x54>; |
| 433 | }; |
| 434 | }; |
| 435 | i2c_si5381: i2c@1 { |
| 436 | #address-cells = <1>; |
| 437 | #size-cells = <0>; |
| 438 | reg = <1>; |
| 439 | /* SI5381 - u43 */ |
| 440 | /* si5381: clock-generator@68 { |
| 441 | reg = <0x68>; |
| 442 | };*/ |
| 443 | }; |
| 444 | i2c_si570_user_c0: i2c@2 { |
| 445 | #address-cells = <1>; |
| 446 | #size-cells = <0>; |
| 447 | reg = <2>; |
| 448 | si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */ |
| 449 | #clock-cells = <0>; |
| 450 | compatible = "silabs,si570"; |
| 451 | reg = <0x5d>; |
| 452 | temperature-stability = <50>; |
| 453 | factory-fout = <300000000>; |
| 454 | clock-frequency = <300000000>; |
| 455 | clock-output-names = "si570_user_c0"; |
| 456 | }; |
| 457 | }; |
| 458 | i2c_si570_mgt: i2c@3 { |
| 459 | #address-cells = <1>; |
| 460 | #size-cells = <0>; |
| 461 | reg = <3>; |
| 462 | si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */ |
| 463 | #clock-cells = <0>; |
| 464 | compatible = "silabs,si570"; |
| 465 | reg = <0x5d>; |
| 466 | temperature-stability = <50>; |
| 467 | factory-fout = <156250000>; |
| 468 | clock-frequency = <156250000>; |
| 469 | clock-output-names = "si570_mgt"; |
| 470 | }; |
| 471 | }; |
| 472 | i2c_8a34001: i2c@4 { |
| 473 | #address-cells = <1>; |
| 474 | #size-cells = <0>; |
| 475 | reg = <4>; |
| 476 | /* U409B - 8a34001 */ |
| 477 | }; |
| 478 | i2c_clk104: i2c@5 { |
| 479 | #address-cells = <1>; |
| 480 | #size-cells = <0>; |
| 481 | reg = <5>; |
| 482 | /* CLK104_SDA */ |
| 483 | }; |
| 484 | i2c@6 { |
| 485 | #address-cells = <1>; |
| 486 | #size-cells = <0>; |
| 487 | reg = <6>; |
| 488 | /* RFMCP connector */ |
| 489 | }; |
| 490 | /* 7 NC */ |
| 491 | }; |
| 492 | |
| 493 | i2c-mux@75 { |
| 494 | compatible = "nxp,pca9548"; /* u22 */ |
| 495 | #address-cells = <1>; |
| 496 | #size-cells = <0>; |
| 497 | reg = <0x75>; |
| 498 | /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ |
| 499 | i2c@0 { |
| 500 | #address-cells = <1>; |
| 501 | #size-cells = <0>; |
| 502 | reg = <0>; |
| 503 | /* FMCP_HSPC_IIC */ |
| 504 | }; |
| 505 | i2c_si570_psrefclk: i2c@1 { |
| 506 | #address-cells = <1>; |
| 507 | #size-cells = <0>; |
| 508 | reg = <1>; |
| 509 | si570_3: clock-generator@5d { /* USER SI570 PSREFCLK - u130 */ |
| 510 | #clock-cells = <0>; |
| 511 | compatible = "silabs,si570"; |
| 512 | reg = <0x5d>; |
| 513 | temperature-stability = <50>; |
| 514 | factory-fout = <33333333>; |
| 515 | clock-frequency = <33333333>; |
| 516 | clock-output-names = "si570_ps_ref_clk"; |
| 517 | silabs,skip-recall; |
| 518 | }; |
| 519 | }; |
| 520 | i2c@2 { |
| 521 | #address-cells = <1>; |
| 522 | #size-cells = <0>; |
| 523 | reg = <2>; |
| 524 | /* SYSMON */ |
| 525 | }; |
| 526 | i2c@3 { |
| 527 | #address-cells = <1>; |
| 528 | #size-cells = <0>; |
| 529 | reg = <3>; |
| 530 | /* DDR4 SODIMM */ |
| 531 | }; |
| 532 | i2c@4 { |
| 533 | #address-cells = <1>; |
| 534 | #size-cells = <0>; |
| 535 | reg = <4>; |
| 536 | /* SFP3 */ |
| 537 | }; |
| 538 | i2c@5 { |
| 539 | #address-cells = <1>; |
| 540 | #size-cells = <0>; |
| 541 | reg = <5>; |
| 542 | /* SFP2 */ |
| 543 | }; |
| 544 | i2c@6 { |
| 545 | #address-cells = <1>; |
| 546 | #size-cells = <0>; |
| 547 | reg = <6>; |
| 548 | /* SFP1 */ |
| 549 | }; |
| 550 | i2c@7 { |
| 551 | #address-cells = <1>; |
| 552 | #size-cells = <0>; |
| 553 | reg = <7>; |
| 554 | /* SFP0 */ |
| 555 | }; |
| 556 | }; |
| 557 | /* u38 MPS430 */ |
| 558 | }; |
| 559 | |
| 560 | &pinctrl0 { |
| 561 | status = "okay"; |
| 562 | pinctrl_i2c0_default: i2c0-default { |
| 563 | mux { |
| 564 | groups = "i2c0_3_grp"; |
| 565 | function = "i2c0"; |
| 566 | }; |
| 567 | |
| 568 | conf { |
| 569 | groups = "i2c0_3_grp"; |
| 570 | bias-pull-up; |
| 571 | slew-rate = <SLEW_RATE_SLOW>; |
| 572 | power-source = <IO_STANDARD_LVCMOS18>; |
| 573 | }; |
| 574 | }; |
| 575 | |
Michal Simek | cf3cd80 | 2023-12-19 17:16:50 +0100 | [diff] [blame] | 576 | pinctrl_i2c0_gpio: i2c0-gpio-grp { |
Michal Simek | 508e091 | 2023-09-27 11:53:36 +0200 | [diff] [blame] | 577 | mux { |
| 578 | groups = "gpio0_14_grp", "gpio0_15_grp"; |
| 579 | function = "gpio0"; |
| 580 | }; |
| 581 | |
| 582 | conf { |
| 583 | groups = "gpio0_14_grp", "gpio0_15_grp"; |
| 584 | slew-rate = <SLEW_RATE_SLOW>; |
| 585 | power-source = <IO_STANDARD_LVCMOS18>; |
| 586 | }; |
| 587 | }; |
| 588 | |
| 589 | pinctrl_i2c1_default: i2c1-default { |
| 590 | mux { |
| 591 | groups = "i2c1_4_grp"; |
| 592 | function = "i2c1"; |
| 593 | }; |
| 594 | |
| 595 | conf { |
| 596 | groups = "i2c1_4_grp"; |
| 597 | bias-pull-up; |
| 598 | slew-rate = <SLEW_RATE_SLOW>; |
| 599 | power-source = <IO_STANDARD_LVCMOS18>; |
| 600 | }; |
| 601 | }; |
| 602 | |
Michal Simek | cf3cd80 | 2023-12-19 17:16:50 +0100 | [diff] [blame] | 603 | pinctrl_i2c1_gpio: i2c1-gpio-grp { |
Michal Simek | 508e091 | 2023-09-27 11:53:36 +0200 | [diff] [blame] | 604 | mux { |
| 605 | groups = "gpio0_16_grp", "gpio0_17_grp"; |
| 606 | function = "gpio0"; |
| 607 | }; |
| 608 | |
| 609 | conf { |
| 610 | groups = "gpio0_16_grp", "gpio0_17_grp"; |
| 611 | slew-rate = <SLEW_RATE_SLOW>; |
| 612 | power-source = <IO_STANDARD_LVCMOS18>; |
| 613 | }; |
| 614 | }; |
| 615 | }; |
| 616 | |
| 617 | &qspi { |
| 618 | status = "okay"; |
| 619 | num-cs = <2>; |
| 620 | flash@0 { |
| 621 | compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 2Gb */ |
| 622 | #address-cells = <1>; |
| 623 | #size-cells = <1>; |
| 624 | reg = <0>, <1>; |
| 625 | parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */ |
| 626 | spi-tx-bus-width = <4>; |
| 627 | spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ |
| 628 | spi-max-frequency = <108000000>; /* Based on DC1 spec */ |
| 629 | }; |
| 630 | }; |
| 631 | |
| 632 | &rtc { |
| 633 | status = "okay"; |
| 634 | }; |
| 635 | |
| 636 | /* SD1 with level shifter */ |
| 637 | &sdhci1 { |
| 638 | status = "okay"; |
| 639 | disable-wp; |
| 640 | /* |
| 641 | * This property should be removed for supporting UHS mode |
| 642 | */ |
| 643 | no-1-8-v; |
| 644 | xlnx,mio-bank = <1>; |
| 645 | }; |
| 646 | |
| 647 | &psgtr { |
| 648 | status = "okay"; |
| 649 | /* hspc_dp4, hspc_dp5, usb3, hspc_dp6 */ |
| 650 | clocks = <&si5381_6>; |
| 651 | clock-names = "ref2"; |
| 652 | }; |
| 653 | |
| 654 | &uart0 { |
| 655 | status = "okay"; |
| 656 | }; |
| 657 | |
| 658 | /* ULPI SMSC USB3320 */ |
| 659 | &usb0 { |
| 660 | status = "okay"; |
| 661 | phy-names = "usb3-phy"; |
| 662 | phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; |
| 663 | }; |
| 664 | |
| 665 | &dwc3_0 { |
| 666 | status = "okay"; |
| 667 | dr_mode = "host"; |
| 668 | snps,usb3_lpm_capable; |
| 669 | }; |