Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / e2f33aeefe6a6178018a4b8981af04c629cd1a2a / . / include / common_timing_params.h
blob: 821de21de7300efaeda1fd5bac19c130bba5b19f [file] [log] [blame]
Kumar Gala124b0822008-08-26 15:01:29 -0500[diff] [blame]1/*
York Sun2896cb72014-03-27 17:54:47 -0700[diff] [blame]2 * Copyright 2008-2014 Freescale Semiconductor, Inc.
Kumar Gala124b0822008-08-26 15:01:29 -0500[diff] [blame]3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
7 */
8
9#ifndef COMMON_TIMING_PARAMS_H
10#define COMMON_TIMING_PARAMS_H
11
12typedef struct {
13 /* parameters to constrict */
14
Priyanka Jain4a717412013-09-25 10:41:19 +0530[diff] [blame]15 unsigned int tckmin_x_ps;
16 unsigned int tckmax_ps;
Priyanka Jain4a717412013-09-25 10:41:19 +0530[diff] [blame]17 unsigned int trcd_ps;
18 unsigned int trp_ps;
19 unsigned int tras_ps;
York Sun2896cb72014-03-27 17:54:47 -0700[diff] [blame]20#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
21 unsigned int taamin_ps;
22#endif
Kumar Gala124b0822008-08-26 15:01:29 -0500[diff] [blame]23
York Sun2896cb72014-03-27 17:54:47 -0700[diff] [blame]24#ifdef CONFIG_SYS_FSL_DDR4
25 unsigned int trfc1_ps;
26 unsigned int trfc2_ps;
27 unsigned int trfc4_ps;
28 unsigned int trrds_ps;
29 unsigned int trrdl_ps;
30 unsigned int tccdl_ps;
31#else
Priyanka Jain4a717412013-09-25 10:41:19 +0530[diff] [blame]32 unsigned int twtr_ps; /* maximum = 63750 ps */
33 unsigned int trfc_ps; /* maximum = 255 ns + 256 ns + .75 ns
Kumar Gala124b0822008-08-26 15:01:29 -0500[diff] [blame]34 = 511750 ps */
35
Priyanka Jain4a717412013-09-25 10:41:19 +0530[diff] [blame]36 unsigned int trrd_ps; /* maximum = 63750 ps */
York Sun2896cb72014-03-27 17:54:47 -0700[diff] [blame]37 unsigned int trtp_ps; /* byte 38, spd->trtp */
38#endif
39 unsigned int twr_ps; /* maximum = 63750 ps */
Priyanka Jain4a717412013-09-25 10:41:19 +0530[diff] [blame]40 unsigned int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */
Kumar Gala124b0822008-08-26 15:01:29 -0500[diff] [blame]41
42 unsigned int refresh_rate_ps;
Valentin Longchamp0b810932013-10-18 11:47:20 +0200[diff] [blame]43 unsigned int extended_op_srt;
Kumar Gala124b0822008-08-26 15:01:29 -0500[diff] [blame]44
York Sun2896cb72014-03-27 17:54:47 -0700[diff] [blame]45#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
Priyanka Jain4a717412013-09-25 10:41:19 +0530[diff] [blame]46 unsigned int tis_ps; /* byte 32, spd->ca_setup */
47 unsigned int tih_ps; /* byte 33, spd->ca_hold */
48 unsigned int tds_ps; /* byte 34, spd->data_setup */
49 unsigned int tdh_ps; /* byte 35, spd->data_hold */
Priyanka Jain4a717412013-09-25 10:41:19 +0530[diff] [blame]50 unsigned int tdqsq_max_ps; /* byte 44, spd->tdqsq */
51 unsigned int tqhs_ps; /* byte 45, spd->tqhs */
York Sun2896cb72014-03-27 17:54:47 -0700[diff] [blame]52#endif
Kumar Gala124b0822008-08-26 15:01:29 -0500[diff] [blame]53
54 unsigned int ndimms_present;
York Sun2896cb72014-03-27 17:54:47 -0700[diff] [blame]55 unsigned int lowest_common_spd_caslat;
Kumar Gala124b0822008-08-26 15:01:29 -0500[diff] [blame]56 unsigned int highest_common_derated_caslat;
57 unsigned int additive_latency;
Priyanka Jain4a717412013-09-25 10:41:19 +0530[diff] [blame]58 unsigned int all_dimms_burst_lengths_bitmask;
59 unsigned int all_dimms_registered;
60 unsigned int all_dimms_unbuffered;
61 unsigned int all_dimms_ecc_capable;
Kumar Gala124b0822008-08-26 15:01:29 -0500[diff] [blame]62
63 unsigned long long total_mem;
64 unsigned long long base_address;
yorkde879322010-07-02 22:25:55 +0000[diff] [blame]65
66 /* DDR3 RDIMM */
67 unsigned char rcw[16]; /* Register Control Word 0-15 */
Kumar Gala124b0822008-08-26 15:01:29 -0500[diff] [blame]68} common_timing_params_t;
69
70#endif