Chris Packham | 2e0d2ba | 2018-12-10 10:41:15 +1300 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright (C) Marvell International Ltd. and its affiliates |
| 4 | */ |
| 5 | |
Chris Packham | 1a07d21 | 2018-05-10 13:28:29 +1200 | [diff] [blame] | 6 | #ifndef _MV_DDR_PLAT_H |
| 7 | #define _MV_DDR_PLAT_H |
| 8 | |
Pali Rohár | 6d5e3fe | 2021-03-02 11:17:41 +0100 | [diff] [blame] | 9 | #include <linux/delay.h> |
| 10 | |
Chris Packham | 4bf81db | 2018-12-03 14:26:49 +1300 | [diff] [blame] | 11 | #define MAX_DEVICE_NUM 1 |
Chris Packham | 1a07d21 | 2018-05-10 13:28:29 +1200 | [diff] [blame] | 12 | #define MAX_INTERFACE_NUM 1 |
| 13 | #define MAX_BUS_NUM 5 |
| 14 | #define DDR_IF_CTRL_SUBPHYS_NUM 3 |
| 15 | |
| 16 | #define DFS_LOW_FREQ_VALUE 120 |
| 17 | #define SDRAM_CS_SIZE 0xfffffff /* FIXME: implement a function for cs size for each platform */ |
| 18 | |
| 19 | #define INTER_REGS_BASE SOC_REGS_PHY_BASE |
| 20 | #define AP_INT_REG_START_ADDR 0xd0000000 |
| 21 | #define AP_INT_REG_END_ADDR 0xd0100000 |
| 22 | |
| 23 | /* Controler bus divider 1 for 32 bit, 2 for 64 bit */ |
| 24 | #define DDR_CONTROLLER_BUS_WIDTH_MULTIPLIER 1 |
| 25 | |
| 26 | /* Tune internal training params values */ |
| 27 | #define TUNE_TRAINING_PARAMS_CK_DELAY 160 |
| 28 | #define TUNE_TRAINING_PARAMS_PHYREG3VAL 0xA |
| 29 | #define TUNE_TRAINING_PARAMS_PRI_DATA 123 |
| 30 | #define TUNE_TRAINING_PARAMS_NRI_DATA 123 |
| 31 | #define TUNE_TRAINING_PARAMS_PRI_CTRL 74 |
| 32 | #define TUNE_TRAINING_PARAMS_NRI_CTRL 74 |
| 33 | #define TUNE_TRAINING_PARAMS_P_ODT_DATA 45 |
| 34 | #define TUNE_TRAINING_PARAMS_N_ODT_DATA 45 |
| 35 | #define TUNE_TRAINING_PARAMS_P_ODT_CTRL 45 |
| 36 | #define TUNE_TRAINING_PARAMS_N_ODT_CTRL 45 |
| 37 | #define TUNE_TRAINING_PARAMS_DIC 0x2 |
| 38 | #define TUNE_TRAINING_PARAMS_ODT_CONFIG_2CS 0x120012 |
| 39 | #define TUNE_TRAINING_PARAMS_ODT_CONFIG_1CS 0x10000 |
| 40 | #define TUNE_TRAINING_PARAMS_RTT_NOM 0x44 |
| 41 | |
Tony Dinh | e2c524b | 2023-01-18 19:03:04 -0800 | [diff] [blame^] | 42 | #if defined(CONFIG_DDR4) |
| 43 | #define TUNE_TRAINING_PARAMS_P_ODT_DATA_DDR4 0x1A |
| 44 | #define TUNE_TRAINING_PARAMS_DIC_DDR4 0x0 |
| 45 | #define TUNE_TRAINING_PARAMS_ODT_CONFIG_DDR4 0 /* 0x330012 */ |
| 46 | #define TUNE_TRAINING_PARAMS_RTT_NOM_DDR4 0 /* 0x400, RZQ/3 = 0x600 */ |
| 47 | #define TUNE_TRAINING_PARAMS_RTT_WR_1CS 0x200 /*RZQ/1 = 0x400*/ |
| 48 | #define TUNE_TRAINING_PARAMS_RTT_WR_2CS 0x200 /*RZQ/1 = 0x400*/ |
| 49 | #define TUNE_TRAINING_PARAMS_RTT_PARK_1CS 0 |
| 50 | #define TUNE_TRAINING_PARAMS_RTT_PARK_2CS 0 |
| 51 | #else /* CONFIG_DDR4 */ |
Chris Packham | 1a07d21 | 2018-05-10 13:28:29 +1200 | [diff] [blame] | 52 | #define TUNE_TRAINING_PARAMS_RTT_WR_1CS 0x0 /*off*/ |
| 53 | #define TUNE_TRAINING_PARAMS_RTT_WR_2CS 0x0 /*off*/ |
Tony Dinh | e2c524b | 2023-01-18 19:03:04 -0800 | [diff] [blame^] | 54 | #endif /* CONFIG_DDR4 */ |
Chris Packham | 1a07d21 | 2018-05-10 13:28:29 +1200 | [diff] [blame] | 55 | |
| 56 | #define MARVELL_BOARD MARVELL_BOARD_ID_BASE |
| 57 | |
| 58 | |
| 59 | #define REG_DEVICE_SAR1_ADDR 0xe4204 |
| 60 | #define RST2_CPU_DDR_CLOCK_SELECT_IN_OFFSET 17 |
| 61 | #define RST2_CPU_DDR_CLOCK_SELECT_IN_MASK 0x1f |
| 62 | #define DEVICE_SAMPLE_AT_RESET2_REG 0x18604 |
| 63 | |
| 64 | #define DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_OFFSET 0 |
| 65 | #define DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_25MHZ 0 |
| 66 | #define DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_40MHZ 1 |
| 67 | |
| 68 | /* DRAM Windows */ |
| 69 | #define REG_XBAR_WIN_5_CTRL_ADDR 0x20050 |
| 70 | #define REG_XBAR_WIN_5_BASE_ADDR 0x20054 |
| 71 | |
| 72 | /* DRAM Windows */ |
| 73 | #define REG_XBAR_WIN_4_CTRL_ADDR 0x20040 |
| 74 | #define REG_XBAR_WIN_4_BASE_ADDR 0x20044 |
| 75 | #define REG_XBAR_WIN_4_REMAP_ADDR 0x20048 |
| 76 | #define REG_XBAR_WIN_7_REMAP_ADDR 0x20078 |
| 77 | #define REG_XBAR_WIN_16_CTRL_ADDR 0x200d0 |
| 78 | #define REG_XBAR_WIN_16_BASE_ADDR 0x200d4 |
| 79 | #define REG_XBAR_WIN_16_REMAP_ADDR 0x200dc |
| 80 | #define REG_XBAR_WIN_19_CTRL_ADDR 0x200e8 |
| 81 | |
| 82 | #define REG_FASTPATH_WIN_BASE_ADDR(win) (0x20180 + (0x8 * win)) |
| 83 | #define REG_FASTPATH_WIN_CTRL_ADDR(win) (0x20184 + (0x8 * win)) |
| 84 | |
| 85 | #define CPU_CONFIGURATION_REG(id) (0x21800 + (id * 0x100)) |
| 86 | #define CPU_MRVL_ID_OFFSET 0x10 |
| 87 | #define SAR1_CPU_CORE_MASK 0x00000018 |
| 88 | #define SAR1_CPU_CORE_OFFSET 3 |
| 89 | |
| 90 | /* SatR defined too change topology busWidth and ECC configuration */ |
| 91 | #define DDR_SATR_CONFIG_MASK_WIDTH 0x8 |
| 92 | #define DDR_SATR_CONFIG_MASK_ECC 0x10 |
| 93 | #define DDR_SATR_CONFIG_MASK_ECC_PUP 0x20 |
| 94 | |
| 95 | #define REG_SAMPLE_RESET_HIGH_ADDR 0x18600 |
| 96 | |
| 97 | #define MV_BOARD_REFCLK_25MHZ 25000000 |
| 98 | #define MV_BOARD_REFCLK MV_BOARD_REFCLK_25MHZ |
| 99 | |
| 100 | #define MAX_DQ_NUM 40 |
| 101 | |
| 102 | /* dram line buffer registers */ |
| 103 | #define DLB_CTRL_REG 0x1700 |
| 104 | #define DLB_EN_OFFS 0 |
| 105 | #define DLB_EN_MASK 0x1 |
| 106 | #define DLB_EN_ENA 1 |
| 107 | #define DLB_EN_DIS 0 |
| 108 | #define WR_COALESCE_EN_OFFS 2 |
| 109 | #define WR_COALESCE_EN_MASK 0x1 |
| 110 | #define WR_COALESCE_EN_ENA 1 |
| 111 | #define WR_COALESCE_EN_DIS 0 |
| 112 | #define AXI_PREFETCH_EN_OFFS 3 |
| 113 | #define AXI_PREFETCH_EN_MASK 0x1 |
| 114 | #define AXI_PREFETCH_EN_ENA 1 |
| 115 | #define AXI_PREFETCH_EN_DIS 0 |
| 116 | #define MBUS_PREFETCH_EN_OFFS 4 |
| 117 | #define MBUS_PREFETCH_EN_MASK 0x1 |
| 118 | #define MBUS_PREFETCH_EN_ENA 1 |
| 119 | #define MBUS_PREFETCH_EN_DIS 0 |
| 120 | #define PREFETCH_NXT_LN_SZ_TRIG_OFFS 6 |
| 121 | #define PREFETCH_NXT_LN_SZ_TRIG_MASK 0x1 |
| 122 | #define PREFETCH_NXT_LN_SZ_TRIG_ENA 1 |
| 123 | #define PREFETCH_NXT_LN_SZ_TRIG_DIS 0 |
| 124 | |
| 125 | #define DLB_BUS_OPT_WT_REG 0x1704 |
| 126 | #define DLB_AGING_REG 0x1708 |
| 127 | #define DLB_EVICTION_CTRL_REG 0x170c |
| 128 | #define DLB_EVICTION_TIMERS_REG 0x1710 |
| 129 | #define DLB_USER_CMD_REG 0x1714 |
| 130 | #define DLB_WTS_DIFF_CS_REG 0x1770 |
| 131 | #define DLB_WTS_DIFF_BG_REG 0x1774 |
| 132 | #define DLB_WTS_SAME_BG_REG 0x1778 |
| 133 | #define DLB_WTS_CMDS_REG 0x177c |
| 134 | #define DLB_WTS_ATTR_PRIO_REG 0x1780 |
| 135 | #define DLB_QUEUE_MAP_REG 0x1784 |
| 136 | #define DLB_SPLIT_REG 0x1788 |
| 137 | |
Chris Packham | 4bf81db | 2018-12-03 14:26:49 +1300 | [diff] [blame] | 138 | /* ck swap control subphy number */ |
| 139 | #define CK_SWAP_CTRL_PHY_NUM 2 |
| 140 | |
Chris Packham | 1a07d21 | 2018-05-10 13:28:29 +1200 | [diff] [blame] | 141 | /* Subphy result control per byte registers */ |
| 142 | #define RESULT_CONTROL_BYTE_PUP_0_REG 0x1830 |
| 143 | #define RESULT_CONTROL_BYTE_PUP_1_REG 0x1834 |
| 144 | #define RESULT_CONTROL_BYTE_PUP_2_REG 0x1838 |
| 145 | #define RESULT_CONTROL_BYTE_PUP_3_REG 0x183c |
| 146 | #define RESULT_CONTROL_BYTE_PUP_4_REG 0x18b0 |
| 147 | |
| 148 | /* Subphy result control per bit registers */ |
| 149 | #define RESULT_CONTROL_PUP_0_BIT_0_REG 0x18b4 |
| 150 | #define RESULT_CONTROL_PUP_0_BIT_1_REG 0x18b8 |
| 151 | #define RESULT_CONTROL_PUP_0_BIT_2_REG 0x18bc |
| 152 | #define RESULT_CONTROL_PUP_0_BIT_3_REG 0x18c0 |
| 153 | #define RESULT_CONTROL_PUP_0_BIT_4_REG 0x18c4 |
| 154 | #define RESULT_CONTROL_PUP_0_BIT_5_REG 0x18c8 |
| 155 | #define RESULT_CONTROL_PUP_0_BIT_6_REG 0x18cc |
| 156 | #define RESULT_CONTROL_PUP_0_BIT_7_REG 0x18f0 |
| 157 | |
| 158 | #define RESULT_CONTROL_PUP_1_BIT_0_REG 0x18f4 |
| 159 | #define RESULT_CONTROL_PUP_1_BIT_1_REG 0x18f8 |
| 160 | #define RESULT_CONTROL_PUP_1_BIT_2_REG 0x18fc |
| 161 | #define RESULT_CONTROL_PUP_1_BIT_3_REG 0x1930 |
| 162 | #define RESULT_CONTROL_PUP_1_BIT_4_REG 0x1934 |
| 163 | #define RESULT_CONTROL_PUP_1_BIT_5_REG 0x1938 |
| 164 | #define RESULT_CONTROL_PUP_1_BIT_6_REG 0x193c |
| 165 | #define RESULT_CONTROL_PUP_1_BIT_7_REG 0x19b0 |
| 166 | |
| 167 | #define RESULT_CONTROL_PUP_2_BIT_0_REG 0x19b4 |
| 168 | #define RESULT_CONTROL_PUP_2_BIT_1_REG 0x19b8 |
| 169 | #define RESULT_CONTROL_PUP_2_BIT_2_REG 0x19bc |
| 170 | #define RESULT_CONTROL_PUP_2_BIT_3_REG 0x19c0 |
| 171 | #define RESULT_CONTROL_PUP_2_BIT_4_REG 0x19c4 |
| 172 | #define RESULT_CONTROL_PUP_2_BIT_5_REG 0x19c8 |
| 173 | #define RESULT_CONTROL_PUP_2_BIT_6_REG 0x19cc |
| 174 | #define RESULT_CONTROL_PUP_2_BIT_7_REG 0x19f0 |
| 175 | |
| 176 | #define RESULT_CONTROL_PUP_3_BIT_0_REG 0x19f4 |
| 177 | #define RESULT_CONTROL_PUP_3_BIT_1_REG 0x19f8 |
| 178 | #define RESULT_CONTROL_PUP_3_BIT_2_REG 0x19fc |
| 179 | #define RESULT_CONTROL_PUP_3_BIT_3_REG 0x1a30 |
| 180 | #define RESULT_CONTROL_PUP_3_BIT_4_REG 0x1a34 |
| 181 | #define RESULT_CONTROL_PUP_3_BIT_5_REG 0x1a38 |
| 182 | #define RESULT_CONTROL_PUP_3_BIT_6_REG 0x1a3c |
| 183 | #define RESULT_CONTROL_PUP_3_BIT_7_REG 0x1ab0 |
| 184 | |
| 185 | #define RESULT_CONTROL_PUP_4_BIT_0_REG 0x1ab4 |
| 186 | #define RESULT_CONTROL_PUP_4_BIT_1_REG 0x1ab8 |
| 187 | #define RESULT_CONTROL_PUP_4_BIT_2_REG 0x1abc |
| 188 | #define RESULT_CONTROL_PUP_4_BIT_3_REG 0x1ac0 |
| 189 | #define RESULT_CONTROL_PUP_4_BIT_4_REG 0x1ac4 |
| 190 | #define RESULT_CONTROL_PUP_4_BIT_5_REG 0x1ac8 |
| 191 | #define RESULT_CONTROL_PUP_4_BIT_6_REG 0x1acc |
| 192 | #define RESULT_CONTROL_PUP_4_BIT_7_REG 0x1af0 |
| 193 | |
| 194 | /* CPU */ |
| 195 | #define REG_BOOTROM_ROUTINE_ADDR 0x182d0 |
| 196 | #define REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS 12 |
| 197 | |
| 198 | /* Matrix enables DRAM modes (bus width/ECC) per boardId */ |
| 199 | #define TOPOLOGY_UPDATE_32BIT 0 |
| 200 | #define TOPOLOGY_UPDATE_32BIT_ECC 1 |
| 201 | #define TOPOLOGY_UPDATE_16BIT 2 |
| 202 | #define TOPOLOGY_UPDATE_16BIT_ECC 3 |
| 203 | #define TOPOLOGY_UPDATE_16BIT_ECC_PUP3 4 |
| 204 | #define TOPOLOGY_UPDATE { \ |
| 205 | /* 32Bit, 32bit ECC, 16bit, 16bit ECC PUP4, 16bit ECC PUP3 */ \ |
| 206 | {1, 1, 1, 1, 1}, /* RD_NAS_68XX_ID */ \ |
| 207 | {1, 1, 1, 1, 1}, /* DB_68XX_ID */ \ |
| 208 | {1, 0, 1, 0, 1}, /* RD_AP_68XX_ID */ \ |
| 209 | {1, 0, 1, 0, 1}, /* DB_AP_68XX_ID */ \ |
| 210 | {1, 0, 1, 0, 1}, /* DB_GP_68XX_ID */ \ |
| 211 | {0, 0, 1, 1, 0}, /* DB_BP_6821_ID */ \ |
| 212 | {1, 1, 1, 1, 1} /* DB_AMC_6820_ID */ \ |
| 213 | }; |
| 214 | |
| 215 | enum { |
| 216 | CPU_1066MHZ_DDR_400MHZ, |
| 217 | CPU_RESERVED_DDR_RESERVED0, |
| 218 | CPU_667MHZ_DDR_667MHZ, |
| 219 | CPU_800MHZ_DDR_800MHZ, |
| 220 | CPU_RESERVED_DDR_RESERVED1, |
| 221 | CPU_RESERVED_DDR_RESERVED2, |
| 222 | CPU_RESERVED_DDR_RESERVED3, |
| 223 | LAST_FREQ |
| 224 | }; |
| 225 | |
| 226 | /* struct used for DLB configuration array */ |
| 227 | struct dlb_config { |
| 228 | u32 reg_addr; |
| 229 | u32 reg_data; |
| 230 | }; |
| 231 | |
| 232 | #define ACTIVE_INTERFACE_MASK 0x1 |
| 233 | |
| 234 | extern u32 dmin_phy_reg_table[][2]; |
| 235 | extern u16 odt_slope[]; |
| 236 | extern u16 odt_intercept[]; |
| 237 | |
| 238 | int mv_ddr_pre_training_soc_config(const char *ddr_type); |
| 239 | int mv_ddr_post_training_soc_config(const char *ddr_type); |
| 240 | void mv_ddr_mem_scrubbing(void); |
Chris Packham | 4bf81db | 2018-12-03 14:26:49 +1300 | [diff] [blame] | 241 | u32 mv_ddr_init_freq_get(void); |
Chris Packham | 1a07d21 | 2018-05-10 13:28:29 +1200 | [diff] [blame] | 242 | void mv_ddr_odpg_enable(void); |
| 243 | void mv_ddr_odpg_disable(void); |
| 244 | void mv_ddr_odpg_done_clr(void); |
| 245 | int mv_ddr_is_odpg_done(u32 count); |
| 246 | void mv_ddr_training_enable(void); |
| 247 | int mv_ddr_is_training_done(u32 count, u32 *result); |
| 248 | u32 mv_ddr_dm_pad_get(void); |
| 249 | int mv_ddr_pre_training_fixup(void); |
| 250 | int mv_ddr_post_training_fixup(void); |
| 251 | int mv_ddr_manual_cal_do(void); |
Chris Packham | 915f8ee | 2018-05-10 13:28:31 +1200 | [diff] [blame] | 252 | int ddr3_calc_mem_cs_size(u32 cs, uint64_t *cs_size); |
Chris Packham | 4bf81db | 2018-12-03 14:26:49 +1300 | [diff] [blame] | 253 | |
Chris Packham | 1a07d21 | 2018-05-10 13:28:29 +1200 | [diff] [blame] | 254 | #endif /* _MV_DDR_PLAT_H */ |