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git01.mediatek.com / filogic / uboot / e2ba093bb8786423664a289f91a4fa42840f43af / . / include / configs / smdkv310.h
blob: 13e81ee2ffedc2836dcc656980f954bc8f4ea665 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000[diff] [blame]2/*
3 * Copyright (C) 2011 Samsung Electronics
4 *
Chander Kashyap4131a772011-12-06 23:34:12 +0000[diff] [blame]5 * Configuration settings for the SAMSUNG SMDKV310 (EXYNOS4210) board.
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000[diff] [blame]6 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
Simon Glass05b3bac32014-10-07 22:01:49 -0600[diff] [blame]11#include "exynos4-common.h"
12
13#undef CONFIG_BOARD_COMMON
Marek Vasutbc623f22015-08-19 23:27:26 +0200[diff] [blame]14#undef CONFIG_USB_GADGET_DWC2_OTG_PHY
Simon Glass05b3bac32014-10-07 22:01:49 -0600[diff] [blame]15#undef CONFIG_REVISION_TAG
Simon Glass05b3bac32014-10-07 22:01:49 -0600[diff] [blame]16
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000[diff] [blame]17/* High Level Configuration Options */
Chander Kashyap4131a772011-12-06 23:34:12 +0000[diff] [blame]18#define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000[diff] [blame]19
Chander Kashyap0f3e95f2011-09-20 21:25:01 +0000[diff] [blame]20/* Mach Type */
21#define CONFIG_MACH_TYPE MACH_TYPE_SMDKV310
22
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000[diff] [blame]23#define CONFIG_SYS_SDRAM_BASE 0x40000000
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000[diff] [blame]24
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000[diff] [blame]25/* Handling Sleep Mode*/
26#define S5P_CHECK_SLEEP 0x00000BAD
27#define S5P_CHECK_DIDLE 0xBAD00000
Rajeshwari Shindebed24422013-07-04 12:29:17 +0530[diff] [blame]28#define S5P_CHECK_LPA 0xABAD0000
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000[diff] [blame]29
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000[diff] [blame]30/* select serial console configuration */
Chander Kashyap4131a772011-12-06 23:34:12 +0000[diff] [blame]31#define EXYNOS4_DEFAULT_UART_OFFSET 0x010000
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000[diff] [blame]32
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000[diff] [blame]33/* allow to overwrite serial and ethaddr */
34#define CONFIG_ENV_OVERWRITE
35
Chander Kashyap0cd984c2011-09-20 21:25:03 +0000[diff] [blame]36/* MMC SPL */
Rajeshwari Shindebed24422013-07-04 12:29:17 +0530[diff] [blame]37#define CONFIG_SKIP_LOWLEVEL_INIT
Chander Kashyape8d043e2011-09-20 21:25:04 +0000[diff] [blame]38#define COPY_BL2_FNPTR_ADDR 0x00002488
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000[diff] [blame]39
40#define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000"
41
42/* Miscellaneous configurable options */
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000[diff] [blame]43#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000[diff] [blame]44/* memtest works on */
45#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
46#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000)
47#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
48
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000[diff] [blame]49/* SMDKV310 has 4 bank of DRAM */
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000[diff] [blame]50#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */
51#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
52#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
53#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
54#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
55#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
56#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
57#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
58#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
59
60/* FLASH and environment organization */
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000[diff] [blame]61
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000[diff] [blame]62#define CONFIG_CLK_1000_400_200
63
64/* MIU (Memory Interleaving Unit) */
65#define CONFIG_MIU_2BIT_INTERLEAVED
66
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000[diff] [blame]67#define CONFIG_SYS_MMC_ENV_DEV 0
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000[diff] [blame]68#define RESERVE_BLOCK_SIZE (512)
69#define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000[diff] [blame]70
Rajeshwari Shindebed24422013-07-04 12:29:17 +0530[diff] [blame]71#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024)
72
73#define CONFIG_SYS_INIT_SP_ADDR 0x02040000
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000[diff] [blame]74
Bin Meng75574052016-02-05 19:30:11 -0800[diff] [blame]75/* U-Boot copy size from boot Media to DRAM.*/
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000[diff] [blame]76#define COPY_BL2_SIZE 0x80000
77#define BL2_START_OFFSET ((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512)
78#define BL2_SIZE_BLOC_COUNT (COPY_BL2_SIZE/512)
79
80/* Ethernet Controllor Driver */
81#ifdef CONFIG_CMD_NET
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000[diff] [blame]82#define CONFIG_ENV_SROM_BANK 1
83#endif /*CONFIG_CMD_NET*/
Thomas Abraham4cd38a42011-06-03 22:52:17 +0000[diff] [blame]84
Chander Kashyapbfef54d2011-05-24 20:02:56 +0000[diff] [blame]85#endif /* __CONFIG_H */