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git01.mediatek.com / filogic / uboot / e2a19f450b74e812c150b67650e0914dd11809a3 / . / arch / arm / cpu / pxa / usb.c
blob: 80a5977415502d2301ead921cdbfc6ebeb14dfad [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Markus Klotzbuecher98095512006-05-23 10:33:11 +0200[diff] [blame]2/*
3 * (C) Copyright 2006
4 * Markus Klotzbuecher, DENX Software Engineering <mk@denx.de>
Markus Klotzbuecher98095512006-05-23 10:33:11 +0200[diff] [blame]5 */
6
7#include <common.h>
Markus Klotzbuecher98095512006-05-23 10:33:11 +0200[diff] [blame]8
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]9#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
Marek Vasut85cc88a2011-11-26 07:20:07 +0100[diff] [blame]10# if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_CPU_PXA27X)
Markus Klotzbuecherd0a38782006-05-23 13:38:35 +0200[diff] [blame]11
12#include <asm/arch/pxa-regs.h>
Marek Vasut2db1e962010-09-09 09:50:39 +0200[diff] [blame]13#include <asm/io.h>
Jean-Christophe PLAGNIOL-VILLARDbce7b142007-10-19 10:55:24 +0200[diff] [blame]14#include <usb.h>
Markus Klotzbuecherd0a38782006-05-23 13:38:35 +0200[diff] [blame]15
Jean-Christophe PLAGNIOL-VILLARD733fc372007-10-19 08:10:15 +0200[diff] [blame]16int usb_cpu_init(void)
Markus Klotzbuecher98095512006-05-23 10:33:11 +0200[diff] [blame]17{
Rodolfo Giometti6659da82007-03-26 12:03:36 +0200[diff] [blame]18#if defined(CONFIG_CPU_MONAHANS)
Markus Klotzbuecher98095512006-05-23 10:33:11 +0200[diff] [blame]19 /* Enable USB host clock. */
Marek Vasut2db1e962010-09-09 09:50:39 +0200[diff] [blame]20 writel(readl(CKENA) | CKENA_2_USBHOST | CKENA_20_UDC, CKENA);
Markus Klotzbuecher98095512006-05-23 10:33:11 +0200[diff] [blame]21 udelay(100);
Rodolfo Giometti6659da82007-03-26 12:03:36 +0200[diff] [blame]22#endif
Marek Vasut85cc88a2011-11-26 07:20:07 +0100[diff] [blame]23#if defined(CONFIG_CPU_PXA27X)
Rodolfo Giometti6659da82007-03-26 12:03:36 +0200[diff] [blame]24 /* Enable USB host clock. */
Marek Vasut2db1e962010-09-09 09:50:39 +0200[diff] [blame]25 writel(readl(CKEN) | CKEN10_USBHOST, CKEN);
Rodolfo Giometti6659da82007-03-26 12:03:36 +0200[diff] [blame]26#endif
Markus Klotzbuecher98095512006-05-23 10:33:11 +0200[diff] [blame]27
Markus Klotzbuecher4a7847b2007-04-03 14:27:08 +0200[diff] [blame]28#if defined(CONFIG_CPU_MONAHANS)
Markus Klotzbuecher98095512006-05-23 10:33:11 +0200[diff] [blame]29 /* Configure Port 2 for Host (USB Client Registers) */
Marek Vasut2db1e962010-09-09 09:50:39 +0200[diff] [blame]30 writel(0x3000c, UP2OCR);
Markus Klotzbuecher98095512006-05-23 10:33:11 +0200[diff] [blame]31#endif
32
Marek Vasut2db1e962010-09-09 09:50:39 +0200[diff] [blame]33 writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
Mike Frysinger60ce19a2012-03-05 13:47:00 +0000[diff] [blame]34 mdelay(11);
Marek Vasut2db1e962010-09-09 09:50:39 +0200[diff] [blame]35 writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
Markus Klotzbuecher98095512006-05-23 10:33:11 +0200[diff] [blame]36
Marek Vasut2db1e962010-09-09 09:50:39 +0200[diff] [blame]37 writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
38 while (readl(UHCHR) & UHCHR_FSBIR)
Markus Klotzbuecher98095512006-05-23 10:33:11 +0200[diff] [blame]39 udelay(1);
40
Stefan Herbrechtsmeier13d240f2011-10-17 17:22:47 +0200[diff] [blame]41#if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
Marek Vasut2db1e962010-09-09 09:50:39 +0200[diff] [blame]42 writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR);
Rodolfo Giometti6659da82007-03-26 12:03:36 +0200[diff] [blame]43#endif
Marek Vasut85cc88a2011-11-26 07:20:07 +0100[diff] [blame]44#if defined(CONFIG_CPU_PXA27X)
Marek Vasut2db1e962010-09-09 09:50:39 +0200[diff] [blame]45 writel(readl(UHCHR) & ~UHCHR_SSEP2, UHCHR);
Rodolfo Giometti6659da82007-03-26 12:03:36 +0200[diff] [blame]46#endif
Marek Vasut2db1e962010-09-09 09:50:39 +0200[diff] [blame]47 writel(readl(UHCHR) & ~(UHCHR_SSEP1 | UHCHR_SSE), UHCHR);
Markus Klotzbuecher98095512006-05-23 10:33:11 +0200[diff] [blame]48
49 return 0;
50}
51
Jean-Christophe PLAGNIOL-VILLARD733fc372007-10-19 08:10:15 +0200[diff] [blame]52int usb_cpu_stop(void)
Markus Klotzbuecher98095512006-05-23 10:33:11 +0200[diff] [blame]53{
Marek Vasut2db1e962010-09-09 09:50:39 +0200[diff] [blame]54 writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
Rodolfo Giomettidae6b7a2007-10-15 11:59:17 +0200[diff] [blame]55 udelay(11);
Marek Vasut2db1e962010-09-09 09:50:39 +0200[diff] [blame]56 writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
Rodolfo Giomettidae6b7a2007-10-15 11:59:17 +0200[diff] [blame]57
Stefan Herbrechtsmeier38f79c62011-10-17 17:22:46 +0200[diff] [blame]58 writel(readl(UHCCOMS) | UHCCOMS_HCR, UHCCOMS);
Rodolfo Giomettidae6b7a2007-10-15 11:59:17 +0200[diff] [blame]59 udelay(10);
60
Stefan Herbrechtsmeier13d240f2011-10-17 17:22:47 +0200[diff] [blame]61#if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
Marek Vasut2db1e962010-09-09 09:50:39 +0200[diff] [blame]62 writel(readl(UHCHR) | UHCHR_SSEP0, UHCHR);
Rodolfo Giomettidae6b7a2007-10-15 11:59:17 +0200[diff] [blame]63#endif
Marek Vasut85cc88a2011-11-26 07:20:07 +0100[diff] [blame]64#if defined(CONFIG_CPU_PXA27X)
Marek Vasut2db1e962010-09-09 09:50:39 +0200[diff] [blame]65 writel(readl(UHCHR) | UHCHR_SSEP2, UHCHR);
Rodolfo Giomettidae6b7a2007-10-15 11:59:17 +0200[diff] [blame]66#endif
Marek Vasut2db1e962010-09-09 09:50:39 +0200[diff] [blame]67 writel(readl(UHCHR) | UHCHR_SSEP1 | UHCHR_SSE, UHCHR);
Rodolfo Giometti6416a732007-10-15 11:59:17 +0200[diff] [blame]68
69#if defined(CONFIG_CPU_MONAHANS)
Marek Vasut2db1e962010-09-09 09:50:39 +0200[diff] [blame]70 /* Disable USB host clock. */
71 writel(readl(CKENA) & ~(CKENA_2_USBHOST | CKENA_20_UDC), CKENA);
72 udelay(100);
Rodolfo Giometti6416a732007-10-15 11:59:17 +0200[diff] [blame]73#endif
Marek Vasut85cc88a2011-11-26 07:20:07 +0100[diff] [blame]74#if defined(CONFIG_CPU_PXA27X)
Marek Vasut2db1e962010-09-09 09:50:39 +0200[diff] [blame]75 /* Disable USB host clock. */
76 writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
Rodolfo Giometti6416a732007-10-15 11:59:17 +0200[diff] [blame]77#endif
Rodolfo Giometti6416a732007-10-15 11:59:17 +0200[diff] [blame]78
Markus Klotzbuecher98095512006-05-23 10:33:11 +0200[diff] [blame]79 return 0;
80}
Markus Klotzbuecheraa219212006-05-30 16:56:14 +0200[diff] [blame]81
Marek Vasut2db1e962010-09-09 09:50:39 +0200[diff] [blame]82int usb_cpu_init_fail(void)
83{
84 return usb_cpu_stop();
85}
86
Marek Vasut85cc88a2011-11-26 07:20:07 +0100[diff] [blame]87# endif /* defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_CPU_PXA27X) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]88#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */