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Sergey Kubushyne8f39122007-08-10 20:26:18 +02001/*
2 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17 * MA 02111-1307 USA
18 */
19
20#ifndef __CONFIG_H
21#define __CONFIG_H
Sergey Kubushyne8f39122007-08-10 20:26:18 +020022
23/*=======*/
24/* Board */
25/*=======*/
26#define SCHMOOGIE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020027#define CONFIG_SYS_NAND_LARGEPAGE
28#define CONFIG_SYS_USE_NAND
Christian Riesch034a4852011-11-19 00:45:42 +000029#define MACH_TYPE_SCHMOOGIE 1255
30#define CONFIG_MACH_TYPE MACH_TYPE_SCHMOOGIE
31
Sergey Kubushyne8f39122007-08-10 20:26:18 +020032/*===================*/
33/* SoC Configuration */
34/*===================*/
35#define CONFIG_ARM926EJS /* arm926ejs CPU core */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020036#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
37#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
38#define CONFIG_SYS_HZ 1000
David Brownell5f02add2009-05-15 23:44:08 +020039#define CONFIG_SOC_DM644X
Sergey Kubushyne8f39122007-08-10 20:26:18 +020040/*=============*/
41/* Memory Info */
42/*=============*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020043#define CONFIG_SYS_MALLOC_LEN (0x10000 + 256*1024) /* malloc() len */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020044#define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */
45#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */
Sergey Kubushyne8f39122007-08-10 20:26:18 +020046#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
Sergey Kubushyne8f39122007-08-10 20:26:18 +020047#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
48#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
Wolfgang Denka48499f2008-04-11 15:11:26 +020049#define DDR_4BANKS /* 4-bank DDR2 (128MB) */
Sergey Kubushyne8f39122007-08-10 20:26:18 +020050/*====================*/
51/* Serial Driver info */
52/*====================*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020053#define CONFIG_SYS_NS16550
54#define CONFIG_SYS_NS16550_SERIAL
David Brownellfedd22d2009-04-12 15:38:06 -070055#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020056#define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */
David Brownell1fc59072009-04-12 15:40:16 -070057#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK /* Input clock to NS16550 */
Sergey Kubushyne8f39122007-08-10 20:26:18 +020058#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
59#define CONFIG_BAUDRATE 115200 /* Default baud rate */
Sergey Kubushyne8f39122007-08-10 20:26:18 +020060/*===================*/
61/* I2C Configuration */
62/*===================*/
63#define CONFIG_HARD_I2C
64#define CONFIG_DRIVER_DAVINCI_I2C
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020065#define CONFIG_SYS_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
66#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
Sergey Kubushyne8f39122007-08-10 20:26:18 +020067/*==================================*/
68/* Network & Ethernet Configuration */
69/*==================================*/
70#define CONFIG_DRIVER_TI_EMAC
71#define CONFIG_MII
72#define CONFIG_BOOTP_DEFAULT
73#define CONFIG_BOOTP_DNS
74#define CONFIG_BOOTP_DNS2
75#define CONFIG_BOOTP_SEND_HOSTNAME
76#define CONFIG_NET_RETRY_COUNT 10
77#define CONFIG_OVERWRITE_ETHADDR_ONCE
78/*=====================*/
79/* Flash & Environment */
80/*=====================*/
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +020081#undef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020082#define CONFIG_SYS_NO_FLASH
Jean-Christophe PLAGNIOL-VILLARDf6812502009-03-30 18:58:39 +020083#define CONFIG_NAND_DAVINCI
Nick Thompson789c8872009-12-12 12:12:26 -050084#define CONFIG_SYS_NAND_CS 2
Jean-Christophe PLAGNIOL-VILLARDdda84dd2008-09-10 22:47:58 +020085#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +020086#define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */
Sandeep Paulraj391d1a62009-09-08 17:09:52 -040087#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
Sergey Kubushyne8f39122007-08-10 20:26:18 +020088#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020089#define CONFIG_SYS_NAND_BASE 0x02000000
90#define CONFIG_SYS_NAND_HW_ECC
91#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +020092#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
Sergey Kubushyne8f39122007-08-10 20:26:18 +020093/*=====================*/
94/* Board related stuff */
95/*=====================*/
96#define CONFIG_RTC_DS1307 /* RTC chip on SCHMOOGIE */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020097#define CONFIG_SYS_I2C_RTC_ADDR 0x6f /* RTC chip I2C address */
Sergey Kubushyne8f39122007-08-10 20:26:18 +020098#define CONFIG_UID_DS28CM00 /* Unique ID on SCHMOOGIE */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020099#define CONFIG_SYS_UID_ADDR 0x50 /* UID chip I2C address */
Sergey Kubushyne8f39122007-08-10 20:26:18 +0200100/*==============================*/
101/* U-Boot general configuration */
102/*==============================*/
Sergey Kubushyne8f39122007-08-10 20:26:18 +0200103#define CONFIG_MISC_INIT_R
104#undef CONFIG_BOOTDELAY
105#define CONFIG_BOOTFILE "uImage" /* Boot file name */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200106#define CONFIG_SYS_PROMPT "U-Boot > " /* Monitor Command Prompt */
107#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
108#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buffer sz */
109#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
110#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
111#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* default Linux kernel load address */
Sergey Kubushyne8f39122007-08-10 20:26:18 +0200112#define CONFIG_VERSION_VARIABLE
113#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200114#define CONFIG_SYS_HUSH_PARSER
Sergey Kubushyne8f39122007-08-10 20:26:18 +0200115#define CONFIG_CMDLINE_EDITING
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200116#define CONFIG_SYS_LONGHELP
Sergey Kubushyne8f39122007-08-10 20:26:18 +0200117#define CONFIG_CRC32_VERIFY
118#define CONFIG_MX_CYCLIC
119/*===================*/
120/* Linux Information */
121/*===================*/
122#define LINUX_BOOT_PARAM_ADDR 0x80000100
123#define CONFIG_CMDLINE_TAG
124#define CONFIG_SETUP_MEMORY_TAGS
125#define CONFIG_BOOTARGS "mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp"
126#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot"
127/*=================*/
128/* U-Boot commands */
129/*=================*/
130#include <config_cmd_default.h>
131#define CONFIG_CMD_ASKENV
132#define CONFIG_CMD_DHCP
133#define CONFIG_CMD_DIAG
134#define CONFIG_CMD_I2C
135#define CONFIG_CMD_MII
136#define CONFIG_CMD_PING
137#define CONFIG_CMD_SAVES
138#define CONFIG_CMD_DATE
139#define CONFIG_CMD_NAND
140#undef CONFIG_CMD_EEPROM
141#undef CONFIG_CMD_BDI
142#undef CONFIG_CMD_FPGA
143#undef CONFIG_CMD_SETGETDCR
144#undef CONFIG_CMD_FLASH
145#undef CONFIG_CMD_IMLS
Sandeep Paulrajada0a222010-12-11 20:38:35 -0500146
Hadli, Manjunath0dfccbe2012-02-06 00:30:44 +0000147#ifdef CONFIG_CMD_BDI
148#define CONFIG_CLOCKS
149#endif
150
Sandeep Paulrajada0a222010-12-11 20:38:35 -0500151#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
152
153#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
154#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
155#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
156 CONFIG_SYS_INIT_RAM_SIZE - \
157 GENERATED_GBL_DATA_SIZE)
158
Sergey Kubushyne8f39122007-08-10 20:26:18 +0200159#endif /* __CONFIG_H */