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git01.mediatek.com / filogic / uboot / e1e30b242ba979879e77d872befa46875973c33f / . / configs / clearfog_defconfig
blob: f613107ccdd56eac452d86851ba4e94523bf087d [file] [log] [blame]
Stefan Roese73606402015-10-20 15:14:47 +0200[diff] [blame]1CONFIG_ARM=y
Tom Rinie1e85442021-08-27 21:18:30 -0400[diff] [blame]2CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
Adam Fordd36b1022019-08-14 08:29:25 -0500[diff] [blame]3CONFIG_ARCH_CPU_INIT=y
Tom Rinicbdc07d2018-11-16 13:32:59 -0500[diff] [blame]4CONFIG_SYS_THUMB_BUILD=y
Stefan Roese73606402015-10-20 15:14:47 +0200[diff] [blame]5CONFIG_ARCH_MVEBU=y
Tom Rini07edfae2018-02-03 12:10:38 -0500[diff] [blame]6CONFIG_SYS_TEXT_BASE=0x00800000
Simon Glassf2a89462016-09-12 23:18:41 -0600[diff] [blame]7CONFIG_SPL_LIBCOMMON_SUPPORT=y
Simon Glassb16c92c2016-09-12 23:18:43 -0600[diff] [blame]8CONFIG_SPL_LIBGENERIC_SUPPORT=y
Masahiro Yamada75794f92016-09-19 21:40:26 +0900[diff] [blame]9CONFIG_SYS_MALLOC_F_LEN=0x2000
Tom Rini2e262c42020-08-10 15:31:07 -0400[diff] [blame]10CONFIG_NR_DRAM_BANKS=2
Stefan Roese73606402015-10-20 15:14:47 +0200[diff] [blame]11CONFIG_TARGET_CLEARFOG=y
Baruch Siachea3d9de2018-06-18 21:56:25 +0300[diff] [blame]12CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC=y
Tom Rinif6e6e1a2020-01-22 13:38:00 -0500[diff] [blame]13CONFIG_DM_GPIO=y
Tom Rinia20e51f2021-06-28 10:17:29 -0400[diff] [blame]14CONFIG_DEFAULT_DEVICE_TREE="armada-388-clearfog"
Tom Rini0332a1a2020-07-06 13:54:25 -0400[diff] [blame]15CONFIG_SPL_TEXT_BASE=0x40000030
Simon Glassf4d60392021-08-08 12:20:12 -0600[diff] [blame]16CONFIG_SPL_SERIAL=y
Tom Rini9bd09622018-04-07 20:27:54 -0400[diff] [blame]17CONFIG_SPL=y
Tom Rinie0056d72018-06-04 11:57:37 -0400[diff] [blame]18CONFIG_DEBUG_UART_BASE=0xd0012000
19CONFIG_DEBUG_UART_CLOCK=250000000
Tom Rini256aa742017-06-19 09:47:40 -0400[diff] [blame]20CONFIG_DEBUG_UART=y
Stefan Roese5caf1082019-05-03 08:42:17 +0200[diff] [blame]21CONFIG_AHCI=y
Patrick Wildt7e5b0192017-05-10 15:12:34 +0200[diff] [blame]22CONFIG_DISTRO_DEFAULTS=y
Tom Rini0997ee02021-08-23 10:25:31 -0400[diff] [blame]23CONFIG_SYS_LOAD_ADDR=0x800000
Heiko Schocher0b368b12016-06-07 08:31:14 +0200[diff] [blame]24CONFIG_BOOTDELAY=3
Simon Glass4be229d2019-07-20 20:51:14 -0600[diff] [blame]25CONFIG_USE_PREBOOT=y
Simon Glassbd5618d2016-10-17 20:13:00 -0600[diff] [blame]26CONFIG_SYS_CONSOLE_INFO_QUIET=y
Lokesh Vutla94d95e42016-10-11 21:33:46 -0400[diff] [blame]27# CONFIG_DISPLAY_BOARDINFO is not set
Mario Sixf7055442018-03-28 14:38:17 +0200[diff] [blame]28CONFIG_DISPLAY_BOARDINFO_LATE=y
Simon Glassbccfc2e2021-07-10 21:14:36 -0600[diff] [blame]29CONFIG_SPL_I2C=y
Baruch Siachb5283272020-01-20 14:20:10 +0200[diff] [blame]30CONFIG_CMD_TLV_EEPROM=y
31CONFIG_SPL_CMD_TLV_EEPROM=y
Stefan Roese73606402015-10-20 15:14:47 +0200[diff] [blame]32# CONFIG_CMD_FLASH is not set
Jon Nettleton959b07e2018-05-28 19:10:30 +0300[diff] [blame]33CONFIG_CMD_GPIO=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]34CONFIG_CMD_I2C=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]35CONFIG_CMD_MMC=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]36CONFIG_CMD_PCI=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]37CONFIG_CMD_SPI=y
Stefan Roese73606402015-10-20 15:14:47 +0200[diff] [blame]38CONFIG_CMD_USB=y
39# CONFIG_CMD_SETEXPR is not set
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]40CONFIG_CMD_TFTPPUT=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]41CONFIG_CMD_CACHE=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]42CONFIG_CMD_TIME=y
Tom Rini47dece32020-04-28 16:15:47 -0400[diff] [blame]43CONFIG_CMD_MVEBU_BUBT=y
Patrick Delaunay73287092017-01-27 11:00:42 +0100[diff] [blame]44# CONFIG_SPL_PARTITION_UUIDS is not set
Adam Ford710966e2020-07-03 06:48:56 -0500[diff] [blame]45CONFIG_ENV_OVERWRITE=y
Baruch Siachb183c352018-02-19 08:17:22 +0200[diff] [blame]46CONFIG_NET_RANDOM_ETHADDR=y
Stefan Roese73606402015-10-20 15:14:47 +0200[diff] [blame]47CONFIG_SPL_OF_TRANSLATE=y
Stefan Roese5caf1082019-05-03 08:42:17 +0200[diff] [blame]48CONFIG_AHCI_MVEBU=y
Jon Nettleton959b07e2018-05-28 19:10:30 +0300[diff] [blame]49CONFIG_DM_PCA953X=y
50CONFIG_DM_I2C=y
51CONFIG_SYS_I2C_MVTWSI=y
Baruch Siachb5283272020-01-20 14:20:10 +0200[diff] [blame]52CONFIG_I2C_EEPROM=y
53CONFIG_SPL_I2C_EEPROM=y
Tom Rini66ea5c72019-05-26 14:45:25 -0400[diff] [blame]54CONFIG_SUPPORT_EMMC_BOOT=y
Masahiro Yamada7db8c172016-12-07 22:10:28 +0900[diff] [blame]55CONFIG_MMC_SDHCI=y
Masahiro Yamada124f6ce2016-12-07 22:10:29 +0900[diff] [blame]56CONFIG_MMC_SDHCI_SDMA=y
57CONFIG_MMC_SDHCI_MV=y
Tom Rinie799f922019-12-04 17:18:38 -0500[diff] [blame]58CONFIG_MTD=y
Patrick Delaunay0df81042019-02-27 15:20:36 +0100[diff] [blame]59CONFIG_SF_DEFAULT_BUS=1
Tom Rinib9baf7f2017-12-18 20:19:09 -0500[diff] [blame]60CONFIG_SPI_FLASH_WINBOND=y
61CONFIG_SPI_FLASH_MTD=y
Mario Sixf504d1a2018-04-27 14:52:21 +0200[diff] [blame]62CONFIG_PHY_MARVELL=y
Tom Rinica22e962017-08-07 22:00:34 -0400[diff] [blame]63CONFIG_PHY_GIGE=y
Chris Packham919041c2017-08-21 20:17:03 +1200[diff] [blame]64CONFIG_MVNETA=y
Adam Ford53705472018-07-20 23:03:57 -0500[diff] [blame]65CONFIG_MII=y
Tom Rinif48e0252016-10-26 17:15:37 -0400[diff] [blame]66CONFIG_PCI=y
Stefan Roese3179ec62019-01-25 11:52:43 +0100[diff] [blame]67CONFIG_PCI_MVEBU=y
Jon Nettleton7a3315e2018-05-28 13:35:15 +0300[diff] [blame]68CONFIG_SCSI=y
Stefan Roese73606402015-10-20 15:14:47 +0200[diff] [blame]69CONFIG_DEBUG_UART_SHIFT=2
70CONFIG_SYS_NS16550=y
Tuomas Tynkkynen13b5cb82018-02-07 02:42:22 +0200[diff] [blame]71CONFIG_KIRKWOOD_SPI=y
Stefan Roese73606402015-10-20 15:14:47 +0200[diff] [blame]72CONFIG_USB=y
Jon Nettleton31c0d3b2017-11-06 10:33:21 +0200[diff] [blame]73CONFIG_USB_XHCI_HCD=y